arch/s390/include/asm/processor.h

   1 /*
   2  *  S390 version
   3  *    Copyright IBM Corp. 1999
   4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
   5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   6  *
   7  *  Derived from "include/asm-i386/processor.h"
   8  *    Copyright (C) 1994, Linus Torvalds
   9  */
  10
  11 #ifndef __ASM_S390_PROCESSOR_H
  12 #define __ASM_S390_PROCESSOR_H
  13
  14 #include <linux/linkage.h>
  15 #include <linux/irqflags.h>
  16 #include <asm/cpu.h>
  17 #include <asm/page.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/setup.h>
  20
  21 /*
  22  * Default implementation of macro that returns current
  23  * instruction pointer ("program counter").
  24  */
  25 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  26
  27 static inline void get_cpu_id(struct cpuid *ptr)
  28 {
  29         asm volatile("stidp %0" : "=Q" (*ptr));
  30 }
  31
  32 extern void s390_adjust_jiffies(void);
  33 extern const struct seq_operations cpuinfo_op;
  34 extern int sysctl_ieee_emulation_warnings;
  35
  36 /*
  37  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  38  */
  39 #ifndef CONFIG_64BIT
  40
  41 #define TASK_SIZE               (1UL << 31)
  42 #define TASK_UNMAPPED_BASE      (1UL << 30)
  43
  44 #else /* CONFIG_64BIT */
  45
  46 #define TASK_SIZE_OF(tsk)       ((tsk)->mm->context.asce_limit)
  47 #define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  48                                         (1UL << 30) : (1UL << 41))
  49 #define TASK_SIZE               TASK_SIZE_OF(current)
  50
  51 #endif /* CONFIG_64BIT */
  52
  53 #ifndef CONFIG_64BIT
  54 #define STACK_TOP               (1UL << 31)
  55 #define STACK_TOP_MAX           (1UL << 31)
  56 #else /* CONFIG_64BIT */
  57 #define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  58 #define STACK_TOP_MAX           (1UL << 42)
  59 #endif /* CONFIG_64BIT */
  60
  61 #define HAVE_ARCH_PICK_MMAP_LAYOUT
  62
  63 typedef struct {
  64         __u32 ar4;
  65 } mm_segment_t;
  66
  67 /*
  68  * Thread structure
  69  */
  70 struct thread_struct {
  71         s390_fp_regs fp_regs;
  72         unsigned int  acrs[NUM_ACRS];
  73         unsigned long ksp;              /* kernel stack pointer             */
  74         mm_segment_t mm_segment;
  75         unsigned long gmap_addr;        /* address of last gmap fault. */
  76         struct per_regs per_user;       /* User specified PER registers */
  77         struct per_event per_event;     /* Cause of the last PER trap */
  78         /* pfault_wait is used to block the process on a pfault event */
  79         unsigned long pfault_wait;
  80         struct list_head list;
  81 };
  82
  83 typedef struct thread_struct thread_struct;
  84
  85 /*
  86  * Stack layout of a C stack frame.
  87  */
  88 #ifndef __PACK_STACK
  89 struct stack_frame {
  90         unsigned long back_chain;
  91         unsigned long empty1[5];
  92         unsigned long gprs[10];
  93         unsigned int  empty2[8];
  94 };
  95 #else
  96 struct stack_frame {
  97         unsigned long empty1[5];
  98         unsigned int  empty2[8];
  99         unsigned long gprs[10];
 100         unsigned long back_chain;
 101 };
 102 #endif
 103
 104 #define ARCH_MIN_TASKALIGN      8
 105
 106 #define INIT_THREAD {                                                   \
 107         .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 108 }
 109
 110 /*
 111  * Do necessary setup to start up a new thread.
 112  */
 113 #define start_thread(regs, new_psw, new_stackp) do {                    \
 114         regs->psw.mask  = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA;    \
 115         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 116         regs->gprs[15]  = new_stackp;                                   \
 117 } while (0)
 118
 119 #define start_thread31(regs, new_psw, new_stackp) do {                  \
 120         regs->psw.mask  = psw_user_bits | PSW_MASK_BA;                  \
 121         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 122         regs->gprs[15]  = new_stackp;                                   \
 123         crst_table_downgrade(current->mm, 1UL << 31);                   \
 124 } while (0)
 125
 126 /* Forward declaration, a strange C thing */
 127 struct task_struct;
 128 struct mm_struct;
 129 struct seq_file;
 130
 131 /* Free all resources held by a thread. */
 132 extern void release_thread(struct task_struct *);
 133 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 134
 135 /*
 136  * Return saved PC of a blocked thread.
 137  */
 138 extern unsigned long thread_saved_pc(struct task_struct *t);
 139
 140 extern void show_code(struct pt_regs *regs);
 141 extern int insn_to_mnemonic(unsigned char *instruction, char buf[8]);
 142
 143 unsigned long get_wchan(struct task_struct *p);
 144 #define task_pt_regs(tsk) ((struct pt_regs *) \
 145         (task_stack_page(tsk) + THREAD_SIZE) - 1)
 146 #define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 147 #define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 148
 149 static inline unsigned short stap(void)
 150 {
 151         unsigned short cpu_address;
 152
 153         asm volatile("stap %0" : "=m" (cpu_address));
 154         return cpu_address;
 155 }
 156
 157 /*
 158  * Give up the time slice of the virtual PU.
 159  */
 160 static inline void cpu_relax(void)
 161 {
 162         if (MACHINE_HAS_DIAG44)
 163                 asm volatile("diag 0,0,68");
 164         barrier();
 165 }
 166
 167 static inline void psw_set_key(unsigned int key)
 168 {
 169         asm volatile("spka 0(%0)" : : "d" (key));
 170 }
 171
 172 /*
 173  * Set PSW to specified value.
 174  */
 175 static inline void __load_psw(psw_t psw)
 176 {
 177 #ifndef CONFIG_64BIT
 178         asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
 179 #else
 180         asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 181 #endif
 182 }
 183
 184 /*
 185  * Set PSW mask to specified value, while leaving the
 186  * PSW addr pointing to the next instruction.
 187  */
 188 static inline void __load_psw_mask (unsigned long mask)
 189 {
 190         unsigned long addr;
 191         psw_t psw;
 192
 193         psw.mask = mask;
 194
 195 #ifndef CONFIG_64BIT
 196         asm volatile(
 197                 "       basr    %0,0\n"
 198                 "0:     ahi     %0,1f-0b\n"
 199                 "       st      %0,%O1+4(%R1)\n"
 200                 "       lpsw    %1\n"
 201                 "1:"
 202                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 203 #else /* CONFIG_64BIT */
 204         asm volatile(
 205                 "       larl    %0,1f\n"
 206                 "       stg     %0,%O1+8(%R1)\n"
 207                 "       lpswe   %1\n"
 208                 "1:"
 209                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 210 #endif /* CONFIG_64BIT */
 211 }
 212
 213 /*
 214  * Rewind PSW instruction address by specified number of bytes.
 215  */
 216 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 217 {
 218 #ifndef CONFIG_64BIT
 219         if (psw.addr & PSW_ADDR_AMODE)
 220                 /* 31 bit mode */
 221                 return (psw.addr - ilc) | PSW_ADDR_AMODE;
 222         /* 24 bit mode */
 223         return (psw.addr - ilc) & ((1UL << 24) - 1);
 224 #else
 225         unsigned long mask;
 226
 227         mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 228                (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 229                                           (1UL << 24) - 1;
 230         return (psw.addr - ilc) & mask;
 231 #endif
 232 }
 233
 234 /*
 235  * Function to drop a processor into disabled wait state
 236  */
 237 static inline void __noreturn disabled_wait(unsigned long code)
 238 {
 239         unsigned long ctl_buf;
 240         psw_t dw_psw;
 241
 242         dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 243         dw_psw.addr = code;
 244         /*
 245          * Store status and then load disabled wait psw,
 246          * the processor is dead afterwards
 247          */
 248 #ifndef CONFIG_64BIT
 249         asm volatile(
 250                 "       stctl   0,0,0(%2)\n"
 251                 "       ni      0(%2),0xef\n"   /* switch off protection */
 252                 "       lctl    0,0,0(%2)\n"
 253                 "       stpt    0xd8\n"         /* store timer */
 254                 "       stckc   0xe0\n"         /* store clock comparator */
 255                 "       stpx    0x108\n"        /* store prefix register */
 256                 "       stam    0,15,0x120\n"   /* store access registers */
 257                 "       std     0,0x160\n"      /* store f0 */
 258                 "       std     2,0x168\n"      /* store f2 */
 259                 "       std     4,0x170\n"      /* store f4 */
 260                 "       std     6,0x178\n"      /* store f6 */
 261                 "       stm     0,15,0x180\n"   /* store general registers */
 262                 "       stctl   0,15,0x1c0\n"   /* store control registers */
 263                 "       oi      0x1c0,0x10\n"   /* fake protection bit */
 264                 "       lpsw    0(%1)"
 265                 : "=m" (ctl_buf)
 266                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
 267 #else /* CONFIG_64BIT */
 268         asm volatile(
 269                 "       stctg   0,0,0(%2)\n"
 270                 "       ni      4(%2),0xef\n"   /* switch off protection */
 271                 "       lctlg   0,0,0(%2)\n"
 272                 "       lghi    1,0x1000\n"
 273                 "       stpt    0x328(1)\n"     /* store timer */
 274                 "       stckc   0x330(1)\n"     /* store clock comparator */
 275                 "       stpx    0x318(1)\n"     /* store prefix register */
 276                 "       stam    0,15,0x340(1)\n"/* store access registers */
 277                 "       stfpc   0x31c(1)\n"     /* store fpu control */
 278                 "       std     0,0x200(1)\n"   /* store f0 */
 279                 "       std     1,0x208(1)\n"   /* store f1 */
 280                 "       std     2,0x210(1)\n"   /* store f2 */
 281                 "       std     3,0x218(1)\n"   /* store f3 */
 282                 "       std     4,0x220(1)\n"   /* store f4 */
 283                 "       std     5,0x228(1)\n"   /* store f5 */
 284                 "       std     6,0x230(1)\n"   /* store f6 */
 285                 "       std     7,0x238(1)\n"   /* store f7 */
 286                 "       std     8,0x240(1)\n"   /* store f8 */
 287                 "       std     9,0x248(1)\n"   /* store f9 */
 288                 "       std     10,0x250(1)\n"  /* store f10 */
 289                 "       std     11,0x258(1)\n"  /* store f11 */
 290                 "       std     12,0x260(1)\n"  /* store f12 */
 291                 "       std     13,0x268(1)\n"  /* store f13 */
 292                 "       std     14,0x270(1)\n"  /* store f14 */
 293                 "       std     15,0x278(1)\n"  /* store f15 */
 294                 "       stmg    0,15,0x280(1)\n"/* store general registers */
 295                 "       stctg   0,15,0x380(1)\n"/* store control registers */
 296                 "       oi      0x384(1),0x10\n"/* fake protection bit */
 297                 "       lpswe   0(%1)"
 298                 : "=m" (ctl_buf)
 299                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
 300 #endif /* CONFIG_64BIT */
 301         while (1);
 302 }
 303
 304 /*
 305  * Use to set psw mask except for the first byte which
 306  * won't be changed by this function.
 307  */
 308 static inline void
 309 __set_psw_mask(unsigned long mask)
 310 {
 311         __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 312 }
 313
 314 #define local_mcck_enable() \
 315         __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
 316 #define local_mcck_disable() \
 317         __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)
 318
 319 /*
 320  * Basic Machine Check/Program Check Handler.
 321  */
 322
 323 extern void s390_base_mcck_handler(void);
 324 extern void s390_base_pgm_handler(void);
 325 extern void s390_base_ext_handler(void);
 326
 327 extern void (*s390_base_mcck_handler_fn)(void);
 328 extern void (*s390_base_pgm_handler_fn)(void);
 329 extern void (*s390_base_ext_handler_fn)(void);
 330
 331 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 332
 333 /*
 334  * Helper macro for exception table entries
 335  */
 336 #ifndef CONFIG_64BIT
 337 #define EX_TABLE(_fault,_target)                        \
 338         ".section __ex_table,\"a\"\n"                   \
 339         "       .align 4\n"                             \
 340         "       .long  " #_fault "," #_target "\n"      \
 341         ".previous\n"
 342 #else
 343 #define EX_TABLE(_fault,_target)                        \
 344         ".section __ex_table,\"a\"\n"                   \
 345         "       .align 8\n"                             \
 346         "       .quad  " #_fault "," #_target "\n"      \
 347         ".previous\n"
 348 #endif
 349
 350 extern int memcpy_real(void *, void *, size_t);
 351 extern void memcpy_absolute(void *, void *, size_t);
 352
 353 #define mem_assign_absolute(dest, val) {                        \
 354         __typeof__(dest) __tmp = (val);                         \
 355                                                                 \
 356         BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 357         memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 358 }
 359
 360 #endif                                 /* __ASM_S390_PROCESSOR_H           */