arch/s390/include/asm/processor.h

   1 /*
   2  *  S390 version
   3  *    Copyright IBM Corp. 1999
   4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
   5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   6  *
   7  *  Derived from "include/asm-i386/processor.h"
   8  *    Copyright (C) 1994, Linus Torvalds
   9  */
  10
  11 #ifndef __ASM_S390_PROCESSOR_H
  12 #define __ASM_S390_PROCESSOR_H
  13
  14 #ifndef __ASSEMBLY__
  15
  16 #include <linux/linkage.h>
  17 #include <linux/irqflags.h>
  18 #include <asm/cpu.h>
  19 #include <asm/page.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/setup.h>
  22 #include <asm/runtime_instr.h>
  23
  24 /*
  25  * Default implementation of macro that returns current
  26  * instruction pointer ("program counter").
  27  */
  28 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  29
  30 static inline void get_cpu_id(struct cpuid *ptr)
  31 {
  32         asm volatile("stidp %0" : "=Q" (*ptr));
  33 }
  34
  35 extern void s390_adjust_jiffies(void);
  36 extern const struct seq_operations cpuinfo_op;
  37 extern int sysctl_ieee_emulation_warnings;
  38 extern void execve_tail(void);
  39
  40 /*
  41  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  42  */
  43 #ifndef CONFIG_64BIT
  44
  45 #define TASK_SIZE               (1UL << 31)
  46 #define TASK_UNMAPPED_BASE      (1UL << 30)
  47
  48 #else /* CONFIG_64BIT */
  49
  50 #define TASK_SIZE_OF(tsk)       ((tsk)->mm->context.asce_limit)
  51 #define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  52                                         (1UL << 30) : (1UL << 41))
  53 #define TASK_SIZE               TASK_SIZE_OF(current)
  54
  55 #endif /* CONFIG_64BIT */
  56
  57 #ifndef CONFIG_64BIT
  58 #define STACK_TOP               (1UL << 31)
  59 #define STACK_TOP_MAX           (1UL << 31)
  60 #else /* CONFIG_64BIT */
  61 #define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  62 #define STACK_TOP_MAX           (1UL << 42)
  63 #endif /* CONFIG_64BIT */
  64
  65 #define HAVE_ARCH_PICK_MMAP_LAYOUT
  66
  67 typedef struct {
  68         __u32 ar4;
  69 } mm_segment_t;
  70
  71 /*
  72  * Thread structure
  73  */
  74 struct thread_struct {
  75         s390_fp_regs fp_regs;
  76         unsigned int  acrs[NUM_ACRS];
  77         unsigned long ksp;              /* kernel stack pointer             */
  78         mm_segment_t mm_segment;
  79         unsigned long gmap_addr;        /* address of last gmap fault. */
  80         struct per_regs per_user;       /* User specified PER registers */
  81         struct per_event per_event;     /* Cause of the last PER trap */
  82         unsigned long per_flags;        /* Flags to control debug behavior */
  83         /* pfault_wait is used to block the process on a pfault event */
  84         unsigned long pfault_wait;
  85         struct list_head list;
  86         /* cpu runtime instrumentation */
  87         struct runtime_instr_cb *ri_cb;
  88         int ri_signum;
  89 #ifdef CONFIG_64BIT
  90         unsigned char trap_tdb[256];    /* Transaction abort diagnose block */
  91 #endif
  92 };
  93
  94 #define PER_FLAG_NO_TE          1UL     /* Flag to disable transactions. */
  95
  96 typedef struct thread_struct thread_struct;
  97
  98 /*
  99  * Stack layout of a C stack frame.
 100  */
 101 #ifndef __PACK_STACK
 102 struct stack_frame {
 103         unsigned long back_chain;
 104         unsigned long empty1[5];
 105         unsigned long gprs[10];
 106         unsigned int  empty2[8];
 107 };
 108 #else
 109 struct stack_frame {
 110         unsigned long empty1[5];
 111         unsigned int  empty2[8];
 112         unsigned long gprs[10];
 113         unsigned long back_chain;
 114 };
 115 #endif
 116
 117 #define ARCH_MIN_TASKALIGN      8
 118
 119 #define INIT_THREAD {                                                   \
 120         .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 121 }
 122
 123 /*
 124  * Do necessary setup to start up a new thread.
 125  */
 126 #define start_thread(regs, new_psw, new_stackp) do {                    \
 127         regs->psw.mask  = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA;    \
 128         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 129         regs->gprs[15]  = new_stackp;                                   \
 130         execve_tail();                                                  \
 131 } while (0)
 132
 133 #define start_thread31(regs, new_psw, new_stackp) do {                  \
 134         regs->psw.mask  = psw_user_bits | PSW_MASK_BA;                  \
 135         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 136         regs->gprs[15]  = new_stackp;                                   \
 137         __tlb_flush_mm(current->mm);                                    \
 138         crst_table_downgrade(current->mm, 1UL << 31);                   \
 139         update_mm(current->mm, current);                                \
 140         execve_tail();                                                  \
 141 } while (0)
 142
 143 /* Forward declaration, a strange C thing */
 144 struct task_struct;
 145 struct mm_struct;
 146 struct seq_file;
 147
 148 #ifdef CONFIG_64BIT
 149 extern void show_cacheinfo(struct seq_file *m);
 150 #else
 151 static inline void show_cacheinfo(struct seq_file *m) { }
 152 #endif
 153
 154 /* Free all resources held by a thread. */
 155 extern void release_thread(struct task_struct *);
 156
 157 /*
 158  * Return saved PC of a blocked thread.
 159  */
 160 extern unsigned long thread_saved_pc(struct task_struct *t);
 161
 162 extern void show_code(struct pt_regs *regs);
 163 extern void print_fn_code(unsigned char *code, unsigned long len);
 164 extern int insn_to_mnemonic(unsigned char *instruction, char *buf,
 165                             unsigned int len);
 166
 167 unsigned long get_wchan(struct task_struct *p);
 168 #define task_pt_regs(tsk) ((struct pt_regs *) \
 169         (task_stack_page(tsk) + THREAD_SIZE) - 1)
 170 #define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 171 #define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 172
 173 static inline unsigned short stap(void)
 174 {
 175         unsigned short cpu_address;
 176
 177         asm volatile("stap %0" : "=m" (cpu_address));
 178         return cpu_address;
 179 }
 180
 181 /*
 182  * Give up the time slice of the virtual PU.
 183  */
 184 static inline void cpu_relax(void)
 185 {
 186         if (MACHINE_HAS_DIAG44)
 187                 asm volatile("diag 0,0,68");
 188         barrier();
 189 }
 190
 191 static inline void psw_set_key(unsigned int key)
 192 {
 193         asm volatile("spka 0(%0)" : : "d" (key));
 194 }
 195
 196 /*
 197  * Set PSW to specified value.
 198  */
 199 static inline void __load_psw(psw_t psw)
 200 {
 201 #ifndef CONFIG_64BIT
 202         asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
 203 #else
 204         asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 205 #endif
 206 }
 207
 208 /*
 209  * Set PSW mask to specified value, while leaving the
 210  * PSW addr pointing to the next instruction.
 211  */
 212 static inline void __load_psw_mask (unsigned long mask)
 213 {
 214         unsigned long addr;
 215         psw_t psw;
 216
 217         psw.mask = mask;
 218
 219 #ifndef CONFIG_64BIT
 220         asm volatile(
 221                 "       basr    %0,0\n"
 222                 "0:     ahi     %0,1f-0b\n"
 223                 "       st      %0,%O1+4(%R1)\n"
 224                 "       lpsw    %1\n"
 225                 "1:"
 226                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 227 #else /* CONFIG_64BIT */
 228         asm volatile(
 229                 "       larl    %0,1f\n"
 230                 "       stg     %0,%O1+8(%R1)\n"
 231                 "       lpswe   %1\n"
 232                 "1:"
 233                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 234 #endif /* CONFIG_64BIT */
 235 }
 236
 237 /*
 238  * Rewind PSW instruction address by specified number of bytes.
 239  */
 240 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 241 {
 242 #ifndef CONFIG_64BIT
 243         if (psw.addr & PSW_ADDR_AMODE)
 244                 /* 31 bit mode */
 245                 return (psw.addr - ilc) | PSW_ADDR_AMODE;
 246         /* 24 bit mode */
 247         return (psw.addr - ilc) & ((1UL << 24) - 1);
 248 #else
 249         unsigned long mask;
 250
 251         mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 252                (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 253                                           (1UL << 24) - 1;
 254         return (psw.addr - ilc) & mask;
 255 #endif
 256 }
 257
 258 /*
 259  * Function to drop a processor into disabled wait state
 260  */
 261 static inline void __noreturn disabled_wait(unsigned long code)
 262 {
 263         unsigned long ctl_buf;
 264         psw_t dw_psw;
 265
 266         dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 267         dw_psw.addr = code;
 268         /*
 269          * Store status and then load disabled wait psw,
 270          * the processor is dead afterwards
 271          */
 272 #ifndef CONFIG_64BIT
 273         asm volatile(
 274                 "       stctl   0,0,0(%2)\n"
 275                 "       ni      0(%2),0xef\n"   /* switch off protection */
 276                 "       lctl    0,0,0(%2)\n"
 277                 "       stpt    0xd8\n"         /* store timer */
 278                 "       stckc   0xe0\n"         /* store clock comparator */
 279                 "       stpx    0x108\n"        /* store prefix register */
 280                 "       stam    0,15,0x120\n"   /* store access registers */
 281                 "       std     0,0x160\n"      /* store f0 */
 282                 "       std     2,0x168\n"      /* store f2 */
 283                 "       std     4,0x170\n"      /* store f4 */
 284                 "       std     6,0x178\n"      /* store f6 */
 285                 "       stm     0,15,0x180\n"   /* store general registers */
 286                 "       stctl   0,15,0x1c0\n"   /* store control registers */
 287                 "       oi      0x1c0,0x10\n"   /* fake protection bit */
 288                 "       lpsw    0(%1)"
 289                 : "=m" (ctl_buf)
 290                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
 291 #else /* CONFIG_64BIT */
 292         asm volatile(
 293                 "       stctg   0,0,0(%2)\n"
 294                 "       ni      4(%2),0xef\n"   /* switch off protection */
 295                 "       lctlg   0,0,0(%2)\n"
 296                 "       lghi    1,0x1000\n"
 297                 "       stpt    0x328(1)\n"     /* store timer */
 298                 "       stckc   0x330(1)\n"     /* store clock comparator */
 299                 "       stpx    0x318(1)\n"     /* store prefix register */
 300                 "       stam    0,15,0x340(1)\n"/* store access registers */
 301                 "       stfpc   0x31c(1)\n"     /* store fpu control */
 302                 "       std     0,0x200(1)\n"   /* store f0 */
 303                 "       std     1,0x208(1)\n"   /* store f1 */
 304                 "       std     2,0x210(1)\n"   /* store f2 */
 305                 "       std     3,0x218(1)\n"   /* store f3 */
 306                 "       std     4,0x220(1)\n"   /* store f4 */
 307                 "       std     5,0x228(1)\n"   /* store f5 */
 308                 "       std     6,0x230(1)\n"   /* store f6 */
 309                 "       std     7,0x238(1)\n"   /* store f7 */
 310                 "       std     8,0x240(1)\n"   /* store f8 */
 311                 "       std     9,0x248(1)\n"   /* store f9 */
 312                 "       std     10,0x250(1)\n"  /* store f10 */
 313                 "       std     11,0x258(1)\n"  /* store f11 */
 314                 "       std     12,0x260(1)\n"  /* store f12 */
 315                 "       std     13,0x268(1)\n"  /* store f13 */
 316                 "       std     14,0x270(1)\n"  /* store f14 */
 317                 "       std     15,0x278(1)\n"  /* store f15 */
 318                 "       stmg    0,15,0x280(1)\n"/* store general registers */
 319                 "       stctg   0,15,0x380(1)\n"/* store control registers */
 320                 "       oi      0x384(1),0x10\n"/* fake protection bit */
 321                 "       lpswe   0(%1)"
 322                 : "=m" (ctl_buf)
 323                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
 324 #endif /* CONFIG_64BIT */
 325         while (1);
 326 }
 327
 328 /*
 329  * Use to set psw mask except for the first byte which
 330  * won't be changed by this function.
 331  */
 332 static inline void
 333 __set_psw_mask(unsigned long mask)
 334 {
 335         __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 336 }
 337
 338 #define local_mcck_enable() \
 339         __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
 340 #define local_mcck_disable() \
 341         __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)
 342
 343 /*
 344  * Basic Machine Check/Program Check Handler.
 345  */
 346
 347 extern void s390_base_mcck_handler(void);
 348 extern void s390_base_pgm_handler(void);
 349 extern void s390_base_ext_handler(void);
 350
 351 extern void (*s390_base_mcck_handler_fn)(void);
 352 extern void (*s390_base_pgm_handler_fn)(void);
 353 extern void (*s390_base_ext_handler_fn)(void);
 354
 355 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 356
 357 extern int memcpy_real(void *, void *, size_t);
 358 extern void memcpy_absolute(void *, void *, size_t);
 359
 360 #define mem_assign_absolute(dest, val) {                        \
 361         __typeof__(dest) __tmp = (val);                         \
 362                                                                 \
 363         BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 364         memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 365 }
 366
 367 /*
 368  * Helper macro for exception table entries
 369  */
 370 #define EX_TABLE(_fault, _target)       \
 371         ".section __ex_table,\"a\"\n"   \
 372         ".align 4\n"                    \
 373         ".long  (" #_fault ") - .\n"    \
 374         ".long  (" #_target ") - .\n"   \
 375         ".previous\n"
 376
 377 #else /* __ASSEMBLY__ */
 378
 379 #define EX_TABLE(_fault, _target)       \
 380         .section __ex_table,"a" ;       \
 381         .align  4 ;                     \
 382         .long   (_fault) - . ;          \
 383         .long   (_target) - . ;         \
 384         .previous
 385
 386 #endif /* __ASSEMBLY__ */
 387
 388 #endif /* __ASM_S390_PROCESSOR_H */