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s390/zcrypt: Toleration of new crypto hardware
[deliverable/linux.git] / arch / s390 / include / asm / processor.h
1 /*
2 * S390 version
3 * Copyright IBM Corp. 1999
4 * Author(s): Hartmut Penner (hp@de.ibm.com),
5 * Martin Schwidefsky (schwidefsky@de.ibm.com)
6 *
7 * Derived from "include/asm-i386/processor.h"
8 * Copyright (C) 1994, Linus Torvalds
9 */
10
11 #ifndef __ASM_S390_PROCESSOR_H
12 #define __ASM_S390_PROCESSOR_H
13
14 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */
15 #define CIF_ASCE 1 /* user asce needs fixup / uaccess */
16 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
17
18 #define _CIF_MCCK_PENDING (1<<CIF_MCCK_PENDING)
19 #define _CIF_ASCE (1<<CIF_ASCE)
20 #define _CIF_NOHZ_DELAY (1<<CIF_NOHZ_DELAY)
21
22
23 #ifndef __ASSEMBLY__
24
25 #include <linux/linkage.h>
26 #include <linux/irqflags.h>
27 #include <asm/cpu.h>
28 #include <asm/page.h>
29 #include <asm/ptrace.h>
30 #include <asm/setup.h>
31 #include <asm/runtime_instr.h>
32
33 static inline void set_cpu_flag(int flag)
34 {
35 S390_lowcore.cpu_flags |= (1U << flag);
36 }
37
38 static inline void clear_cpu_flag(int flag)
39 {
40 S390_lowcore.cpu_flags &= ~(1U << flag);
41 }
42
43 static inline int test_cpu_flag(int flag)
44 {
45 return !!(S390_lowcore.cpu_flags & (1U << flag));
46 }
47
48 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
49
50 /*
51 * Default implementation of macro that returns current
52 * instruction pointer ("program counter").
53 */
54 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
55
56 static inline void get_cpu_id(struct cpuid *ptr)
57 {
58 asm volatile("stidp %0" : "=Q" (*ptr));
59 }
60
61 extern void s390_adjust_jiffies(void);
62 extern const struct seq_operations cpuinfo_op;
63 extern int sysctl_ieee_emulation_warnings;
64 extern void execve_tail(void);
65
66 /*
67 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
68 */
69 #ifndef CONFIG_64BIT
70
71 #define TASK_SIZE (1UL << 31)
72 #define TASK_MAX_SIZE (1UL << 31)
73 #define TASK_UNMAPPED_BASE (1UL << 30)
74
75 #else /* CONFIG_64BIT */
76
77 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
78 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
79 (1UL << 30) : (1UL << 41))
80 #define TASK_SIZE TASK_SIZE_OF(current)
81 #define TASK_MAX_SIZE (1UL << 53)
82
83 #endif /* CONFIG_64BIT */
84
85 #ifndef CONFIG_64BIT
86 #define STACK_TOP (1UL << 31)
87 #define STACK_TOP_MAX (1UL << 31)
88 #else /* CONFIG_64BIT */
89 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
90 #define STACK_TOP_MAX (1UL << 42)
91 #endif /* CONFIG_64BIT */
92
93 #define HAVE_ARCH_PICK_MMAP_LAYOUT
94
95 typedef struct {
96 __u32 ar4;
97 } mm_segment_t;
98
99 /*
100 * Thread structure
101 */
102 struct thread_struct {
103 s390_fp_regs fp_regs;
104 unsigned int acrs[NUM_ACRS];
105 unsigned long ksp; /* kernel stack pointer */
106 mm_segment_t mm_segment;
107 unsigned long gmap_addr; /* address of last gmap fault. */
108 unsigned int gmap_pfault; /* signal of a pending guest pfault */
109 struct per_regs per_user; /* User specified PER registers */
110 struct per_event per_event; /* Cause of the last PER trap */
111 unsigned long per_flags; /* Flags to control debug behavior */
112 /* pfault_wait is used to block the process on a pfault event */
113 unsigned long pfault_wait;
114 struct list_head list;
115 /* cpu runtime instrumentation */
116 struct runtime_instr_cb *ri_cb;
117 int ri_signum;
118 #ifdef CONFIG_64BIT
119 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
120 #endif
121 };
122
123 /* Flag to disable transactions. */
124 #define PER_FLAG_NO_TE 1UL
125 /* Flag to enable random transaction aborts. */
126 #define PER_FLAG_TE_ABORT_RAND 2UL
127 /* Flag to specify random transaction abort mode:
128 * - abort each transaction at a random instruction before TEND if set.
129 * - abort random transactions at a random instruction if cleared.
130 */
131 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
132
133 typedef struct thread_struct thread_struct;
134
135 /*
136 * Stack layout of a C stack frame.
137 */
138 #ifndef __PACK_STACK
139 struct stack_frame {
140 unsigned long back_chain;
141 unsigned long empty1[5];
142 unsigned long gprs[10];
143 unsigned int empty2[8];
144 };
145 #else
146 struct stack_frame {
147 unsigned long empty1[5];
148 unsigned int empty2[8];
149 unsigned long gprs[10];
150 unsigned long back_chain;
151 };
152 #endif
153
154 #define ARCH_MIN_TASKALIGN 8
155
156 #define INIT_THREAD { \
157 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
158 }
159
160 /*
161 * Do necessary setup to start up a new thread.
162 */
163 #define start_thread(regs, new_psw, new_stackp) do { \
164 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
165 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
166 regs->gprs[15] = new_stackp; \
167 execve_tail(); \
168 } while (0)
169
170 #define start_thread31(regs, new_psw, new_stackp) do { \
171 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
172 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
173 regs->gprs[15] = new_stackp; \
174 crst_table_downgrade(current->mm, 1UL << 31); \
175 execve_tail(); \
176 } while (0)
177
178 /* Forward declaration, a strange C thing */
179 struct task_struct;
180 struct mm_struct;
181 struct seq_file;
182
183 #ifdef CONFIG_64BIT
184 extern void show_cacheinfo(struct seq_file *m);
185 #else
186 static inline void show_cacheinfo(struct seq_file *m) { }
187 #endif
188
189 /* Free all resources held by a thread. */
190 extern void release_thread(struct task_struct *);
191
192 /*
193 * Return saved PC of a blocked thread.
194 */
195 extern unsigned long thread_saved_pc(struct task_struct *t);
196
197 unsigned long get_wchan(struct task_struct *p);
198 #define task_pt_regs(tsk) ((struct pt_regs *) \
199 (task_stack_page(tsk) + THREAD_SIZE) - 1)
200 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
201 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
202
203 /* Has task runtime instrumentation enabled ? */
204 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
205
206 static inline unsigned short stap(void)
207 {
208 unsigned short cpu_address;
209
210 asm volatile("stap %0" : "=m" (cpu_address));
211 return cpu_address;
212 }
213
214 /*
215 * Give up the time slice of the virtual PU.
216 */
217 static inline void cpu_relax(void)
218 {
219 if (MACHINE_HAS_DIAG44)
220 asm volatile("diag 0,0,68");
221 barrier();
222 }
223
224 #define cpu_relax_lowlatency() barrier()
225
226 static inline void psw_set_key(unsigned int key)
227 {
228 asm volatile("spka 0(%0)" : : "d" (key));
229 }
230
231 /*
232 * Set PSW to specified value.
233 */
234 static inline void __load_psw(psw_t psw)
235 {
236 #ifndef CONFIG_64BIT
237 asm volatile("lpsw %0" : : "Q" (psw) : "cc");
238 #else
239 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
240 #endif
241 }
242
243 /*
244 * Set PSW mask to specified value, while leaving the
245 * PSW addr pointing to the next instruction.
246 */
247 static inline void __load_psw_mask (unsigned long mask)
248 {
249 unsigned long addr;
250 psw_t psw;
251
252 psw.mask = mask;
253
254 #ifndef CONFIG_64BIT
255 asm volatile(
256 " basr %0,0\n"
257 "0: ahi %0,1f-0b\n"
258 " st %0,%O1+4(%R1)\n"
259 " lpsw %1\n"
260 "1:"
261 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
262 #else /* CONFIG_64BIT */
263 asm volatile(
264 " larl %0,1f\n"
265 " stg %0,%O1+8(%R1)\n"
266 " lpswe %1\n"
267 "1:"
268 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
269 #endif /* CONFIG_64BIT */
270 }
271
272 /*
273 * Rewind PSW instruction address by specified number of bytes.
274 */
275 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
276 {
277 #ifndef CONFIG_64BIT
278 if (psw.addr & PSW_ADDR_AMODE)
279 /* 31 bit mode */
280 return (psw.addr - ilc) | PSW_ADDR_AMODE;
281 /* 24 bit mode */
282 return (psw.addr - ilc) & ((1UL << 24) - 1);
283 #else
284 unsigned long mask;
285
286 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
287 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
288 (1UL << 24) - 1;
289 return (psw.addr - ilc) & mask;
290 #endif
291 }
292
293 /*
294 * Function to stop a processor until the next interrupt occurs
295 */
296 void enabled_wait(void);
297
298 /*
299 * Function to drop a processor into disabled wait state
300 */
301 static inline void __noreturn disabled_wait(unsigned long code)
302 {
303 unsigned long ctl_buf;
304 psw_t dw_psw;
305
306 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
307 dw_psw.addr = code;
308 /*
309 * Store status and then load disabled wait psw,
310 * the processor is dead afterwards
311 */
312 #ifndef CONFIG_64BIT
313 asm volatile(
314 " stctl 0,0,0(%2)\n"
315 " ni 0(%2),0xef\n" /* switch off protection */
316 " lctl 0,0,0(%2)\n"
317 " stpt 0xd8\n" /* store timer */
318 " stckc 0xe0\n" /* store clock comparator */
319 " stpx 0x108\n" /* store prefix register */
320 " stam 0,15,0x120\n" /* store access registers */
321 " std 0,0x160\n" /* store f0 */
322 " std 2,0x168\n" /* store f2 */
323 " std 4,0x170\n" /* store f4 */
324 " std 6,0x178\n" /* store f6 */
325 " stm 0,15,0x180\n" /* store general registers */
326 " stctl 0,15,0x1c0\n" /* store control registers */
327 " oi 0x1c0,0x10\n" /* fake protection bit */
328 " lpsw 0(%1)"
329 : "=m" (ctl_buf)
330 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
331 #else /* CONFIG_64BIT */
332 asm volatile(
333 " stctg 0,0,0(%2)\n"
334 " ni 4(%2),0xef\n" /* switch off protection */
335 " lctlg 0,0,0(%2)\n"
336 " lghi 1,0x1000\n"
337 " stpt 0x328(1)\n" /* store timer */
338 " stckc 0x330(1)\n" /* store clock comparator */
339 " stpx 0x318(1)\n" /* store prefix register */
340 " stam 0,15,0x340(1)\n"/* store access registers */
341 " stfpc 0x31c(1)\n" /* store fpu control */
342 " std 0,0x200(1)\n" /* store f0 */
343 " std 1,0x208(1)\n" /* store f1 */
344 " std 2,0x210(1)\n" /* store f2 */
345 " std 3,0x218(1)\n" /* store f3 */
346 " std 4,0x220(1)\n" /* store f4 */
347 " std 5,0x228(1)\n" /* store f5 */
348 " std 6,0x230(1)\n" /* store f6 */
349 " std 7,0x238(1)\n" /* store f7 */
350 " std 8,0x240(1)\n" /* store f8 */
351 " std 9,0x248(1)\n" /* store f9 */
352 " std 10,0x250(1)\n" /* store f10 */
353 " std 11,0x258(1)\n" /* store f11 */
354 " std 12,0x260(1)\n" /* store f12 */
355 " std 13,0x268(1)\n" /* store f13 */
356 " std 14,0x270(1)\n" /* store f14 */
357 " std 15,0x278(1)\n" /* store f15 */
358 " stmg 0,15,0x280(1)\n"/* store general registers */
359 " stctg 0,15,0x380(1)\n"/* store control registers */
360 " oi 0x384(1),0x10\n"/* fake protection bit */
361 " lpswe 0(%1)"
362 : "=m" (ctl_buf)
363 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
364 #endif /* CONFIG_64BIT */
365 while (1);
366 }
367
368 /*
369 * Use to set psw mask except for the first byte which
370 * won't be changed by this function.
371 */
372 static inline void
373 __set_psw_mask(unsigned long mask)
374 {
375 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
376 }
377
378 #define local_mcck_enable() \
379 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
380 #define local_mcck_disable() \
381 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
382
383 /*
384 * Basic Machine Check/Program Check Handler.
385 */
386
387 extern void s390_base_mcck_handler(void);
388 extern void s390_base_pgm_handler(void);
389 extern void s390_base_ext_handler(void);
390
391 extern void (*s390_base_mcck_handler_fn)(void);
392 extern void (*s390_base_pgm_handler_fn)(void);
393 extern void (*s390_base_ext_handler_fn)(void);
394
395 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
396
397 extern int memcpy_real(void *, void *, size_t);
398 extern void memcpy_absolute(void *, void *, size_t);
399
400 #define mem_assign_absolute(dest, val) { \
401 __typeof__(dest) __tmp = (val); \
402 \
403 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
404 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
405 }
406
407 /*
408 * Helper macro for exception table entries
409 */
410 #define EX_TABLE(_fault, _target) \
411 ".section __ex_table,\"a\"\n" \
412 ".align 4\n" \
413 ".long (" #_fault ") - .\n" \
414 ".long (" #_target ") - .\n" \
415 ".previous\n"
416
417 #else /* __ASSEMBLY__ */
418
419 #define EX_TABLE(_fault, _target) \
420 .section __ex_table,"a" ; \
421 .align 4 ; \
422 .long (_fault) - . ; \
423 .long (_target) - . ; \
424 .previous
425
426 #endif /* __ASSEMBLY__ */
427
428 #endif /* __ASM_S390_PROCESSOR_H */
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