2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
15 #include <linux/errno.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
19 #include <linux/param.h>
20 #include <linux/string.h>
22 #include <linux/interrupt.h>
23 #include <linux/time.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/smp.h>
27 #include <linux/types.h>
28 #include <linux/profile.h>
29 #include <linux/timex.h>
30 #include <linux/notifier.h>
31 #include <linux/clocksource.h>
33 #include <asm/uaccess.h>
34 #include <asm/delay.h>
35 #include <asm/s390_ext.h>
36 #include <asm/div64.h>
38 #include <asm/irq_regs.h>
39 #include <asm/timer.h>
42 /* change this if you have some constant time drift */
43 #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
44 #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
46 /* The value of the TOD clock for 1.1.1970. */
47 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
50 * Create a small time difference between the timer interrupts
51 * on the different cpus to avoid lock contention.
53 #define CPU_DEVIATION (smp_processor_id() << 12)
55 #define TICK_SIZE tick
57 static ext_int_info_t ext_int_info_cc
;
58 static ext_int_info_t ext_int_etr_cc
;
59 static u64 init_timer_cc
;
60 static u64 jiffies_timer_cc
;
64 * Scheduler clock - returns current time in nanosec units.
66 unsigned long long sched_clock(void)
68 return ((get_clock() - jiffies_timer_cc
) * 125) >> 9;
72 * Monotonic_clock - returns # of nanoseconds passed since time_init()
74 unsigned long long monotonic_clock(void)
78 EXPORT_SYMBOL(monotonic_clock
);
80 void tod_to_timeval(__u64 todval
, struct timespec
*xtime
)
82 unsigned long long sec
;
87 todval
-= (sec
* 1000000) << 12;
88 xtime
->tv_nsec
= ((todval
* 1000) >> 12);
91 #ifdef CONFIG_PROFILING
92 #define s390_do_profile() profile_tick(CPU_PROFILING)
94 #define s390_do_profile() do { ; } while(0)
95 #endif /* CONFIG_PROFILING */
98 * Advance the per cpu tick counter up to the time given with the
99 * "time" argument. The per cpu update consists of accounting
100 * the virtual cpu time, calling update_process_times and calling
101 * the profiling hook. If xtime is before time it is advanced as well.
103 void account_ticks(u64 time
)
108 /* Calculate how many ticks have passed. */
109 if (time
< S390_lowcore
.jiffy_timer
)
111 tmp
= time
- S390_lowcore
.jiffy_timer
;
112 if (tmp
>= 2*CLK_TICKS_PER_JIFFY
) { /* more than two ticks ? */
113 ticks
= __div(tmp
, CLK_TICKS_PER_JIFFY
) + 1;
114 S390_lowcore
.jiffy_timer
+=
115 CLK_TICKS_PER_JIFFY
* (__u64
) ticks
;
116 } else if (tmp
>= CLK_TICKS_PER_JIFFY
) {
118 S390_lowcore
.jiffy_timer
+= 2*CLK_TICKS_PER_JIFFY
;
121 S390_lowcore
.jiffy_timer
+= CLK_TICKS_PER_JIFFY
;
126 * Do not rely on the boot cpu to do the calls to do_timer.
127 * Spread it over all cpus instead.
129 write_seqlock(&xtime_lock
);
130 if (S390_lowcore
.jiffy_timer
> xtime_cc
) {
132 tmp
= S390_lowcore
.jiffy_timer
- xtime_cc
;
133 if (tmp
>= 2*CLK_TICKS_PER_JIFFY
) {
134 xticks
= __div(tmp
, CLK_TICKS_PER_JIFFY
);
135 xtime_cc
+= (__u64
) xticks
* CLK_TICKS_PER_JIFFY
;
138 xtime_cc
+= CLK_TICKS_PER_JIFFY
;
142 write_sequnlock(&xtime_lock
);
147 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
148 account_tick_vtime(current
);
151 update_process_times(user_mode(get_irq_regs()));
157 #ifdef CONFIG_NO_IDLE_HZ
159 #ifdef CONFIG_NO_IDLE_HZ_INIT
160 int sysctl_hz_timer
= 0;
162 int sysctl_hz_timer
= 1;
166 * Stop the HZ tick on the current CPU.
167 * Only cpu_idle may call this function.
169 static void stop_hz_timer(void)
172 unsigned long seq
, next
;
174 int cpu
= smp_processor_id();
176 if (sysctl_hz_timer
!= 0)
179 cpu_set(cpu
, nohz_cpu_mask
);
182 * Leave the clock comparator set up for the next timer
183 * tick if either rcu or a softirq is pending.
185 if (rcu_needs_cpu(cpu
) || local_softirq_pending()) {
186 cpu_clear(cpu
, nohz_cpu_mask
);
191 * This cpu is going really idle. Set up the clock comparator
192 * for the next event.
194 next
= next_timer_interrupt();
196 seq
= read_seqbegin_irqsave(&xtime_lock
, flags
);
197 timer
= ((__u64
) next
) - ((__u64
) jiffies
) + jiffies_64
;
198 } while (read_seqretry_irqrestore(&xtime_lock
, seq
, flags
));
200 /* Be careful about overflows. */
201 if (timer
< (-1ULL / CLK_TICKS_PER_JIFFY
)) {
202 timer
= jiffies_timer_cc
+ timer
* CLK_TICKS_PER_JIFFY
;
203 if (timer
>= jiffies_timer_cc
)
206 set_clock_comparator(todval
);
210 * Start the HZ tick on the current CPU.
211 * Only cpu_idle may call this function.
213 static void start_hz_timer(void)
215 BUG_ON(!in_interrupt());
217 if (!cpu_isset(smp_processor_id(), nohz_cpu_mask
))
219 account_ticks(get_clock());
220 set_clock_comparator(S390_lowcore
.jiffy_timer
+ CPU_DEVIATION
);
221 cpu_clear(smp_processor_id(), nohz_cpu_mask
);
224 static int nohz_idle_notify(struct notifier_block
*self
,
225 unsigned long action
, void *hcpu
)
238 static struct notifier_block nohz_idle_nb
= {
239 .notifier_call
= nohz_idle_notify
,
242 static void __init
nohz_init(void)
244 if (register_idle_notifier(&nohz_idle_nb
))
245 panic("Couldn't register idle notifier");
251 * Set up per cpu jiffy timer and set the clock comparator.
253 static void setup_jiffy_timer(void)
255 /* Set up clock comparator to next jiffy. */
256 S390_lowcore
.jiffy_timer
=
257 jiffies_timer_cc
+ (jiffies_64
+ 1) * CLK_TICKS_PER_JIFFY
;
258 set_clock_comparator(S390_lowcore
.jiffy_timer
+ CPU_DEVIATION
);
262 * Set up lowcore and control register of the current cpu to
263 * enable TOD clock and clock comparator interrupts.
265 void init_cpu_timer(void)
269 /* Enable clock comparator timer interrupt. */
272 /* Always allow ETR external interrupts, even without an ETR. */
276 static void clock_comparator_interrupt(__u16 code
)
278 /* set clock comparator for next tick */
279 set_clock_comparator(S390_lowcore
.jiffy_timer
+ CPU_DEVIATION
);
282 static void etr_reset(void);
283 static void etr_init(void);
284 static void etr_ext_handler(__u16
);
287 * Get the TOD clock running.
289 static u64 __init
reset_tod_clock(void)
294 if (store_clock(&time
) == 0)
296 /* TOD clock not running. Set the clock to Unix Epoch. */
297 if (set_clock(TOD_UNIX_EPOCH
) != 0 || store_clock(&time
) != 0)
298 panic("TOD clock not operational.");
300 return TOD_UNIX_EPOCH
;
303 static cycle_t
read_tod_clock(void)
308 static struct clocksource clocksource_tod
= {
311 .read
= read_tod_clock
,
320 * Initialize the TOD clock and the CPU timer of
323 void __init
time_init(void)
325 init_timer_cc
= reset_tod_clock();
326 xtime_cc
= init_timer_cc
+ CLK_TICKS_PER_JIFFY
;
327 jiffies_timer_cc
= init_timer_cc
- jiffies_64
* CLK_TICKS_PER_JIFFY
;
330 tod_to_timeval(init_timer_cc
- TOD_UNIX_EPOCH
, &xtime
);
331 set_normalized_timespec(&wall_to_monotonic
,
332 -xtime
.tv_sec
, -xtime
.tv_nsec
);
334 /* request the clock comparator external interrupt */
335 if (register_early_external_interrupt(0x1004,
336 clock_comparator_interrupt
,
337 &ext_int_info_cc
) != 0)
338 panic("Couldn't request external interrupt 0x1004");
340 if (clocksource_register(&clocksource_tod
) != 0)
341 panic("Could not register TOD clock source");
343 /* request the etr external interrupt */
344 if (register_early_external_interrupt(0x1406, etr_ext_handler
,
345 &ext_int_etr_cc
) != 0)
346 panic("Couldn't request external interrupt 0x1406");
348 /* Enable TOD clock interrupts on the boot cpu. */
351 #ifdef CONFIG_NO_IDLE_HZ
355 #ifdef CONFIG_VIRT_TIMER
362 * External Time Reference (ETR) code.
364 static int etr_port0_online
;
365 static int etr_port1_online
;
367 static int __init
early_parse_etr(char *p
)
369 if (strncmp(p
, "off", 3) == 0)
370 etr_port0_online
= etr_port1_online
= 0;
371 else if (strncmp(p
, "port0", 5) == 0)
372 etr_port0_online
= 1;
373 else if (strncmp(p
, "port1", 5) == 0)
374 etr_port1_online
= 1;
375 else if (strncmp(p
, "on", 2) == 0)
376 etr_port0_online
= etr_port1_online
= 1;
379 early_param("etr", early_parse_etr
);
382 ETR_EVENT_PORT0_CHANGE
,
383 ETR_EVENT_PORT1_CHANGE
,
384 ETR_EVENT_PORT_ALERT
,
385 ETR_EVENT_SYNC_CHECK
,
386 ETR_EVENT_SWITCH_LOCAL
,
397 * Valid bit combinations of the eacr register are (x = don't care):
398 * e0 e1 dp p0 p1 ea es sl
399 * 0 0 x 0 0 0 0 0 initial, disabled state
400 * 0 0 x 0 1 1 0 0 port 1 online
401 * 0 0 x 1 0 1 0 0 port 0 online
402 * 0 0 x 1 1 1 0 0 both ports online
403 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
404 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
405 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
406 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
407 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
408 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
409 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
410 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
411 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
412 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
413 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
414 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
415 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
416 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
417 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
418 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
420 static struct etr_eacr etr_eacr
;
421 static u64 etr_tolec
; /* time of last eacr update */
422 static unsigned long etr_flags
;
423 static struct etr_aib etr_port0
;
424 static int etr_port0_uptodate
;
425 static struct etr_aib etr_port1
;
426 static int etr_port1_uptodate
;
427 static unsigned long etr_events
;
428 static struct timer_list etr_timer
;
429 static struct tasklet_struct etr_tasklet
;
430 static DEFINE_PER_CPU(atomic_t
, etr_sync_word
);
432 static void etr_timeout(unsigned long dummy
);
433 static void etr_tasklet_fn(unsigned long dummy
);
436 * The etr get_clock function. It will write the current clock value
437 * to the clock pointer and return 0 if the clock is in sync with the
438 * external time source. If the clock mode is local it will return
439 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
440 * reference. This function is what ETR is all about..
442 int get_sync_clock(unsigned long long *clock
)
445 unsigned int sw0
, sw1
;
447 sw_ptr
= &get_cpu_var(etr_sync_word
);
448 sw0
= atomic_read(sw_ptr
);
449 *clock
= get_clock();
450 sw1
= atomic_read(sw_ptr
);
451 put_cpu_var(etr_sync_sync
);
452 if (sw0
== sw1
&& (sw0
& 0x80000000U
))
453 /* Success: time is in sync. */
455 if (test_bit(ETR_FLAG_ENOSYS
, &etr_flags
))
457 if (test_bit(ETR_FLAG_EACCES
, &etr_flags
))
461 EXPORT_SYMBOL(get_sync_clock
);
464 * Make get_sync_clock return -EAGAIN.
466 static void etr_disable_sync_clock(void *dummy
)
468 atomic_t
*sw_ptr
= &__get_cpu_var(etr_sync_word
);
470 * Clear the in-sync bit 2^31. All get_sync_clock calls will
471 * fail until the sync bit is turned back on. In addition
472 * increase the "sequence" counter to avoid the race of an
473 * etr event and the complete recovery against get_sync_clock.
475 atomic_clear_mask(0x80000000, sw_ptr
);
480 * Make get_sync_clock return 0 again.
481 * Needs to be called from a context disabled for preemption.
483 static void etr_enable_sync_clock(void)
485 atomic_t
*sw_ptr
= &__get_cpu_var(etr_sync_word
);
486 atomic_set_mask(0x80000000, sw_ptr
);
490 * Reset ETR attachment.
492 static void etr_reset(void)
494 etr_eacr
= (struct etr_eacr
) {
495 .e0
= 0, .e1
= 0, ._pad0
= 4, .dp
= 0,
496 .p0
= 0, .p1
= 0, ._pad1
= 0, .ea
= 0,
498 if (etr_setr(&etr_eacr
) == 0)
499 etr_tolec
= get_clock();
501 set_bit(ETR_FLAG_ENOSYS
, &etr_flags
);
502 if (etr_port0_online
|| etr_port1_online
) {
503 printk(KERN_WARNING
"Running on non ETR capable "
504 "machine, only local mode available.\n");
505 etr_port0_online
= etr_port1_online
= 0;
510 static void etr_init(void)
514 if (test_bit(ETR_FLAG_ENOSYS
, &etr_flags
))
516 /* Check if this machine has the steai instruction. */
517 if (etr_steai(&aib
, ETR_STEAI_STEPPING_PORT
) == 0)
518 set_bit(ETR_FLAG_STEAI
, &etr_flags
);
519 setup_timer(&etr_timer
, etr_timeout
, 0UL);
520 tasklet_init(&etr_tasklet
, etr_tasklet_fn
, 0);
521 if (!etr_port0_online
&& !etr_port1_online
)
522 set_bit(ETR_FLAG_EACCES
, &etr_flags
);
523 if (etr_port0_online
) {
524 set_bit(ETR_EVENT_PORT0_CHANGE
, &etr_events
);
525 tasklet_hi_schedule(&etr_tasklet
);
527 if (etr_port1_online
) {
528 set_bit(ETR_EVENT_PORT1_CHANGE
, &etr_events
);
529 tasklet_hi_schedule(&etr_tasklet
);
534 * Two sorts of ETR machine checks. The architecture reads:
535 * "When a machine-check niterruption occurs and if a switch-to-local or
536 * ETR-sync-check interrupt request is pending but disabled, this pending
537 * disabled interruption request is indicated and is cleared".
538 * Which means that we can get etr_switch_to_local events from the machine
539 * check handler although the interruption condition is disabled. Lovely..
543 * Switch to local machine check. This is called when the last usable
544 * ETR port goes inactive. After switch to local the clock is not in sync.
546 void etr_switch_to_local(void)
550 etr_disable_sync_clock(NULL
);
551 set_bit(ETR_EVENT_SWITCH_LOCAL
, &etr_events
);
552 tasklet_hi_schedule(&etr_tasklet
);
556 * ETR sync check machine check. This is called when the ETR OTE and the
557 * local clock OTE are farther apart than the ETR sync check tolerance.
558 * After a ETR sync check the clock is not in sync. The machine check
559 * is broadcasted to all cpus at the same time.
561 void etr_sync_check(void)
565 etr_disable_sync_clock(NULL
);
566 set_bit(ETR_EVENT_SYNC_CHECK
, &etr_events
);
567 tasklet_hi_schedule(&etr_tasklet
);
571 * ETR external interrupt. There are two causes:
572 * 1) port state change, check the usability of the port
573 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
574 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
575 * or ETR-data word 4 (edf4) has changed.
577 static void etr_ext_handler(__u16 code
)
579 struct etr_interruption_parameter
*intparm
=
580 (struct etr_interruption_parameter
*) &S390_lowcore
.ext_params
;
583 /* ETR port 0 state change. */
584 set_bit(ETR_EVENT_PORT0_CHANGE
, &etr_events
);
586 /* ETR port 1 state change. */
587 set_bit(ETR_EVENT_PORT1_CHANGE
, &etr_events
);
590 * ETR port alert on either port 0, 1 or both.
591 * Both ports are not up-to-date now.
593 set_bit(ETR_EVENT_PORT_ALERT
, &etr_events
);
594 tasklet_hi_schedule(&etr_tasklet
);
597 static void etr_timeout(unsigned long dummy
)
599 set_bit(ETR_EVENT_UPDATE
, &etr_events
);
600 tasklet_hi_schedule(&etr_tasklet
);
604 * Check if the etr mode is pss.
606 static inline int etr_mode_is_pps(struct etr_eacr eacr
)
608 return eacr
.es
&& !eacr
.sl
;
612 * Check if the etr mode is etr.
614 static inline int etr_mode_is_etr(struct etr_eacr eacr
)
616 return eacr
.es
&& eacr
.sl
;
620 * Check if the port can be used for TOD synchronization.
621 * For PPS mode the port has to receive OTEs. For ETR mode
622 * the port has to receive OTEs, the ETR stepping bit has to
623 * be zero and the validity bits for data frame 1, 2, and 3
626 static int etr_port_valid(struct etr_aib
*aib
, int port
)
630 /* Check that this port is receiving OTEs. */
634 psc
= port
? aib
->esw
.psc1
: aib
->esw
.psc0
;
635 if (psc
== etr_lpsc_pps_mode
)
637 if (psc
== etr_lpsc_operational_step
)
638 return !aib
->esw
.y
&& aib
->slsw
.v1
&&
639 aib
->slsw
.v2
&& aib
->slsw
.v3
;
644 * Check if two ports are on the same network.
646 static int etr_compare_network(struct etr_aib
*aib1
, struct etr_aib
*aib2
)
648 // FIXME: any other fields we have to compare?
649 return aib1
->edf1
.net_id
== aib2
->edf1
.net_id
;
653 * Wrapper for etr_stei that converts physical port states
654 * to logical port states to be consistent with the output
655 * of stetr (see etr_psc vs. etr_lpsc).
657 static void etr_steai_cv(struct etr_aib
*aib
, unsigned int func
)
659 BUG_ON(etr_steai(aib
, func
) != 0);
660 /* Convert port state to logical port state. */
661 if (aib
->esw
.psc0
== 1)
663 else if (aib
->esw
.psc0
== 0 && aib
->esw
.p
== 0)
665 if (aib
->esw
.psc1
== 1)
667 else if (aib
->esw
.psc1
== 0 && aib
->esw
.p
== 1)
672 * Check if the aib a2 is still connected to the same attachment as
673 * aib a1, the etv values differ by one and a2 is valid.
675 static int etr_aib_follows(struct etr_aib
*a1
, struct etr_aib
*a2
, int p
)
677 int state_a1
, state_a2
;
679 /* Paranoia check: e0/e1 should better be the same. */
680 if (a1
->esw
.eacr
.e0
!= a2
->esw
.eacr
.e0
||
681 a1
->esw
.eacr
.e1
!= a2
->esw
.eacr
.e1
)
684 /* Still connected to the same etr ? */
685 state_a1
= p
? a1
->esw
.psc1
: a1
->esw
.psc0
;
686 state_a2
= p
? a2
->esw
.psc1
: a2
->esw
.psc0
;
687 if (state_a1
== etr_lpsc_operational_step
) {
688 if (state_a2
!= etr_lpsc_operational_step
||
689 a1
->edf1
.net_id
!= a2
->edf1
.net_id
||
690 a1
->edf1
.etr_id
!= a2
->edf1
.etr_id
||
691 a1
->edf1
.etr_pn
!= a2
->edf1
.etr_pn
)
693 } else if (state_a2
!= etr_lpsc_pps_mode
)
696 /* The ETV value of a2 needs to be ETV of a1 + 1. */
697 if (a1
->edf2
.etv
+ 1 != a2
->edf2
.etv
)
700 if (!etr_port_valid(a2
, p
))
707 * The time is "clock". xtime is what we think the time is.
708 * Adjust the value by a multiple of jiffies and add the delta to ntp.
709 * "delay" is an approximation how long the synchronization took. If
710 * the time correction is positive, then "delay" is subtracted from
711 * the time difference and only the remaining part is passed to ntp.
713 static void etr_adjust_time(unsigned long long clock
, unsigned long long delay
)
715 unsigned long long delta
, ticks
;
719 * We don't have to take the xtime lock because the cpu
720 * executing etr_adjust_time is running disabled in
721 * tasklet context and all other cpus are looping in
722 * etr_sync_cpu_start.
724 if (clock
> xtime_cc
) {
725 /* It is later than we thought. */
726 delta
= ticks
= clock
- xtime_cc
;
727 delta
= ticks
= (delta
< delay
) ? 0 : delta
- delay
;
728 delta
-= do_div(ticks
, CLK_TICKS_PER_JIFFY
);
729 init_timer_cc
= init_timer_cc
+ delta
;
730 jiffies_timer_cc
= jiffies_timer_cc
+ delta
;
731 xtime_cc
= xtime_cc
+ delta
;
732 adjust
.offset
= ticks
* (1000000 / HZ
);
734 /* It is earlier than we thought. */
735 delta
= ticks
= xtime_cc
- clock
;
736 delta
-= do_div(ticks
, CLK_TICKS_PER_JIFFY
);
737 init_timer_cc
= init_timer_cc
- delta
;
738 jiffies_timer_cc
= jiffies_timer_cc
- delta
;
739 xtime_cc
= xtime_cc
- delta
;
740 adjust
.offset
= -ticks
* (1000000 / HZ
);
742 if (adjust
.offset
!= 0) {
743 printk(KERN_NOTICE
"etr: time adjusted by %li micro-seconds\n",
745 adjust
.modes
= ADJ_OFFSET_SINGLESHOT
;
746 do_adjtimex(&adjust
);
750 static void etr_sync_cpu_start(void *dummy
)
752 int *in_sync
= dummy
;
754 etr_enable_sync_clock();
756 * This looks like a busy wait loop but it isn't. etr_sync_cpus
757 * is called on all other cpus while the TOD clocks is stopped.
758 * __udelay will stop the cpu on an enabled wait psw until the
759 * TOD is running again.
761 while (*in_sync
== 0)
764 /* Didn't work. Clear per-cpu in sync bit again. */
765 etr_disable_sync_clock(NULL
);
767 * This round of TOD syncing is done. Set the clock comparator
768 * to the next tick and let the processor continue.
773 static void etr_sync_cpu_end(void *dummy
)
778 * Sync the TOD clock using the port refered to by aibp. This port
779 * has to be enabled and the other port has to be disabled. The
780 * last eacr update has to be more than 1.6 seconds in the past.
782 static int etr_sync_clock(struct etr_aib
*aib
, int port
)
784 struct etr_aib
*sync_port
;
785 unsigned long long clock
, delay
;
786 int in_sync
, follows
;
789 /* Check if the current aib is adjacent to the sync port aib. */
790 sync_port
= (port
== 0) ? &etr_port0
: &etr_port1
;
791 follows
= etr_aib_follows(sync_port
, aib
, port
);
792 memcpy(sync_port
, aib
, sizeof(*aib
));
797 * Catch all other cpus and make them wait until we have
798 * successfully synced the clock. smp_call_function will
799 * return after all other cpus are in etr_sync_cpu_start.
803 smp_call_function(etr_sync_cpu_start
,&in_sync
,0,0);
805 etr_enable_sync_clock();
807 /* Set clock to next OTE. */
808 __ctl_set_bit(14, 21);
809 __ctl_set_bit(0, 29);
810 clock
= ((unsigned long long) (aib
->edf2
.etv
+ 1)) << 32;
811 if (set_clock(clock
) == 0) {
812 __udelay(1); /* Wait for the clock to start. */
813 __ctl_clear_bit(0, 29);
814 __ctl_clear_bit(14, 21);
816 /* Adjust Linux timing variables. */
817 delay
= (unsigned long long)
818 (aib
->edf2
.etv
- sync_port
->edf2
.etv
) << 32;
819 etr_adjust_time(clock
, delay
);
821 /* Verify that the clock is properly set. */
822 if (!etr_aib_follows(sync_port
, aib
, port
)) {
824 etr_disable_sync_clock(NULL
);
832 /* Could not set the clock ?!? */
833 __ctl_clear_bit(0, 29);
834 __ctl_clear_bit(14, 21);
835 etr_disable_sync_clock(NULL
);
840 smp_call_function(etr_sync_cpu_end
,NULL
,0,0);
846 * Handle the immediate effects of the different events.
847 * The port change event is used for online/offline changes.
849 static struct etr_eacr
etr_handle_events(struct etr_eacr eacr
)
851 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK
, &etr_events
))
853 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL
, &etr_events
))
854 eacr
.es
= eacr
.sl
= 0;
855 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT
, &etr_events
))
856 etr_port0_uptodate
= etr_port1_uptodate
= 0;
858 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE
, &etr_events
)) {
861 * Port change of an enabled port. We have to
862 * assume that this can have caused an stepping
865 etr_tolec
= get_clock();
866 eacr
.p0
= etr_port0_online
;
869 etr_port0_uptodate
= 0;
871 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE
, &etr_events
)) {
874 * Port change of an enabled port. We have to
875 * assume that this can have caused an stepping
878 etr_tolec
= get_clock();
879 eacr
.p1
= etr_port1_online
;
882 etr_port1_uptodate
= 0;
884 clear_bit(ETR_EVENT_UPDATE
, &etr_events
);
889 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
890 * one of the ports needs an update.
892 static void etr_set_tolec_timeout(unsigned long long now
)
894 unsigned long micros
;
896 if ((!etr_eacr
.p0
|| etr_port0_uptodate
) &&
897 (!etr_eacr
.p1
|| etr_port1_uptodate
))
899 micros
= (now
> etr_tolec
) ? ((now
- etr_tolec
) >> 12) : 0;
900 micros
= (micros
> 1600000) ? 0 : 1600000 - micros
;
901 mod_timer(&etr_timer
, jiffies
+ (micros
* HZ
) / 1000000 + 1);
905 * Set up a time that expires after 1/2 second.
907 static void etr_set_sync_timeout(void)
909 mod_timer(&etr_timer
, jiffies
+ HZ
/2);
913 * Update the aib information for one or both ports.
915 static struct etr_eacr
etr_handle_update(struct etr_aib
*aib
,
916 struct etr_eacr eacr
)
918 /* With both ports disabled the aib information is useless. */
919 if (!eacr
.e0
&& !eacr
.e1
)
922 /* Update port0 or port1 with aib stored in etr_tasklet_fn. */
923 if (aib
->esw
.q
== 0) {
924 /* Information for port 0 stored. */
925 if (eacr
.p0
&& !etr_port0_uptodate
) {
927 if (etr_port0_online
)
928 etr_port0_uptodate
= 1;
931 /* Information for port 1 stored. */
932 if (eacr
.p1
&& !etr_port1_uptodate
) {
934 if (etr_port0_online
)
935 etr_port1_uptodate
= 1;
940 * Do not try to get the alternate port aib if the clock
941 * is not in sync yet.
947 * If steai is available we can get the information about
948 * the other port immediately. If only stetr is available the
949 * data-port bit toggle has to be used.
951 if (test_bit(ETR_FLAG_STEAI
, &etr_flags
)) {
952 if (eacr
.p0
&& !etr_port0_uptodate
) {
953 etr_steai_cv(&etr_port0
, ETR_STEAI_PORT_0
);
954 etr_port0_uptodate
= 1;
956 if (eacr
.p1
&& !etr_port1_uptodate
) {
957 etr_steai_cv(&etr_port1
, ETR_STEAI_PORT_1
);
958 etr_port1_uptodate
= 1;
962 * One port was updated above, if the other
963 * port is not uptodate toggle dp bit.
965 if ((eacr
.p0
&& !etr_port0_uptodate
) ||
966 (eacr
.p1
&& !etr_port1_uptodate
))
975 * Write new etr control register if it differs from the current one.
976 * Return 1 if etr_tolec has been updated as well.
978 static void etr_update_eacr(struct etr_eacr eacr
)
982 if (memcmp(&etr_eacr
, &eacr
, sizeof(eacr
)) == 0)
983 /* No change, return. */
986 * The disable of an active port of the change of the data port
987 * bit can/will cause a change in the data port.
989 dp_changed
= etr_eacr
.e0
> eacr
.e0
|| etr_eacr
.e1
> eacr
.e1
||
990 (etr_eacr
.dp
^ eacr
.dp
) != 0;
994 etr_tolec
= get_clock();
998 * ETR tasklet. In this function you'll find the main logic. In
999 * particular this is the only function that calls etr_update_eacr(),
1000 * it "controls" the etr control register.
1002 static void etr_tasklet_fn(unsigned long dummy
)
1004 unsigned long long now
;
1005 struct etr_eacr eacr
;
1009 /* Create working copy of etr_eacr. */
1012 /* Check for the different events and their immediate effects. */
1013 eacr
= etr_handle_events(eacr
);
1015 /* Check if ETR is supposed to be active. */
1016 eacr
.ea
= eacr
.p0
|| eacr
.p1
;
1018 /* Both ports offline. Reset everything. */
1019 eacr
.dp
= eacr
.es
= eacr
.sl
= 0;
1020 on_each_cpu(etr_disable_sync_clock
, NULL
, 0, 1);
1021 del_timer_sync(&etr_timer
);
1022 etr_update_eacr(eacr
);
1023 set_bit(ETR_FLAG_EACCES
, &etr_flags
);
1027 /* Store aib to get the current ETR status word. */
1028 BUG_ON(etr_stetr(&aib
) != 0);
1029 etr_port0
.esw
= etr_port1
.esw
= aib
.esw
; /* Copy status word. */
1033 * Update the port information if the last stepping port change
1034 * or data port change is older than 1.6 seconds.
1036 if (now
>= etr_tolec
+ (1600000 << 12))
1037 eacr
= etr_handle_update(&aib
, eacr
);
1040 * Select ports to enable. The prefered synchronization mode is PPS.
1041 * If a port can be enabled depends on a number of things:
1042 * 1) The port needs to be online and uptodate. A port is not
1043 * disabled just because it is not uptodate, but it is only
1044 * enabled if it is uptodate.
1045 * 2) The port needs to have the same mode (pps / etr).
1046 * 3) The port needs to be usable -> etr_port_valid() == 1
1047 * 4) To enable the second port the clock needs to be in sync.
1048 * 5) If both ports are useable and are ETR ports, the network id
1049 * has to be the same.
1050 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
1052 if (eacr
.p0
&& aib
.esw
.psc0
== etr_lpsc_pps_mode
) {
1055 if (!etr_mode_is_pps(etr_eacr
))
1057 if (!eacr
.es
|| !eacr
.p1
|| aib
.esw
.psc1
!= etr_lpsc_pps_mode
)
1059 // FIXME: uptodate checks ?
1060 else if (etr_port0_uptodate
&& etr_port1_uptodate
)
1062 sync_port
= (etr_port0_uptodate
&&
1063 etr_port_valid(&etr_port0
, 0)) ? 0 : -1;
1064 clear_bit(ETR_FLAG_EACCES
, &etr_flags
);
1065 } else if (eacr
.p1
&& aib
.esw
.psc1
== etr_lpsc_pps_mode
) {
1069 if (!etr_mode_is_pps(etr_eacr
))
1071 sync_port
= (etr_port1_uptodate
&&
1072 etr_port_valid(&etr_port1
, 1)) ? 1 : -1;
1073 clear_bit(ETR_FLAG_EACCES
, &etr_flags
);
1074 } else if (eacr
.p0
&& aib
.esw
.psc0
== etr_lpsc_operational_step
) {
1077 if (!etr_mode_is_etr(etr_eacr
))
1079 if (!eacr
.es
|| !eacr
.p1
||
1080 aib
.esw
.psc1
!= etr_lpsc_operational_alt
)
1082 else if (etr_port0_uptodate
&& etr_port1_uptodate
&&
1083 etr_compare_network(&etr_port0
, &etr_port1
))
1085 sync_port
= (etr_port0_uptodate
&&
1086 etr_port_valid(&etr_port0
, 0)) ? 0 : -1;
1087 clear_bit(ETR_FLAG_EACCES
, &etr_flags
);
1088 } else if (eacr
.p1
&& aib
.esw
.psc1
== etr_lpsc_operational_step
) {
1092 if (!etr_mode_is_etr(etr_eacr
))
1094 sync_port
= (etr_port1_uptodate
&&
1095 etr_port_valid(&etr_port1
, 1)) ? 1 : -1;
1096 clear_bit(ETR_FLAG_EACCES
, &etr_flags
);
1098 /* Both ports not usable. */
1099 eacr
.es
= eacr
.sl
= 0;
1101 set_bit(ETR_FLAG_EACCES
, &etr_flags
);
1105 * If the clock is in sync just update the eacr and return.
1106 * If there is no valid sync port wait for a port update.
1108 if (eacr
.es
|| sync_port
< 0) {
1109 etr_update_eacr(eacr
);
1110 etr_set_tolec_timeout(now
);
1115 * Prepare control register for clock syncing
1116 * (reset data port bit, set sync check control.
1122 * Update eacr and try to synchronize the clock. If the update
1123 * of eacr caused a stepping port switch (or if we have to
1124 * assume that a stepping port switch has occured) or the
1125 * clock syncing failed, reset the sync check control bit
1126 * and set up a timer to try again after 0.5 seconds
1128 etr_update_eacr(eacr
);
1129 if (now
< etr_tolec
+ (1600000 << 12) ||
1130 etr_sync_clock(&aib
, sync_port
) != 0) {
1131 /* Sync failed. Try again in 1/2 second. */
1133 etr_update_eacr(eacr
);
1134 etr_set_sync_timeout();
1136 etr_set_tolec_timeout(now
);
1140 * Sysfs interface functions
1142 static struct sysdev_class etr_sysclass
= {
1143 set_kset_name("etr")
1146 static struct sys_device etr_port0_dev
= {
1148 .cls
= &etr_sysclass
,
1151 static struct sys_device etr_port1_dev
= {
1153 .cls
= &etr_sysclass
,
1157 * ETR class attributes
1159 static ssize_t
etr_stepping_port_show(struct sysdev_class
*class, char *buf
)
1161 return sprintf(buf
, "%i\n", etr_port0
.esw
.p
);
1164 static SYSDEV_CLASS_ATTR(stepping_port
, 0400, etr_stepping_port_show
, NULL
);
1166 static ssize_t
etr_stepping_mode_show(struct sysdev_class
*class, char *buf
)
1170 if (etr_mode_is_pps(etr_eacr
))
1172 else if (etr_mode_is_etr(etr_eacr
))
1176 return sprintf(buf
, "%s\n", mode_str
);
1179 static SYSDEV_CLASS_ATTR(stepping_mode
, 0400, etr_stepping_mode_show
, NULL
);
1182 * ETR port attributes
1184 static inline struct etr_aib
*etr_aib_from_dev(struct sys_device
*dev
)
1186 if (dev
== &etr_port0_dev
)
1187 return etr_port0_online
? &etr_port0
: NULL
;
1189 return etr_port1_online
? &etr_port1
: NULL
;
1192 static ssize_t
etr_online_show(struct sys_device
*dev
, char *buf
)
1194 unsigned int online
;
1196 online
= (dev
== &etr_port0_dev
) ? etr_port0_online
: etr_port1_online
;
1197 return sprintf(buf
, "%i\n", online
);
1200 static ssize_t
etr_online_store(struct sys_device
*dev
,
1201 const char *buf
, size_t count
)
1205 value
= simple_strtoul(buf
, NULL
, 0);
1206 if (value
!= 0 && value
!= 1)
1208 if (test_bit(ETR_FLAG_ENOSYS
, &etr_flags
))
1210 if (dev
== &etr_port0_dev
) {
1211 if (etr_port0_online
== value
)
1212 return count
; /* Nothing to do. */
1213 etr_port0_online
= value
;
1214 set_bit(ETR_EVENT_PORT0_CHANGE
, &etr_events
);
1215 tasklet_hi_schedule(&etr_tasklet
);
1217 if (etr_port1_online
== value
)
1218 return count
; /* Nothing to do. */
1219 etr_port1_online
= value
;
1220 set_bit(ETR_EVENT_PORT1_CHANGE
, &etr_events
);
1221 tasklet_hi_schedule(&etr_tasklet
);
1226 static SYSDEV_ATTR(online
, 0600, etr_online_show
, etr_online_store
);
1228 static ssize_t
etr_stepping_control_show(struct sys_device
*dev
, char *buf
)
1230 return sprintf(buf
, "%i\n", (dev
== &etr_port0_dev
) ?
1231 etr_eacr
.e0
: etr_eacr
.e1
);
1234 static SYSDEV_ATTR(stepping_control
, 0400, etr_stepping_control_show
, NULL
);
1236 static ssize_t
etr_mode_code_show(struct sys_device
*dev
, char *buf
)
1238 if (!etr_port0_online
&& !etr_port1_online
)
1239 /* Status word is not uptodate if both ports are offline. */
1241 return sprintf(buf
, "%i\n", (dev
== &etr_port0_dev
) ?
1242 etr_port0
.esw
.psc0
: etr_port0
.esw
.psc1
);
1245 static SYSDEV_ATTR(state_code
, 0400, etr_mode_code_show
, NULL
);
1247 static ssize_t
etr_untuned_show(struct sys_device
*dev
, char *buf
)
1249 struct etr_aib
*aib
= etr_aib_from_dev(dev
);
1251 if (!aib
|| !aib
->slsw
.v1
)
1253 return sprintf(buf
, "%i\n", aib
->edf1
.u
);
1256 static SYSDEV_ATTR(untuned
, 0400, etr_untuned_show
, NULL
);
1258 static ssize_t
etr_network_id_show(struct sys_device
*dev
, char *buf
)
1260 struct etr_aib
*aib
= etr_aib_from_dev(dev
);
1262 if (!aib
|| !aib
->slsw
.v1
)
1264 return sprintf(buf
, "%i\n", aib
->edf1
.net_id
);
1267 static SYSDEV_ATTR(network
, 0400, etr_network_id_show
, NULL
);
1269 static ssize_t
etr_id_show(struct sys_device
*dev
, char *buf
)
1271 struct etr_aib
*aib
= etr_aib_from_dev(dev
);
1273 if (!aib
|| !aib
->slsw
.v1
)
1275 return sprintf(buf
, "%i\n", aib
->edf1
.etr_id
);
1278 static SYSDEV_ATTR(id
, 0400, etr_id_show
, NULL
);
1280 static ssize_t
etr_port_number_show(struct sys_device
*dev
, char *buf
)
1282 struct etr_aib
*aib
= etr_aib_from_dev(dev
);
1284 if (!aib
|| !aib
->slsw
.v1
)
1286 return sprintf(buf
, "%i\n", aib
->edf1
.etr_pn
);
1289 static SYSDEV_ATTR(port
, 0400, etr_port_number_show
, NULL
);
1291 static ssize_t
etr_coupled_show(struct sys_device
*dev
, char *buf
)
1293 struct etr_aib
*aib
= etr_aib_from_dev(dev
);
1295 if (!aib
|| !aib
->slsw
.v3
)
1297 return sprintf(buf
, "%i\n", aib
->edf3
.c
);
1300 static SYSDEV_ATTR(coupled
, 0400, etr_coupled_show
, NULL
);
1302 static ssize_t
etr_local_time_show(struct sys_device
*dev
, char *buf
)
1304 struct etr_aib
*aib
= etr_aib_from_dev(dev
);
1306 if (!aib
|| !aib
->slsw
.v3
)
1308 return sprintf(buf
, "%i\n", aib
->edf3
.blto
);
1311 static SYSDEV_ATTR(local_time
, 0400, etr_local_time_show
, NULL
);
1313 static ssize_t
etr_utc_offset_show(struct sys_device
*dev
, char *buf
)
1315 struct etr_aib
*aib
= etr_aib_from_dev(dev
);
1317 if (!aib
|| !aib
->slsw
.v3
)
1319 return sprintf(buf
, "%i\n", aib
->edf3
.buo
);
1322 static SYSDEV_ATTR(utc_offset
, 0400, etr_utc_offset_show
, NULL
);
1324 static struct sysdev_attribute
*etr_port_attributes
[] = {
1326 &attr_stepping_control
,
1338 static int __init
etr_register_port(struct sys_device
*dev
)
1340 struct sysdev_attribute
**attr
;
1343 rc
= sysdev_register(dev
);
1346 for (attr
= etr_port_attributes
; *attr
; attr
++) {
1347 rc
= sysdev_create_file(dev
, *attr
);
1353 for (; attr
>= etr_port_attributes
; attr
--)
1354 sysdev_remove_file(dev
, *attr
);
1355 sysdev_unregister(dev
);
1360 static void __init
etr_unregister_port(struct sys_device
*dev
)
1362 struct sysdev_attribute
**attr
;
1364 for (attr
= etr_port_attributes
; *attr
; attr
++)
1365 sysdev_remove_file(dev
, *attr
);
1366 sysdev_unregister(dev
);
1369 static int __init
etr_init_sysfs(void)
1373 rc
= sysdev_class_register(&etr_sysclass
);
1376 rc
= sysdev_class_create_file(&etr_sysclass
, &attr_stepping_port
);
1378 goto out_unreg_class
;
1379 rc
= sysdev_class_create_file(&etr_sysclass
, &attr_stepping_mode
);
1381 goto out_remove_stepping_port
;
1382 rc
= etr_register_port(&etr_port0_dev
);
1384 goto out_remove_stepping_mode
;
1385 rc
= etr_register_port(&etr_port1_dev
);
1387 goto out_remove_port0
;
1391 etr_unregister_port(&etr_port0_dev
);
1392 out_remove_stepping_mode
:
1393 sysdev_class_remove_file(&etr_sysclass
, &attr_stepping_mode
);
1394 out_remove_stepping_port
:
1395 sysdev_class_remove_file(&etr_sysclass
, &attr_stepping_port
);
1397 sysdev_class_unregister(&etr_sysclass
);
1402 device_initcall(etr_init_sysfs
);