Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable
[deliverable/linux.git] / arch / sh / boards / board-ap325rxa.c
1 /*
2 * Renesas - AP-325RXA
3 * (Compatible with Algo System ., LTD. - AP-320A)
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/sh_flctl.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/smsc911x.h>
22 #include <linux/gpio.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_gpio.h>
25 #include <media/soc_camera_platform.h>
26 #include <media/sh_mobile_ceu.h>
27 #include <video/sh_mobile_lcdc.h>
28 #include <asm/io.h>
29 #include <asm/clock.h>
30 #include <cpu/sh7723.h>
31
32 static struct smsc911x_platform_config smsc911x_config = {
33 .phy_interface = PHY_INTERFACE_MODE_MII,
34 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
35 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
36 .flags = SMSC911X_USE_32BIT,
37 };
38
39 static struct resource smsc9118_resources[] = {
40 [0] = {
41 .start = 0xb6080000,
42 .end = 0xb60fffff,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = 35,
47 .end = 35,
48 .flags = IORESOURCE_IRQ,
49 }
50 };
51
52 static struct platform_device smsc9118_device = {
53 .name = "smsc911x",
54 .id = -1,
55 .num_resources = ARRAY_SIZE(smsc9118_resources),
56 .resource = smsc9118_resources,
57 .dev = {
58 .platform_data = &smsc911x_config,
59 },
60 };
61
62 /*
63 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
64 * If this area erased, this board can not boot.
65 */
66 static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
67 {
68 .name = "uboot",
69 .offset = 0,
70 .size = (1 * 1024 * 1024),
71 .mask_flags = MTD_WRITEABLE, /* Read-only */
72 }, {
73 .name = "kernel",
74 .offset = MTDPART_OFS_APPEND,
75 .size = (2 * 1024 * 1024),
76 }, {
77 .name = "free-area0",
78 .offset = MTDPART_OFS_APPEND,
79 .size = ((7 * 1024 * 1024) + (512 * 1024)),
80 }, {
81 .name = "CPLD-Data",
82 .offset = MTDPART_OFS_APPEND,
83 .mask_flags = MTD_WRITEABLE, /* Read-only */
84 .size = (1024 * 128 * 2),
85 }, {
86 .name = "free-area1",
87 .offset = MTDPART_OFS_APPEND,
88 .size = MTDPART_SIZ_FULL,
89 },
90 };
91
92 static struct physmap_flash_data ap325rxa_nor_flash_data = {
93 .width = 2,
94 .parts = ap325rxa_nor_flash_partitions,
95 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
96 };
97
98 static struct resource ap325rxa_nor_flash_resources[] = {
99 [0] = {
100 .name = "NOR Flash",
101 .start = 0x00000000,
102 .end = 0x00ffffff,
103 .flags = IORESOURCE_MEM,
104 }
105 };
106
107 static struct platform_device ap325rxa_nor_flash_device = {
108 .name = "physmap-flash",
109 .resource = ap325rxa_nor_flash_resources,
110 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
111 .dev = {
112 .platform_data = &ap325rxa_nor_flash_data,
113 },
114 };
115
116 static struct mtd_partition nand_partition_info[] = {
117 {
118 .name = "nand_data",
119 .offset = 0,
120 .size = MTDPART_SIZ_FULL,
121 },
122 };
123
124 static struct resource nand_flash_resources[] = {
125 [0] = {
126 .start = 0xa4530000,
127 .end = 0xa45300ff,
128 .flags = IORESOURCE_MEM,
129 }
130 };
131
132 static struct sh_flctl_platform_data nand_flash_data = {
133 .parts = nand_partition_info,
134 .nr_parts = ARRAY_SIZE(nand_partition_info),
135 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
136 .has_hwecc = 1,
137 };
138
139 static struct platform_device nand_flash_device = {
140 .name = "sh_flctl",
141 .resource = nand_flash_resources,
142 .num_resources = ARRAY_SIZE(nand_flash_resources),
143 .dev = {
144 .platform_data = &nand_flash_data,
145 },
146 };
147
148 #define FPGA_LCDREG 0xB4100180
149 #define FPGA_BKLREG 0xB4100212
150 #define FPGA_LCDREG_VAL 0x0018
151 #define PORT_MSELCRB 0xA4050182
152 #define PORT_HIZCRC 0xA405015C
153 #define PORT_DRVCRA 0xA405018A
154 #define PORT_DRVCRB 0xA405018C
155
156 static void ap320_wvga_power_on(void *board_data)
157 {
158 msleep(100);
159
160 /* ASD AP-320/325 LCD ON */
161 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
162
163 /* backlight */
164 gpio_set_value(GPIO_PTS3, 0);
165 ctrl_outw(0x100, FPGA_BKLREG);
166 }
167
168 static struct sh_mobile_lcdc_info lcdc_info = {
169 .clock_source = LCDC_CLK_EXTERNAL,
170 .ch[0] = {
171 .chan = LCDC_CHAN_MAINLCD,
172 .bpp = 16,
173 .interface_type = RGB18,
174 .clock_divider = 1,
175 .lcd_cfg = {
176 .name = "LB070WV1",
177 .xres = 800,
178 .yres = 480,
179 .left_margin = 40,
180 .right_margin = 160,
181 .hsync_len = 8,
182 .upper_margin = 63,
183 .lower_margin = 80,
184 .vsync_len = 1,
185 .sync = 0, /* hsync and vsync are active low */
186 },
187 .lcd_size_cfg = { /* 7.0 inch */
188 .width = 152,
189 .height = 91,
190 },
191 .board_cfg = {
192 .display_on = ap320_wvga_power_on,
193 },
194 }
195 };
196
197 static struct resource lcdc_resources[] = {
198 [0] = {
199 .name = "LCDC",
200 .start = 0xfe940000, /* P4-only space */
201 .end = 0xfe941fff,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 .start = 28,
206 .flags = IORESOURCE_IRQ,
207 },
208 };
209
210 static struct platform_device lcdc_device = {
211 .name = "sh_mobile_lcdc_fb",
212 .num_resources = ARRAY_SIZE(lcdc_resources),
213 .resource = lcdc_resources,
214 .dev = {
215 .platform_data = &lcdc_info,
216 },
217 };
218
219 static void camera_power(int val)
220 {
221 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
222 mdelay(10);
223 }
224
225 #ifdef CONFIG_I2C
226 static unsigned char camera_ncm03j_magic[] =
227 {
228 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
229 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
230 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
231 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
232 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
233 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
234 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
235 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
236 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
237 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
238 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
239 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
240 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
241 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
242 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
243 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
244 };
245
246 static int camera_set_capture(struct soc_camera_platform_info *info,
247 int enable)
248 {
249 struct i2c_adapter *a = i2c_get_adapter(0);
250 struct i2c_msg msg;
251 int ret = 0;
252 int i;
253
254 camera_power(0);
255 if (!enable)
256 return 0; /* no disable for now */
257
258 camera_power(1);
259 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
260 u_int8_t buf[8];
261
262 msg.addr = 0x6e;
263 msg.buf = buf;
264 msg.len = 2;
265 msg.flags = 0;
266
267 buf[0] = camera_ncm03j_magic[i];
268 buf[1] = camera_ncm03j_magic[i + 1];
269
270 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
271 }
272
273 return ret;
274 }
275
276 static struct soc_camera_platform_info camera_info = {
277 .iface = 0,
278 .format_name = "UYVY",
279 .format_depth = 16,
280 .format = {
281 .pixelformat = V4L2_PIX_FMT_UYVY,
282 .colorspace = V4L2_COLORSPACE_SMPTE170M,
283 .width = 640,
284 .height = 480,
285 },
286 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
287 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
288 .set_capture = camera_set_capture,
289 };
290
291 static struct platform_device camera_device = {
292 .name = "soc_camera_platform",
293 .dev = {
294 .platform_data = &camera_info,
295 },
296 };
297 #endif /* CONFIG_I2C */
298
299 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
300 .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
301 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
302 };
303
304 static struct resource ceu_resources[] = {
305 [0] = {
306 .name = "CEU",
307 .start = 0xfe910000,
308 .end = 0xfe91009f,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = 52,
313 .flags = IORESOURCE_IRQ,
314 },
315 [2] = {
316 /* place holder for contiguous memory */
317 },
318 };
319
320 static struct platform_device ceu_device = {
321 .name = "sh_mobile_ceu",
322 .id = 0, /* "ceu0" clock */
323 .num_resources = ARRAY_SIZE(ceu_resources),
324 .resource = ceu_resources,
325 .dev = {
326 .platform_data = &sh_mobile_ceu_info,
327 },
328 };
329
330 struct spi_gpio_platform_data sdcard_cn3_platform_data = {
331 .sck = GPIO_PTD0,
332 .mosi = GPIO_PTD1,
333 .miso = GPIO_PTD2,
334 .num_chipselect = 1,
335 };
336
337 static struct platform_device sdcard_cn3_device = {
338 .name = "spi_gpio",
339 .dev = {
340 .platform_data = &sdcard_cn3_platform_data,
341 },
342 };
343
344 static struct platform_device *ap325rxa_devices[] __initdata = {
345 &smsc9118_device,
346 &ap325rxa_nor_flash_device,
347 &lcdc_device,
348 &ceu_device,
349 #ifdef CONFIG_I2C
350 &camera_device,
351 #endif
352 &nand_flash_device,
353 &sdcard_cn3_device,
354 };
355
356 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
357 {
358 I2C_BOARD_INFO("pcf8563", 0x51),
359 },
360 };
361
362 static struct spi_board_info ap325rxa_spi_devices[] = {
363 {
364 .modalias = "mmc_spi",
365 .max_speed_hz = 5000000,
366 .chip_select = 0,
367 .controller_data = (void *) GPIO_PTD5,
368 },
369 };
370
371 static int __init ap325rxa_devices_setup(void)
372 {
373 /* LD3 and LD4 LEDs */
374 gpio_request(GPIO_PTX5, NULL); /* RUN */
375 gpio_direction_output(GPIO_PTX5, 1);
376 gpio_export(GPIO_PTX5, 0);
377
378 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
379 gpio_direction_output(GPIO_PTX4, 0);
380 gpio_export(GPIO_PTX4, 0);
381
382 /* SW1 input */
383 gpio_request(GPIO_PTF7, NULL); /* MODE */
384 gpio_direction_input(GPIO_PTF7);
385 gpio_export(GPIO_PTF7, 0);
386
387 /* LCDC */
388 gpio_request(GPIO_FN_LCDD15, NULL);
389 gpio_request(GPIO_FN_LCDD14, NULL);
390 gpio_request(GPIO_FN_LCDD13, NULL);
391 gpio_request(GPIO_FN_LCDD12, NULL);
392 gpio_request(GPIO_FN_LCDD11, NULL);
393 gpio_request(GPIO_FN_LCDD10, NULL);
394 gpio_request(GPIO_FN_LCDD9, NULL);
395 gpio_request(GPIO_FN_LCDD8, NULL);
396 gpio_request(GPIO_FN_LCDD7, NULL);
397 gpio_request(GPIO_FN_LCDD6, NULL);
398 gpio_request(GPIO_FN_LCDD5, NULL);
399 gpio_request(GPIO_FN_LCDD4, NULL);
400 gpio_request(GPIO_FN_LCDD3, NULL);
401 gpio_request(GPIO_FN_LCDD2, NULL);
402 gpio_request(GPIO_FN_LCDD1, NULL);
403 gpio_request(GPIO_FN_LCDD0, NULL);
404 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
405 gpio_request(GPIO_FN_LCDDCK, NULL);
406 gpio_request(GPIO_FN_LCDVEPWC, NULL);
407 gpio_request(GPIO_FN_LCDVCPWC, NULL);
408 gpio_request(GPIO_FN_LCDVSYN, NULL);
409 gpio_request(GPIO_FN_LCDHSYN, NULL);
410 gpio_request(GPIO_FN_LCDDISP, NULL);
411 gpio_request(GPIO_FN_LCDDON, NULL);
412
413 /* LCD backlight */
414 gpio_request(GPIO_PTS3, NULL);
415 gpio_direction_output(GPIO_PTS3, 1);
416
417 /* CEU */
418 gpio_request(GPIO_FN_VIO_CLK2, NULL);
419 gpio_request(GPIO_FN_VIO_VD2, NULL);
420 gpio_request(GPIO_FN_VIO_HD2, NULL);
421 gpio_request(GPIO_FN_VIO_FLD, NULL);
422 gpio_request(GPIO_FN_VIO_CKO, NULL);
423 gpio_request(GPIO_FN_VIO_D15, NULL);
424 gpio_request(GPIO_FN_VIO_D14, NULL);
425 gpio_request(GPIO_FN_VIO_D13, NULL);
426 gpio_request(GPIO_FN_VIO_D12, NULL);
427 gpio_request(GPIO_FN_VIO_D11, NULL);
428 gpio_request(GPIO_FN_VIO_D10, NULL);
429 gpio_request(GPIO_FN_VIO_D9, NULL);
430 gpio_request(GPIO_FN_VIO_D8, NULL);
431
432 gpio_request(GPIO_PTZ7, NULL);
433 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
434 gpio_request(GPIO_PTZ6, NULL);
435 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
436 gpio_request(GPIO_PTZ5, NULL);
437 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
438 gpio_request(GPIO_PTZ4, NULL);
439 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
440
441 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
442
443 /* FLCTL */
444 gpio_request(GPIO_FN_FCE, NULL);
445 gpio_request(GPIO_FN_NAF7, NULL);
446 gpio_request(GPIO_FN_NAF6, NULL);
447 gpio_request(GPIO_FN_NAF5, NULL);
448 gpio_request(GPIO_FN_NAF4, NULL);
449 gpio_request(GPIO_FN_NAF3, NULL);
450 gpio_request(GPIO_FN_NAF2, NULL);
451 gpio_request(GPIO_FN_NAF1, NULL);
452 gpio_request(GPIO_FN_NAF0, NULL);
453 gpio_request(GPIO_FN_FCDE, NULL);
454 gpio_request(GPIO_FN_FOE, NULL);
455 gpio_request(GPIO_FN_FSC, NULL);
456 gpio_request(GPIO_FN_FWE, NULL);
457 gpio_request(GPIO_FN_FRB, NULL);
458
459 ctrl_outw(0, PORT_HIZCRC);
460 ctrl_outw(0xFFFF, PORT_DRVCRA);
461 ctrl_outw(0xFFFF, PORT_DRVCRB);
462
463 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
464
465 i2c_register_board_info(0, ap325rxa_i2c_devices,
466 ARRAY_SIZE(ap325rxa_i2c_devices));
467
468 spi_register_board_info(ap325rxa_spi_devices,
469 ARRAY_SIZE(ap325rxa_spi_devices));
470
471 return platform_add_devices(ap325rxa_devices,
472 ARRAY_SIZE(ap325rxa_devices));
473 }
474 device_initcall(ap325rxa_devices_setup);
475
476 static struct sh_machine_vector mv_ap325rxa __initmv = {
477 .mv_name = "AP-325RXA",
478 };
This page took 0.043687 seconds and 6 git commands to generate.