Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[deliverable/linux.git] / arch / sh / boards / board-ap325rxa.c
1 /*
2 * Renesas - AP-325RXA
3 * (Compatible with Algo System ., LTD. - AP-320A)
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/sh_flctl.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/smsc911x.h>
22 #include <linux/gpio.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_gpio.h>
25 #include <media/ov772x.h>
26 #include <media/soc_camera_platform.h>
27 #include <media/sh_mobile_ceu.h>
28 #include <video/sh_mobile_lcdc.h>
29 #include <asm/io.h>
30 #include <asm/clock.h>
31 #include <cpu/sh7723.h>
32
33 static struct smsc911x_platform_config smsc911x_config = {
34 .phy_interface = PHY_INTERFACE_MODE_MII,
35 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
36 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
37 .flags = SMSC911X_USE_32BIT,
38 };
39
40 static struct resource smsc9118_resources[] = {
41 [0] = {
42 .start = 0xb6080000,
43 .end = 0xb60fffff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = 35,
48 .end = 35,
49 .flags = IORESOURCE_IRQ,
50 }
51 };
52
53 static struct platform_device smsc9118_device = {
54 .name = "smsc911x",
55 .id = -1,
56 .num_resources = ARRAY_SIZE(smsc9118_resources),
57 .resource = smsc9118_resources,
58 .dev = {
59 .platform_data = &smsc911x_config,
60 },
61 };
62
63 /*
64 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
65 * If this area erased, this board can not boot.
66 */
67 static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
68 {
69 .name = "uboot",
70 .offset = 0,
71 .size = (1 * 1024 * 1024),
72 .mask_flags = MTD_WRITEABLE, /* Read-only */
73 }, {
74 .name = "kernel",
75 .offset = MTDPART_OFS_APPEND,
76 .size = (2 * 1024 * 1024),
77 }, {
78 .name = "free-area0",
79 .offset = MTDPART_OFS_APPEND,
80 .size = ((7 * 1024 * 1024) + (512 * 1024)),
81 }, {
82 .name = "CPLD-Data",
83 .offset = MTDPART_OFS_APPEND,
84 .mask_flags = MTD_WRITEABLE, /* Read-only */
85 .size = (1024 * 128 * 2),
86 }, {
87 .name = "free-area1",
88 .offset = MTDPART_OFS_APPEND,
89 .size = MTDPART_SIZ_FULL,
90 },
91 };
92
93 static struct physmap_flash_data ap325rxa_nor_flash_data = {
94 .width = 2,
95 .parts = ap325rxa_nor_flash_partitions,
96 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
97 };
98
99 static struct resource ap325rxa_nor_flash_resources[] = {
100 [0] = {
101 .name = "NOR Flash",
102 .start = 0x00000000,
103 .end = 0x00ffffff,
104 .flags = IORESOURCE_MEM,
105 }
106 };
107
108 static struct platform_device ap325rxa_nor_flash_device = {
109 .name = "physmap-flash",
110 .resource = ap325rxa_nor_flash_resources,
111 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
112 .dev = {
113 .platform_data = &ap325rxa_nor_flash_data,
114 },
115 };
116
117 static struct mtd_partition nand_partition_info[] = {
118 {
119 .name = "nand_data",
120 .offset = 0,
121 .size = MTDPART_SIZ_FULL,
122 },
123 };
124
125 static struct resource nand_flash_resources[] = {
126 [0] = {
127 .start = 0xa4530000,
128 .end = 0xa45300ff,
129 .flags = IORESOURCE_MEM,
130 }
131 };
132
133 static struct sh_flctl_platform_data nand_flash_data = {
134 .parts = nand_partition_info,
135 .nr_parts = ARRAY_SIZE(nand_partition_info),
136 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
137 .has_hwecc = 1,
138 };
139
140 static struct platform_device nand_flash_device = {
141 .name = "sh_flctl",
142 .resource = nand_flash_resources,
143 .num_resources = ARRAY_SIZE(nand_flash_resources),
144 .dev = {
145 .platform_data = &nand_flash_data,
146 },
147 };
148
149 #define FPGA_LCDREG 0xB4100180
150 #define FPGA_BKLREG 0xB4100212
151 #define FPGA_LCDREG_VAL 0x0018
152 #define PORT_MSELCRB 0xA4050182
153 #define PORT_HIZCRC 0xA405015C
154 #define PORT_DRVCRA 0xA405018A
155 #define PORT_DRVCRB 0xA405018C
156
157 static void ap320_wvga_power_on(void *board_data)
158 {
159 msleep(100);
160
161 /* ASD AP-320/325 LCD ON */
162 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
163
164 /* backlight */
165 gpio_set_value(GPIO_PTS3, 0);
166 ctrl_outw(0x100, FPGA_BKLREG);
167 }
168
169 static struct sh_mobile_lcdc_info lcdc_info = {
170 .clock_source = LCDC_CLK_EXTERNAL,
171 .ch[0] = {
172 .chan = LCDC_CHAN_MAINLCD,
173 .bpp = 16,
174 .interface_type = RGB18,
175 .clock_divider = 1,
176 .lcd_cfg = {
177 .name = "LB070WV1",
178 .xres = 800,
179 .yres = 480,
180 .left_margin = 40,
181 .right_margin = 160,
182 .hsync_len = 8,
183 .upper_margin = 63,
184 .lower_margin = 80,
185 .vsync_len = 1,
186 .sync = 0, /* hsync and vsync are active low */
187 },
188 .lcd_size_cfg = { /* 7.0 inch */
189 .width = 152,
190 .height = 91,
191 },
192 .board_cfg = {
193 .display_on = ap320_wvga_power_on,
194 },
195 }
196 };
197
198 static struct resource lcdc_resources[] = {
199 [0] = {
200 .name = "LCDC",
201 .start = 0xfe940000, /* P4-only space */
202 .end = 0xfe941fff,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = 28,
207 .flags = IORESOURCE_IRQ,
208 },
209 };
210
211 static struct platform_device lcdc_device = {
212 .name = "sh_mobile_lcdc_fb",
213 .num_resources = ARRAY_SIZE(lcdc_resources),
214 .resource = lcdc_resources,
215 .dev = {
216 .platform_data = &lcdc_info,
217 },
218 };
219
220 static void camera_power(int val)
221 {
222 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
223 mdelay(10);
224 }
225
226 #ifdef CONFIG_I2C
227 /* support for the old ncm03j camera */
228 static unsigned char camera_ncm03j_magic[] =
229 {
230 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
231 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
232 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
233 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
234 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
235 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
236 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
237 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
238 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
239 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
240 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
241 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
242 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
243 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
244 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
245 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
246 };
247
248 static int camera_probe(void)
249 {
250 struct i2c_adapter *a = i2c_get_adapter(0);
251 struct i2c_msg msg;
252 int ret;
253
254 camera_power(1);
255 msg.addr = 0x6e;
256 msg.buf = camera_ncm03j_magic;
257 msg.len = 2;
258 msg.flags = 0;
259 ret = i2c_transfer(a, &msg, 1);
260 camera_power(0);
261
262 return ret;
263 }
264
265 static int camera_set_capture(struct soc_camera_platform_info *info,
266 int enable)
267 {
268 struct i2c_adapter *a = i2c_get_adapter(0);
269 struct i2c_msg msg;
270 int ret = 0;
271 int i;
272
273 camera_power(0);
274 if (!enable)
275 return 0; /* no disable for now */
276
277 camera_power(1);
278 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
279 u_int8_t buf[8];
280
281 msg.addr = 0x6e;
282 msg.buf = buf;
283 msg.len = 2;
284 msg.flags = 0;
285
286 buf[0] = camera_ncm03j_magic[i];
287 buf[1] = camera_ncm03j_magic[i + 1];
288
289 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
290 }
291
292 return ret;
293 }
294
295 static struct soc_camera_platform_info camera_info = {
296 .iface = 0,
297 .format_name = "UYVY",
298 .format_depth = 16,
299 .format = {
300 .pixelformat = V4L2_PIX_FMT_UYVY,
301 .colorspace = V4L2_COLORSPACE_SMPTE170M,
302 .width = 640,
303 .height = 480,
304 },
305 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
306 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
307 .set_capture = camera_set_capture,
308 };
309
310 static struct platform_device camera_device = {
311 .name = "soc_camera_platform",
312 .dev = {
313 .platform_data = &camera_info,
314 },
315 };
316
317 static int __init camera_setup(void)
318 {
319 if (camera_probe() > 0)
320 platform_device_register(&camera_device);
321
322 return 0;
323 }
324 late_initcall(camera_setup);
325
326 #endif /* CONFIG_I2C */
327
328 static int ov7725_power(struct device *dev, int mode)
329 {
330 camera_power(0);
331 if (mode)
332 camera_power(1);
333
334 return 0;
335 }
336
337 static struct ov772x_camera_info ov7725_info = {
338 .buswidth = SOCAM_DATAWIDTH_8,
339 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
340 .link = {
341 .power = ov7725_power,
342 },
343 };
344
345 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
346 .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
347 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
348 };
349
350 static struct resource ceu_resources[] = {
351 [0] = {
352 .name = "CEU",
353 .start = 0xfe910000,
354 .end = 0xfe91009f,
355 .flags = IORESOURCE_MEM,
356 },
357 [1] = {
358 .start = 52,
359 .flags = IORESOURCE_IRQ,
360 },
361 [2] = {
362 /* place holder for contiguous memory */
363 },
364 };
365
366 static struct platform_device ceu_device = {
367 .name = "sh_mobile_ceu",
368 .id = 0, /* "ceu0" clock */
369 .num_resources = ARRAY_SIZE(ceu_resources),
370 .resource = ceu_resources,
371 .dev = {
372 .platform_data = &sh_mobile_ceu_info,
373 },
374 };
375
376 struct spi_gpio_platform_data sdcard_cn3_platform_data = {
377 .sck = GPIO_PTD0,
378 .mosi = GPIO_PTD1,
379 .miso = GPIO_PTD2,
380 .num_chipselect = 1,
381 };
382
383 static struct platform_device sdcard_cn3_device = {
384 .name = "spi_gpio",
385 .dev = {
386 .platform_data = &sdcard_cn3_platform_data,
387 },
388 };
389
390 static struct platform_device *ap325rxa_devices[] __initdata = {
391 &smsc9118_device,
392 &ap325rxa_nor_flash_device,
393 &lcdc_device,
394 &ceu_device,
395 &nand_flash_device,
396 &sdcard_cn3_device,
397 };
398
399 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
400 {
401 I2C_BOARD_INFO("pcf8563", 0x51),
402 },
403 {
404 I2C_BOARD_INFO("ov772x", 0x21),
405 .platform_data = &ov7725_info,
406 },
407 };
408
409 static struct spi_board_info ap325rxa_spi_devices[] = {
410 {
411 .modalias = "mmc_spi",
412 .max_speed_hz = 5000000,
413 .chip_select = 0,
414 .controller_data = (void *) GPIO_PTD5,
415 },
416 };
417
418 static int __init ap325rxa_devices_setup(void)
419 {
420 /* LD3 and LD4 LEDs */
421 gpio_request(GPIO_PTX5, NULL); /* RUN */
422 gpio_direction_output(GPIO_PTX5, 1);
423 gpio_export(GPIO_PTX5, 0);
424
425 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
426 gpio_direction_output(GPIO_PTX4, 0);
427 gpio_export(GPIO_PTX4, 0);
428
429 /* SW1 input */
430 gpio_request(GPIO_PTF7, NULL); /* MODE */
431 gpio_direction_input(GPIO_PTF7);
432 gpio_export(GPIO_PTF7, 0);
433
434 /* LCDC */
435 gpio_request(GPIO_FN_LCDD15, NULL);
436 gpio_request(GPIO_FN_LCDD14, NULL);
437 gpio_request(GPIO_FN_LCDD13, NULL);
438 gpio_request(GPIO_FN_LCDD12, NULL);
439 gpio_request(GPIO_FN_LCDD11, NULL);
440 gpio_request(GPIO_FN_LCDD10, NULL);
441 gpio_request(GPIO_FN_LCDD9, NULL);
442 gpio_request(GPIO_FN_LCDD8, NULL);
443 gpio_request(GPIO_FN_LCDD7, NULL);
444 gpio_request(GPIO_FN_LCDD6, NULL);
445 gpio_request(GPIO_FN_LCDD5, NULL);
446 gpio_request(GPIO_FN_LCDD4, NULL);
447 gpio_request(GPIO_FN_LCDD3, NULL);
448 gpio_request(GPIO_FN_LCDD2, NULL);
449 gpio_request(GPIO_FN_LCDD1, NULL);
450 gpio_request(GPIO_FN_LCDD0, NULL);
451 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
452 gpio_request(GPIO_FN_LCDDCK, NULL);
453 gpio_request(GPIO_FN_LCDVEPWC, NULL);
454 gpio_request(GPIO_FN_LCDVCPWC, NULL);
455 gpio_request(GPIO_FN_LCDVSYN, NULL);
456 gpio_request(GPIO_FN_LCDHSYN, NULL);
457 gpio_request(GPIO_FN_LCDDISP, NULL);
458 gpio_request(GPIO_FN_LCDDON, NULL);
459
460 /* LCD backlight */
461 gpio_request(GPIO_PTS3, NULL);
462 gpio_direction_output(GPIO_PTS3, 1);
463
464 /* CEU */
465 gpio_request(GPIO_FN_VIO_CLK2, NULL);
466 gpio_request(GPIO_FN_VIO_VD2, NULL);
467 gpio_request(GPIO_FN_VIO_HD2, NULL);
468 gpio_request(GPIO_FN_VIO_FLD, NULL);
469 gpio_request(GPIO_FN_VIO_CKO, NULL);
470 gpio_request(GPIO_FN_VIO_D15, NULL);
471 gpio_request(GPIO_FN_VIO_D14, NULL);
472 gpio_request(GPIO_FN_VIO_D13, NULL);
473 gpio_request(GPIO_FN_VIO_D12, NULL);
474 gpio_request(GPIO_FN_VIO_D11, NULL);
475 gpio_request(GPIO_FN_VIO_D10, NULL);
476 gpio_request(GPIO_FN_VIO_D9, NULL);
477 gpio_request(GPIO_FN_VIO_D8, NULL);
478
479 gpio_request(GPIO_PTZ7, NULL);
480 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
481 gpio_request(GPIO_PTZ6, NULL);
482 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
483 gpio_request(GPIO_PTZ5, NULL);
484 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
485 gpio_request(GPIO_PTZ4, NULL);
486 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
487
488 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
489
490 /* FLCTL */
491 gpio_request(GPIO_FN_FCE, NULL);
492 gpio_request(GPIO_FN_NAF7, NULL);
493 gpio_request(GPIO_FN_NAF6, NULL);
494 gpio_request(GPIO_FN_NAF5, NULL);
495 gpio_request(GPIO_FN_NAF4, NULL);
496 gpio_request(GPIO_FN_NAF3, NULL);
497 gpio_request(GPIO_FN_NAF2, NULL);
498 gpio_request(GPIO_FN_NAF1, NULL);
499 gpio_request(GPIO_FN_NAF0, NULL);
500 gpio_request(GPIO_FN_FCDE, NULL);
501 gpio_request(GPIO_FN_FOE, NULL);
502 gpio_request(GPIO_FN_FSC, NULL);
503 gpio_request(GPIO_FN_FWE, NULL);
504 gpio_request(GPIO_FN_FRB, NULL);
505
506 ctrl_outw(0, PORT_HIZCRC);
507 ctrl_outw(0xFFFF, PORT_DRVCRA);
508 ctrl_outw(0xFFFF, PORT_DRVCRB);
509
510 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
511
512 i2c_register_board_info(0, ap325rxa_i2c_devices,
513 ARRAY_SIZE(ap325rxa_i2c_devices));
514
515 spi_register_board_info(ap325rxa_spi_devices,
516 ARRAY_SIZE(ap325rxa_spi_devices));
517
518 return platform_add_devices(ap325rxa_devices,
519 ARRAY_SIZE(ap325rxa_devices));
520 }
521 device_initcall(ap325rxa_devices_setup);
522
523 static struct sh_machine_vector mv_ap325rxa __initmv = {
524 .mv_name = "AP-325RXA",
525 };
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