arch/sh/boards/mach-se/7343/irq.c

   1 /*
   2  * linux/arch/sh/boards/se/7343/irq.c
   3  *
   4  * Copyright (C) 2008  Yoshihiro Shimoda
   5  *
   6  * Based on linux/arch/sh/boards/se/7722/irq.c
   7  * Copyright (C) 2007  Nobuhiro Iwamatsu
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/io.h>
  18 #include <mach-se/mach/se7343.h>
  19
  20 static void disable_se7343_irq(unsigned int irq)
  21 {
  22         unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
  23         ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
  24 }
  25
  26 static void enable_se7343_irq(unsigned int irq)
  27 {
  28         unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
  29         ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
  30 }
  31
  32 static struct irq_chip se7343_irq_chip __read_mostly = {
  33         .name           = "SE7343-FPGA",
  34         .mask           = disable_se7343_irq,
  35         .unmask         = enable_se7343_irq,
  36         .mask_ack       = disable_se7343_irq,
  37 };
  38
  39 static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
  40 {
  41         unsigned short intv = ctrl_inw(PA_CPLD_ST);
  42         struct irq_desc *ext_desc;
  43         unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
  44
  45         intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
  46
  47         while (intv) {
  48                 if (intv & 1) {
  49                         ext_desc = irq_desc + ext_irq;
  50                         handle_level_irq(ext_irq, ext_desc);
  51                 }
  52                 intv >>= 1;
  53                 ext_irq++;
  54         }
  55 }
  56
  57 /*
  58  * Initialize IRQ setting
  59  */
  60 void __init init_7343se_IRQ(void)
  61 {
  62         int i;
  63
  64         ctrl_outw(0, PA_CPLD_IMSK);     /* disable all irqs */
  65         ctrl_outw(0x2000, 0xb03fffec);  /* mrshpc irq enable */
  66
  67         for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
  68                 set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
  69                                               &se7343_irq_chip,
  70                                               handle_level_irq, "level");
  71
  72         set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
  73         set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
  74         set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
  75         set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
  76         set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
  77         set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
  78         set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
  79         set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
  80 }