arch/sh/boards/mach-se/7343/irq.c

   1 /*
   2  * linux/arch/sh/boards/se/7343/irq.c
   3  *
   4  * Copyright (C) 2008  Yoshihiro Shimoda
   5  *
   6  * Based on linux/arch/sh/boards/se/7722/irq.c
   7  * Copyright (C) 2007  Nobuhiro Iwamatsu
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <mach-se/mach/se7343.h>
  18
  19 static void disable_se7343_irq(unsigned int irq)
  20 {
  21         unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
  22         ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
  23 }
  24
  25 static void enable_se7343_irq(unsigned int irq)
  26 {
  27         unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
  28         ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
  29 }
  30
  31 static struct irq_chip se7343_irq_chip __read_mostly = {
  32         .name           = "SE7343-FPGA",
  33         .mask           = disable_se7343_irq,
  34         .unmask         = enable_se7343_irq,
  35         .mask_ack       = disable_se7343_irq,
  36 };
  37
  38 static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
  39 {
  40         unsigned short intv = ctrl_inw(PA_CPLD_ST);
  41         struct irq_desc *ext_desc;
  42         unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
  43
  44         intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
  45
  46         while (intv) {
  47                 if (intv & 1) {
  48                         ext_desc = irq_desc + ext_irq;
  49                         handle_level_irq(ext_irq, ext_desc);
  50                 }
  51                 intv >>= 1;
  52                 ext_irq++;
  53         }
  54 }
  55
  56 /*
  57  * Initialize IRQ setting
  58  */
  59 void __init init_7343se_IRQ(void)
  60 {
  61         int i;
  62
  63         ctrl_outw(0, PA_CPLD_IMSK);     /* disable all irqs */
  64         ctrl_outw(0x2000, 0xb03fffec);  /* mrshpc irq enable */
  65
  66         for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
  67                 set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
  68                                               &se7343_irq_chip,
  69                                               handle_level_irq, "level");
  70
  71         set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
  72         set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
  73         set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
  74         set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
  75         set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
  76         set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
  77         set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
  78         set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
  79 }