arch/sh/boards/renesas/r7780rp/irq-r7785rp.c

   1 /*
   2  * Renesas Solutions Highlander R7785RP Support.
   3  *
   4  * Copyright (C) 2002  Atom Create Engineering Co., Ltd.
   5  * Copyright (C) 2006  Paul Mundt
   6  * Copyright (C) 2007  Magnus Damm
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/irq.h>
  14 #include <linux/io.h>
  15 #include <asm/r7780rp.h>
  16
  17 enum {
  18         UNUSED = 0,
  19
  20         /* board specific interrupt sources */
  21         AX88796,          /* Ethernet controller */
  22         CF,               /* Compact Flash */
  23 };
  24
  25 static struct intc_vect vectors[] __initdata = {
  26         INTC_IRQ(CF, IRQ_CF),
  27         INTC_IRQ(AX88796, IRQ_AX88796),
  28 };
  29
  30 static struct intc_mask_reg mask_registers[] __initdata = {
  31         { 0xa4000010, 0, 16, /* IRLMCR1 */
  32           { 0, 0, 0, 0, CF, AX88796, 0, 0,
  33             0, 0, 0, 0, 0, 0, 0, 0 } },
  34 };
  35
  36 static unsigned char irl2irq[HL_NR_IRL] __initdata = {
  37         0, IRQ_CF, 0, 0,
  38         0, 0, 0, 0,
  39         0, 0, IRQ_AX88796, 0,
  40         0, 0, 0,
  41 };
  42
  43 static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
  44                          NULL, NULL, mask_registers, NULL, NULL);
  45
  46 unsigned char * __init highlander_init_irq_r7785rp(void)
  47 {
  48         if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000)
  49                 return NULL;
  50
  51         printk(KERN_INFO "Using r7785rp interrupt controller.\n");
  52
  53         ctrl_outw(0x0000, PA_IRLSSR1);  /* FPGA IRLSSR1(CF_CD clear) */
  54
  55         /* Setup the FPGA IRL */
  56         ctrl_outw(0x0000, PA_IRLPRA);   /* FPGA IRLA */
  57         ctrl_outw(0xe598, PA_IRLPRB);   /* FPGA IRLB */
  58         ctrl_outw(0x7060, PA_IRLPRC);   /* FPGA IRLC */
  59         ctrl_outw(0x0000, PA_IRLPRD);   /* FPGA IRLD */
  60         ctrl_outw(0x4321, PA_IRLPRE);   /* FPGA IRLE */
  61         ctrl_outw(0x0000, PA_IRLPRF);   /* FPGA IRLF */
  62
  63         register_intc_controller(&intc_desc);
  64         return irl2irq;
  65 }