2 * arch/sh/drivers/dma/dma-sh.c
4 * SuperH On-chip DMAC Support
6 * Copyright (C) 2000 Takashi YOSHII
7 * Copyright (C) 2003, 2004 Paul Mundt
8 * Copyright (C) 2005 Andriy Skulysh
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <asm/dreamcast/dma.h>
22 static int dmte_irq_map
[] = {
27 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7760) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7780)
37 static inline unsigned int get_dmte_irq(unsigned int chan
)
40 if (chan
< ARRAY_SIZE(dmte_irq_map
))
41 irq
= dmte_irq_map
[chan
];
46 * We determine the correct shift size based off of the CHCR transmit size
47 * for the given channel. Since we know that it will take:
49 * info->count >> ts_shift[transmit_size]
51 * iterations to complete the transfer.
53 static inline unsigned int calc_xmit_shift(struct dma_channel
*chan
)
55 u32 chcr
= ctrl_inl(CHCR
[chan
->chan
]);
57 return ts_shift
[(chcr
& CHCR_TS_MASK
)>>CHCR_TS_SHIFT
];
61 * The transfer end interrupt must read the chcr register to end the
62 * hardware interrupt active condition.
63 * Besides that it needs to waken any waiting process, which should handle
64 * setting up the next transfer.
66 static irqreturn_t
dma_tei(int irq
, void *dev_id
)
68 struct dma_channel
*chan
= dev_id
;
71 chcr
= ctrl_inl(CHCR
[chan
->chan
]);
73 if (!(chcr
& CHCR_TE
))
76 chcr
&= ~(CHCR_IE
| CHCR_DE
);
77 ctrl_outl(chcr
, CHCR
[chan
->chan
]);
79 wake_up(&chan
->wait_queue
);
84 static int sh_dmac_request_dma(struct dma_channel
*chan
)
86 if (unlikely(!chan
->flags
& DMA_TEI_CAPABLE
))
89 return request_irq(get_dmte_irq(chan
->chan
), dma_tei
,
90 IRQF_DISABLED
, chan
->dev_id
, chan
);
93 static void sh_dmac_free_dma(struct dma_channel
*chan
)
95 free_irq(get_dmte_irq(chan
->chan
), chan
);
99 sh_dmac_configure_channel(struct dma_channel
*chan
, unsigned long chcr
)
102 chcr
= RS_DUAL
| CHCR_IE
;
104 if (chcr
& CHCR_IE
) {
106 chan
->flags
|= DMA_TEI_CAPABLE
;
108 chan
->flags
&= ~DMA_TEI_CAPABLE
;
111 ctrl_outl(chcr
, CHCR
[chan
->chan
]);
113 chan
->flags
|= DMA_CONFIGURED
;
117 static void sh_dmac_enable_dma(struct dma_channel
*chan
)
122 chcr
= ctrl_inl(CHCR
[chan
->chan
]);
125 if (chan
->flags
& DMA_TEI_CAPABLE
)
128 ctrl_outl(chcr
, CHCR
[chan
->chan
]);
130 if (chan
->flags
& DMA_TEI_CAPABLE
) {
131 irq
= get_dmte_irq(chan
->chan
);
136 static void sh_dmac_disable_dma(struct dma_channel
*chan
)
141 if (chan
->flags
& DMA_TEI_CAPABLE
) {
142 irq
= get_dmte_irq(chan
->chan
);
146 chcr
= ctrl_inl(CHCR
[chan
->chan
]);
147 chcr
&= ~(CHCR_DE
| CHCR_TE
| CHCR_IE
);
148 ctrl_outl(chcr
, CHCR
[chan
->chan
]);
151 static int sh_dmac_xfer_dma(struct dma_channel
*chan
)
154 * If we haven't pre-configured the channel with special flags, use
157 if (unlikely(!(chan
->flags
& DMA_CONFIGURED
)))
158 sh_dmac_configure_channel(chan
, 0);
160 sh_dmac_disable_dma(chan
);
163 * Single-address mode usage note!
165 * It's important that we don't accidentally write any value to SAR/DAR
166 * (this includes 0) that hasn't been directly specified by the user if
167 * we're in single-address mode.
169 * In this case, only one address can be defined, anything else will
170 * result in a DMA address error interrupt (at least on the SH-4),
171 * which will subsequently halt the transfer.
173 * Channel 2 on the Dreamcast is a special case, as this is used for
174 * cascading to the PVR2 DMAC. In this case, we still need to write
175 * SAR and DAR, regardless of value, in order for cascading to work.
177 if (chan
->sar
|| (mach_is_dreamcast() &&
178 chan
->chan
== PVR2_CASCADE_CHAN
))
179 ctrl_outl(chan
->sar
, SAR
[chan
->chan
]);
180 if (chan
->dar
|| (mach_is_dreamcast() &&
181 chan
->chan
== PVR2_CASCADE_CHAN
))
182 ctrl_outl(chan
->dar
, DAR
[chan
->chan
]);
184 ctrl_outl(chan
->count
>> calc_xmit_shift(chan
), DMATCR
[chan
->chan
]);
186 sh_dmac_enable_dma(chan
);
191 static int sh_dmac_get_dma_residue(struct dma_channel
*chan
)
193 if (!(ctrl_inl(CHCR
[chan
->chan
]) & CHCR_DE
))
196 return ctrl_inl(DMATCR
[chan
->chan
]) << calc_xmit_shift(chan
);
199 #ifdef CONFIG_CPU_SUBTYPE_SH7780
200 #define dmaor_read_reg() ctrl_inw(DMAOR)
201 #define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
203 #define dmaor_read_reg() ctrl_inl(DMAOR)
204 #define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
207 static inline int dmaor_reset(void)
209 unsigned long dmaor
= dmaor_read_reg();
211 /* Try to clear the error flags first, incase they are set */
212 dmaor
&= ~(DMAOR_NMIF
| DMAOR_AE
);
213 dmaor_write_reg(dmaor
);
216 dmaor_write_reg(dmaor
);
218 /* See if we got an error again */
219 if ((dmaor_read_reg() & (DMAOR_AE
| DMAOR_NMIF
))) {
220 printk(KERN_ERR
"dma-sh: Can't initialize DMAOR.\n");
227 #if defined(CONFIG_CPU_SH4)
228 static irqreturn_t
dma_err(int irq
, void *dummy
)
237 static struct dma_ops sh_dmac_ops
= {
238 .request
= sh_dmac_request_dma
,
239 .free
= sh_dmac_free_dma
,
240 .get_residue
= sh_dmac_get_dma_residue
,
241 .xfer
= sh_dmac_xfer_dma
,
242 .configure
= sh_dmac_configure_channel
,
245 static struct dma_info sh_dmac_info
= {
247 .nr_channels
= CONFIG_NR_ONCHIP_DMA_CHANNELS
,
249 .flags
= DMAC_CHANNELS_TEI_CAPABLE
,
252 static int __init
sh_dmac_init(void)
254 struct dma_info
*info
= &sh_dmac_info
;
257 #ifdef CONFIG_CPU_SH4
258 i
= request_irq(DMAE_IRQ
, dma_err
, IRQF_DISABLED
, "DMAC Address Error", 0);
264 * Initialize DMAOR, and clean up any error flags that may have
268 if (unlikely(i
!= 0))
271 return register_dmac(info
);
274 static void __exit
sh_dmac_exit(void)
276 #ifdef CONFIG_CPU_SH4
277 free_irq(DMAE_IRQ
, 0);
279 unregister_dmac(&sh_dmac_info
);
282 subsys_initcall(sh_dmac_init
);
283 module_exit(sh_dmac_exit
);
285 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
286 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
287 MODULE_LICENSE("GPL");