arch/sh/drivers/pci/pci-sh7780.c

   1 /*
   2  *      Low-Level PCI Support for the SH7780
   3  *
   4  *  Dustin McIntire (dustin@sensoria.com)
   5  *      Derived from arch/i386/kernel/pci-*.c which bore the message:
   6  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   7  *
   8  *  Ported to the new API by Paul Mundt <lethal@linux-sh.org>
   9  *  With cleanup by Paul van Gool <pvangool@mimotech.com>
  10  *
  11  *  May be copied or modified under the terms of the GNU General Public
  12  *  License.  See linux/COPYING for more information.
  13  *
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include "pci-sh4.h"
  24
  25 #define INTC_BASE       0xffd00000
  26 #define INTC_ICR0       (INTC_BASE+0x0)
  27 #define INTC_ICR1       (INTC_BASE+0x1c)
  28 #define INTC_INTPRI     (INTC_BASE+0x10)
  29 #define INTC_INTREQ     (INTC_BASE+0x24)
  30 #define INTC_INTMSK0    (INTC_BASE+0x44)
  31 #define INTC_INTMSK1    (INTC_BASE+0x48)
  32 #define INTC_INTMSK2    (INTC_BASE+0x40080)
  33 #define INTC_INTMSKCLR0 (INTC_BASE+0x64)
  34 #define INTC_INTMSKCLR1 (INTC_BASE+0x68)
  35 #define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
  36 #define INTC_INT2MSKR   (INTC_BASE+0x40038)
  37 #define INTC_INT2MSKCR  (INTC_BASE+0x4003c)
  38
  39 /*
  40  * Initialization. Try all known PCI access methods. Note that we support
  41  * using both PCI BIOS and direct access: in such cases, we use I/O ports
  42  * to access config space.
  43  *
  44  * Note that the platform specific initialization (BSC registers, and memory
  45  * space mapping) will be called via the platform defined function
  46  * pcibios_init_platform().
  47  */
  48 static int __init sh7780_pci_init(void)
  49 {
  50         unsigned int id;
  51         int ret;
  52
  53         pr_debug("PCI: Starting intialization.\n");
  54
  55         outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
  56
  57         /* check for SH7780/SH7780R hardware */
  58         id = pci_read_reg(SH7780_PCIVID);
  59         if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
  60             (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
  61                 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
  62                 return -ENODEV;
  63         }
  64
  65         /* Setup the INTC */
  66         ctrl_outl(0x00200000, INTC_ICR0);       /* INTC SH-4 Mode */
  67         ctrl_outl(0x00078000, INTC_INT2MSKCR);  /* enable PCIINTA - PCIINTD */
  68         ctrl_outl(0x40000000, INTC_INTMSK1);    /* disable IRL4-7 Interrupt */
  69         ctrl_outl(0x0000fffe, INTC_INTMSK2);    /* disable IRL4-7 Interrupt */
  70         ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
  71         ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
  72
  73         if ((ret = sh4_pci_check_direct()) != 0)
  74                 return ret;
  75
  76         return pcibios_init_platform();
  77 }
  78 core_initcall(sh7780_pci_init);
  79
  80 int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
  81 {
  82         u32 word;
  83
  84         /*
  85          * This code is unused for some boards as it is done in the
  86          * bootloader and doing it here means the MAC addresses loaded
  87          * by the bootloader get lost.
  88          */
  89         if (!(map->flags & SH4_PCIC_NO_RESET)) {
  90                 /* toggle PCI reset pin */
  91                 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
  92                 pci_write_reg(word, SH4_PCICR);
  93                 /* Wait for a long time... not 1 sec. but long enough */
  94                 mdelay(100);
  95                 word = SH4_PCICR_PREFIX;
  96                 pci_write_reg(word, SH4_PCICR);
  97         }
  98
  99         /* set the command/status bits to:
 100          * Wait Cycle Control + Parity Enable + Bus Master +
 101          * Mem space enable
 102          */
 103         pci_write_reg(0x00000046, SH7780_PCICMD);
 104
 105         /* define this host as the host bridge */
 106         word = PCI_BASE_CLASS_BRIDGE << 24;
 107         pci_write_reg(word, SH7780_PCIRID);
 108
 109         /* Set IO and Mem windows to local address
 110          * Make PCI and local address the same for easy 1 to 1 mapping
 111          * Window0 = map->window0.size @ non-cached area base = SDRAM
 112          * Window1 = map->window1.size @ cached area base = SDRAM
 113          */
 114         word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
 115         pci_write_reg(0x07f00001, SH4_PCILSR0);
 116         word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
 117         pci_write_reg(0x00000001, SH4_PCILSR1);
 118         /* Set the values on window 0 PCI config registers */
 119         word = P2SEGADDR(map->window0.base);
 120         pci_write_reg(0xa8000000, SH4_PCILAR0);
 121         pci_write_reg(0x08000000, SH7780_PCIMBAR0);
 122         /* Set the values on window 1 PCI config registers */
 123         word = P2SEGADDR(map->window1.base);
 124         pci_write_reg(0x00000000, SH4_PCILAR1);
 125         pci_write_reg(0x00000000, SH7780_PCIMBAR1);
 126
 127         /* Map IO space into PCI IO window
 128          * The IO window is 64K-PCIBIOS_MIN_IO in size
 129          * IO addresses will be translated to the
 130          * PCI IO window base address
 131          */
 132         pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
 133                  PCIBIOS_MIN_IO, (64 << 10),
 134                  SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
 135
 136         /* NOTE: I'm ignoring the PCI error IRQs for now..
 137          * TODO: add support for the internal error interrupts and
 138          * DMA interrupts...
 139          */
 140
 141 #ifdef CONFIG_SH_R7780RP
 142         pci_fixup_pcic();
 143 #endif
 144
 145         /* SH7780 init done, set central function init complete */
 146         /* use round robin mode to stop a device starving/overruning */
 147         word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
 148         pci_write_reg(word, SH4_PCICR);
 149
 150         return 1;
 151 }