arch/sh/include/asm/pgtable.h

   1 /*
   2  * This file contains the functions and defines necessary to modify and
   3  * use the SuperH page table tree.
   4  *
   5  * Copyright (C) 1999 Niibe Yutaka
   6  * Copyright (C) 2002 - 2007 Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General
   9  * Public License.  See the file "COPYING" in the main directory of this
  10  * archive for more details.
  11  */
  12 #ifndef __ASM_SH_PGTABLE_H
  13 #define __ASM_SH_PGTABLE_H
  14
  15 #include <asm-generic/pgtable-nopmd.h>
  16 #include <asm/page.h>
  17
  18 #ifndef __ASSEMBLY__
  19 #include <asm/addrspace.h>
  20 #include <asm/fixmap.h>
  21
  22 /*
  23  * ZERO_PAGE is a global shared page that is always zero: used
  24  * for zero-mapped memory areas etc..
  25  */
  26 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
  27 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
  28
  29 #endif /* !__ASSEMBLY__ */
  30
  31 /*
  32  * Effective and physical address definitions, to aid with sign
  33  * extension.
  34  */
  35 #define NEFF            32
  36 #define NEFF_SIGN       (1LL << (NEFF - 1))
  37 #define NEFF_MASK       (-1LL << NEFF)
  38
  39 static inline unsigned long long neff_sign_extend(unsigned long val)
  40 {
  41         unsigned long long extended = val;
  42         return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
  43 }
  44
  45 #ifdef CONFIG_29BIT
  46 #define NPHYS           29
  47 #else
  48 #define NPHYS           32
  49 #endif
  50
  51 #define NPHYS_SIGN      (1LL << (NPHYS - 1))
  52 #define NPHYS_MASK      (-1LL << NPHYS)
  53
  54 /*
  55  * traditional two-level paging structure
  56  */
  57 /* PTE bits */
  58 #if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
  59 # define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
  60 #else
  61 # define PTE_MAGNITUDE  2       /* 32-bit PTEs */
  62 #endif
  63 #define PTE_SHIFT       PAGE_SHIFT
  64 #define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
  65
  66 /* PGD bits */
  67 #define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
  68 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  69 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  70
  71 /* Entries per level */
  72 #define PTRS_PER_PTE    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
  73 #define PTRS_PER_PGD    (PAGE_SIZE / sizeof(pgd_t))
  74
  75 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  76 #define FIRST_USER_ADDRESS      0
  77
  78 #define PHYS_ADDR_MASK29                0x1fffffff
  79 #define PHYS_ADDR_MASK32                0xffffffff
  80
  81 #ifdef CONFIG_PMB
  82 static inline unsigned long phys_addr_mask(void)
  83 {
  84         /* Is the MMU in 29bit mode? */
  85         if (__in_29bit_mode())
  86                 return PHYS_ADDR_MASK29;
  87
  88         return PHYS_ADDR_MASK32;
  89 }
  90 #elif defined(CONFIG_32BIT)
  91 static inline unsigned long phys_addr_mask(void)
  92 {
  93         return PHYS_ADDR_MASK32;
  94 }
  95 #else
  96 static inline unsigned long phys_addr_mask(void)
  97 {
  98         return PHYS_ADDR_MASK29;
  99 }
 100 #endif
 101
 102 #define PTE_PHYS_MASK           (phys_addr_mask() & PAGE_MASK)
 103 #define PTE_FLAGS_MASK          (~(PTE_PHYS_MASK) << PAGE_SHIFT)
 104
 105 #ifdef CONFIG_SUPERH32
 106 #define VMALLOC_START   (P3SEG)
 107 #else
 108 #define VMALLOC_START   (0xf0000000)
 109 #endif
 110 #define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
 111
 112 #if defined(CONFIG_SUPERH32)
 113 #include <asm/pgtable_32.h>
 114 #else
 115 #include <asm/pgtable_64.h>
 116 #endif
 117
 118 /*
 119  * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
 120  * protection for execute, and considers it the same as a read. Also, write
 121  * permission implies read permission. This is the closest we can get..
 122  *
 123  * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
 124  * not only supporting separate execute, read, and write bits, but having
 125  * completely separate permission bits for user and kernel space.
 126  */
 127          /*xwr*/
 128 #define __P000  PAGE_NONE
 129 #define __P001  PAGE_READONLY
 130 #define __P010  PAGE_COPY
 131 #define __P011  PAGE_COPY
 132 #define __P100  PAGE_EXECREAD
 133 #define __P101  PAGE_EXECREAD
 134 #define __P110  PAGE_COPY
 135 #define __P111  PAGE_COPY
 136
 137 #define __S000  PAGE_NONE
 138 #define __S001  PAGE_READONLY
 139 #define __S010  PAGE_WRITEONLY
 140 #define __S011  PAGE_SHARED
 141 #define __S100  PAGE_EXECREAD
 142 #define __S101  PAGE_EXECREAD
 143 #define __S110  PAGE_RWX
 144 #define __S111  PAGE_RWX
 145
 146 typedef pte_t *pte_addr_t;
 147
 148 #define kern_addr_valid(addr)   (1)
 149
 150 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 151                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 152
 153 #define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
 154
 155 /*
 156  * No page table caches to initialise
 157  */
 158 #define pgtable_cache_init()    do { } while (0)
 159
 160 struct vm_area_struct;
 161
 162 extern void __update_cache(struct vm_area_struct *vma,
 163                            unsigned long address, pte_t pte);
 164 extern void __update_tlb(struct vm_area_struct *vma,
 165                          unsigned long address, pte_t pte);
 166
 167 static inline void
 168 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 169 {
 170         __update_cache(vma, address, pte);
 171         __update_tlb(vma, address, pte);
 172 }
 173
 174 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 175 extern void paging_init(void);
 176 extern void page_table_range_init(unsigned long start, unsigned long end,
 177                                   pgd_t *pgd);
 178
 179 /* arch/sh/mm/mmap.c */
 180 #define HAVE_ARCH_UNMAPPED_AREA
 181 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 182
 183 #include <asm-generic/pgtable.h>
 184
 185 #endif /* __ASM_SH_PGTABLE_H */