arch/sh/kernel/cpu/clock.c

   1 /*
   2  * arch/sh/kernel/cpu/clock.c - SuperH clock framework
   3  *
   4  *  Copyright (C) 2005, 2006  Paul Mundt
   5  *
   6  * This clock framework is derived from the OMAP version by:
   7  *
   8  *      Copyright (C) 2004 Nokia Corporation
   9  *      Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <linux/list.h>
  20 #include <linux/kref.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/err.h>
  23 #include <asm/clock.h>
  24 #include <asm/timer.h>
  25
  26 static LIST_HEAD(clock_list);
  27 static DEFINE_SPINLOCK(clock_lock);
  28 static DEFINE_MUTEX(clock_list_sem);
  29
  30 /*
  31  * Each subtype is expected to define the init routines for these clocks,
  32  * as each subtype (or processor family) will have these clocks at the
  33  * very least. These are all provided through the CPG, which even some of
  34  * the more quirky parts (such as ST40, SH4-202, etc.) still have.
  35  *
  36  * The processor-specific code is expected to register any additional
  37  * clock sources that are of interest.
  38  */
  39 static struct clk master_clk = {
  40         .name           = "master_clk",
  41         .flags          = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
  42         .rate           = CONFIG_SH_PCLK_FREQ,
  43 };
  44
  45 static struct clk module_clk = {
  46         .name           = "module_clk",
  47         .parent         = &master_clk,
  48         .flags          = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
  49 };
  50
  51 static struct clk bus_clk = {
  52         .name           = "bus_clk",
  53         .parent         = &master_clk,
  54         .flags          = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
  55 };
  56
  57 static struct clk cpu_clk = {
  58         .name           = "cpu_clk",
  59         .parent         = &master_clk,
  60         .flags          = CLK_ALWAYS_ENABLED,
  61 };
  62
  63 /*
  64  * The ordering of these clocks matters, do not change it.
  65  */
  66 static struct clk *onchip_clocks[] = {
  67         &master_clk,
  68         &module_clk,
  69         &bus_clk,
  70         &cpu_clk,
  71 };
  72
  73 static void propagate_rate(struct clk *clk)
  74 {
  75         struct clk *clkp;
  76
  77         list_for_each_entry(clkp, &clock_list, node) {
  78                 if (likely(clkp->parent != clk))
  79                         continue;
  80                 if (likely(clkp->ops && clkp->ops->recalc))
  81                         clkp->ops->recalc(clkp);
  82         }
  83 }
  84
  85 int __clk_enable(struct clk *clk)
  86 {
  87         /*
  88          * See if this is the first time we're enabling the clock, some
  89          * clocks that are always enabled still require "special"
  90          * initialization. This is especially true if the clock mode
  91          * changes and the clock needs to hunt for the proper set of
  92          * divisors to use before it can effectively recalc.
  93          */
  94         if (unlikely(atomic_read(&clk->kref.refcount) == 1))
  95                 if (clk->ops && clk->ops->init)
  96                         clk->ops->init(clk);
  97
  98         if (clk->flags & CLK_ALWAYS_ENABLED)
  99                 return 0;
 100
 101         if (likely(clk->ops && clk->ops->enable))
 102                 clk->ops->enable(clk);
 103
 104         kref_get(&clk->kref);
 105         return 0;
 106 }
 107
 108 int clk_enable(struct clk *clk)
 109 {
 110         unsigned long flags;
 111         int ret;
 112
 113         spin_lock_irqsave(&clock_lock, flags);
 114         ret = __clk_enable(clk);
 115         spin_unlock_irqrestore(&clock_lock, flags);
 116
 117         return ret;
 118 }
 119
 120 static void clk_kref_release(struct kref *kref)
 121 {
 122         /* Nothing to do */
 123 }
 124
 125 void __clk_disable(struct clk *clk)
 126 {
 127         if (clk->flags & CLK_ALWAYS_ENABLED)
 128                 return;
 129
 130         kref_put(&clk->kref, clk_kref_release);
 131 }
 132
 133 void clk_disable(struct clk *clk)
 134 {
 135         unsigned long flags;
 136
 137         spin_lock_irqsave(&clock_lock, flags);
 138         __clk_disable(clk);
 139         spin_unlock_irqrestore(&clock_lock, flags);
 140 }
 141
 142 int clk_register(struct clk *clk)
 143 {
 144         mutex_lock(&clock_list_sem);
 145
 146         list_add(&clk->node, &clock_list);
 147         kref_init(&clk->kref);
 148
 149         mutex_unlock(&clock_list_sem);
 150
 151         return 0;
 152 }
 153
 154 void clk_unregister(struct clk *clk)
 155 {
 156         mutex_lock(&clock_list_sem);
 157         list_del(&clk->node);
 158         mutex_unlock(&clock_list_sem);
 159 }
 160
 161 inline unsigned long clk_get_rate(struct clk *clk)
 162 {
 163         return clk->rate;
 164 }
 165
 166 int clk_set_rate(struct clk *clk, unsigned long rate)
 167 {
 168         int ret = -EOPNOTSUPP;
 169
 170         if (likely(clk->ops && clk->ops->set_rate)) {
 171                 unsigned long flags;
 172
 173                 spin_lock_irqsave(&clock_lock, flags);
 174                 ret = clk->ops->set_rate(clk, rate);
 175                 spin_unlock_irqrestore(&clock_lock, flags);
 176         }
 177
 178         if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
 179                 propagate_rate(clk);
 180
 181         return ret;
 182 }
 183
 184 void clk_recalc_rate(struct clk *clk)
 185 {
 186         if (likely(clk->ops && clk->ops->recalc)) {
 187                 unsigned long flags;
 188
 189                 spin_lock_irqsave(&clock_lock, flags);
 190                 clk->ops->recalc(clk);
 191                 spin_unlock_irqrestore(&clock_lock, flags);
 192         }
 193
 194         if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
 195                 propagate_rate(clk);
 196 }
 197
 198 struct clk *clk_get(const char *id)
 199 {
 200         struct clk *p, *clk = ERR_PTR(-ENOENT);
 201
 202         mutex_lock(&clock_list_sem);
 203         list_for_each_entry(p, &clock_list, node) {
 204                 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
 205                         clk = p;
 206                         break;
 207                 }
 208         }
 209         mutex_unlock(&clock_list_sem);
 210
 211         return clk;
 212 }
 213
 214 void clk_put(struct clk *clk)
 215 {
 216         if (clk && !IS_ERR(clk))
 217                 module_put(clk->owner);
 218 }
 219
 220 void __init __attribute__ ((weak))
 221 arch_init_clk_ops(struct clk_ops **ops, int type)
 222 {
 223 }
 224
 225 int __init clk_init(void)
 226 {
 227         int i, ret = 0;
 228
 229         BUG_ON(!master_clk.rate);
 230
 231         for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
 232                 struct clk *clk = onchip_clocks[i];
 233
 234                 arch_init_clk_ops(&clk->ops, i);
 235                 ret |= clk_register(clk);
 236                 clk_enable(clk);
 237         }
 238
 239         /* Kick the child clocks.. */
 240         propagate_rate(&master_clk);
 241         propagate_rate(&bus_clk);
 242
 243         return ret;
 244 }
 245
 246 int show_clocks(struct seq_file *m)
 247 {
 248         struct clk *clk;
 249
 250         list_for_each_entry_reverse(clk, &clock_list, node) {
 251                 unsigned long rate = clk_get_rate(clk);
 252
 253                 /*
 254                  * Don't bother listing dummy clocks with no ancestry
 255                  * that only support enable and disable ops.
 256                  */
 257                 if (unlikely(!rate && !clk->parent))
 258                         continue;
 259
 260                 seq_printf(m, "%-12s\t: %ld.%02ldMHz\n", clk->name,
 261                            rate / 1000000, (rate % 1000000) / 10000);
 262         }
 263
 264         return 0;
 265 }
 266
 267 EXPORT_SYMBOL_GPL(clk_register);
 268 EXPORT_SYMBOL_GPL(clk_unregister);
 269 EXPORT_SYMBOL_GPL(clk_get);
 270 EXPORT_SYMBOL_GPL(clk_put);
 271 EXPORT_SYMBOL_GPL(clk_enable);
 272 EXPORT_SYMBOL_GPL(clk_disable);
 273 EXPORT_SYMBOL_GPL(__clk_enable);
 274 EXPORT_SYMBOL_GPL(__clk_disable);
 275 EXPORT_SYMBOL_GPL(clk_get_rate);
 276 EXPORT_SYMBOL_GPL(clk_set_rate);
 277 EXPORT_SYMBOL_GPL(clk_recalc_rate);