arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7750/SH7751 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/serial_sci.h>
  17 #include <asm/machtypes.h>
  18
  19 static struct resource rtc_resources[] = {
  20         [0] = {
  21                 .start  = 0xffc80000,
  22                 .end    = 0xffc80000 + 0x58 - 1,
  23                 .flags  = IORESOURCE_IO,
  24         },
  25         [1] = {
  26                 /* Shared Period/Carry/Alarm IRQ */
  27                 .start  = 20,
  28                 .flags  = IORESOURCE_IRQ,
  29         },
  30 };
  31
  32 static struct platform_device rtc_device = {
  33         .name           = "sh-rtc",
  34         .id             = -1,
  35         .num_resources  = ARRAY_SIZE(rtc_resources),
  36         .resource       = rtc_resources,
  37 };
  38
  39 static struct plat_sci_port sci_platform_data = {
  40         .mapbase        = 0xffe00000,
  41         .flags          = UPF_BOOT_AUTOCONF,
  42         .scscr          = SCSCR_TE | SCSCR_RE,
  43         .scbrr_algo_id  = SCBRR_ALGO_2,
  44         .type           = PORT_SCI,
  45         .irqs           = { 23, 23, 23, 0 },
  46 };
  47
  48 static struct platform_device sci_device = {
  49         .name           = "sh-sci",
  50         .id             = 0,
  51         .dev            = {
  52                 .platform_data  = &sci_platform_data,
  53         },
  54 };
  55
  56 static struct plat_sci_port scif_platform_data = {
  57         .mapbase        = 0xffe80000,
  58         .flags          = UPF_BOOT_AUTOCONF,
  59         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
  60         .scbrr_algo_id  = SCBRR_ALGO_2,
  61         .type           = PORT_SCIF,
  62         .irqs           = { 40, 40, 40, 40 },
  63 };
  64
  65 static struct platform_device scif_device = {
  66         .name           = "sh-sci",
  67         .id             = 1,
  68         .dev            = {
  69                 .platform_data  = &scif_platform_data,
  70         },
  71 };
  72
  73 static struct sh_timer_config tmu0_platform_data = {
  74         .channel_offset = 0x04,
  75         .timer_bit = 0,
  76         .clockevent_rating = 200,
  77 };
  78
  79 static struct resource tmu0_resources[] = {
  80         [0] = {
  81                 .start  = 0xffd80008,
  82                 .end    = 0xffd80013,
  83                 .flags  = IORESOURCE_MEM,
  84         },
  85         [1] = {
  86                 .start  = 16,
  87                 .flags  = IORESOURCE_IRQ,
  88         },
  89 };
  90
  91 static struct platform_device tmu0_device = {
  92         .name           = "sh_tmu",
  93         .id             = 0,
  94         .dev = {
  95                 .platform_data  = &tmu0_platform_data,
  96         },
  97         .resource       = tmu0_resources,
  98         .num_resources  = ARRAY_SIZE(tmu0_resources),
  99 };
 100
 101 static struct sh_timer_config tmu1_platform_data = {
 102         .channel_offset = 0x10,
 103         .timer_bit = 1,
 104         .clocksource_rating = 200,
 105 };
 106
 107 static struct resource tmu1_resources[] = {
 108         [0] = {
 109                 .start  = 0xffd80014,
 110                 .end    = 0xffd8001f,
 111                 .flags  = IORESOURCE_MEM,
 112         },
 113         [1] = {
 114                 .start  = 17,
 115                 .flags  = IORESOURCE_IRQ,
 116         },
 117 };
 118
 119 static struct platform_device tmu1_device = {
 120         .name           = "sh_tmu",
 121         .id             = 1,
 122         .dev = {
 123                 .platform_data  = &tmu1_platform_data,
 124         },
 125         .resource       = tmu1_resources,
 126         .num_resources  = ARRAY_SIZE(tmu1_resources),
 127 };
 128
 129 static struct sh_timer_config tmu2_platform_data = {
 130         .channel_offset = 0x1c,
 131         .timer_bit = 2,
 132 };
 133
 134 static struct resource tmu2_resources[] = {
 135         [0] = {
 136                 .start  = 0xffd80020,
 137                 .end    = 0xffd8002f,
 138                 .flags  = IORESOURCE_MEM,
 139         },
 140         [1] = {
 141                 .start  = 18,
 142                 .flags  = IORESOURCE_IRQ,
 143         },
 144 };
 145
 146 static struct platform_device tmu2_device = {
 147         .name           = "sh_tmu",
 148         .id             = 2,
 149         .dev = {
 150                 .platform_data  = &tmu2_platform_data,
 151         },
 152         .resource       = tmu2_resources,
 153         .num_resources  = ARRAY_SIZE(tmu2_resources),
 154 };
 155
 156 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 157 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 158         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 159         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 160
 161 static struct sh_timer_config tmu3_platform_data = {
 162         .channel_offset = 0x04,
 163         .timer_bit = 0,
 164 };
 165
 166 static struct resource tmu3_resources[] = {
 167         [0] = {
 168                 .start  = 0xfe100008,
 169                 .end    = 0xfe100013,
 170                 .flags  = IORESOURCE_MEM,
 171         },
 172         [1] = {
 173                 .start  = 72,
 174                 .flags  = IORESOURCE_IRQ,
 175         },
 176 };
 177
 178 static struct platform_device tmu3_device = {
 179         .name           = "sh_tmu",
 180         .id             = 3,
 181         .dev = {
 182                 .platform_data  = &tmu3_platform_data,
 183         },
 184         .resource       = tmu3_resources,
 185         .num_resources  = ARRAY_SIZE(tmu3_resources),
 186 };
 187
 188 static struct sh_timer_config tmu4_platform_data = {
 189         .channel_offset = 0x10,
 190         .timer_bit = 1,
 191 };
 192
 193 static struct resource tmu4_resources[] = {
 194         [0] = {
 195                 .start  = 0xfe100014,
 196                 .end    = 0xfe10001f,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         [1] = {
 200                 .start  = 76,
 201                 .flags  = IORESOURCE_IRQ,
 202         },
 203 };
 204
 205 static struct platform_device tmu4_device = {
 206         .name           = "sh_tmu",
 207         .id             = 4,
 208         .dev = {
 209                 .platform_data  = &tmu4_platform_data,
 210         },
 211         .resource       = tmu4_resources,
 212         .num_resources  = ARRAY_SIZE(tmu4_resources),
 213 };
 214
 215 #endif
 216
 217 static struct platform_device *sh7750_devices[] __initdata = {
 218         &rtc_device,
 219         &tmu0_device,
 220         &tmu1_device,
 221         &tmu2_device,
 222 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 223         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 224         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 225         &tmu3_device,
 226         &tmu4_device,
 227 #endif
 228 };
 229
 230 static int __init sh7750_devices_setup(void)
 231 {
 232         if (mach_is_rts7751r2d()) {
 233                 platform_device_register(&scif_device);
 234         } else {
 235                 platform_device_register(&sci_device);
 236                 platform_device_register(&scif_device);
 237         }
 238
 239         return platform_add_devices(sh7750_devices,
 240                                     ARRAY_SIZE(sh7750_devices));
 241 }
 242 arch_initcall(sh7750_devices_setup);
 243
 244 static struct platform_device *sh7750_early_devices[] __initdata = {
 245         &tmu0_device,
 246         &tmu1_device,
 247         &tmu2_device,
 248 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 249         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 250         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 251         &tmu3_device,
 252         &tmu4_device,
 253 #endif
 254 };
 255
 256 void __init plat_early_device_setup(void)
 257 {
 258         if (mach_is_rts7751r2d()) {
 259                 scif_platform_data.scscr |= SCSCR_CKE1;
 260                 early_platform_add_devices(&scif_device, 1);
 261         } else {
 262                 early_platform_add_devices(&sci_device, 1);
 263                 early_platform_add_devices(&scif_device, 1);
 264         }
 265
 266         early_platform_add_devices(sh7750_early_devices,
 267                                    ARRAY_SIZE(sh7750_early_devices));
 268 }
 269
 270 enum {
 271         UNUSED = 0,
 272
 273         /* interrupt sources */
 274         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 275         HUDI, GPIOI, DMAC,
 276         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 277         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 278         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 279
 280         /* interrupt groups */
 281         PCIC1,
 282 };
 283
 284 static struct intc_vect vectors[] __initdata = {
 285         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 286         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 287         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 288         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 289         INTC_VECT(RTC, 0x4c0),
 290         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 291         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 292         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 293         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 294         INTC_VECT(WDT, 0x560),
 295         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 296 };
 297
 298 static struct intc_prio_reg prio_registers[] __initdata = {
 299         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 300         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 301         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 302         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 303         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 304                                                  TMU4, TMU3,
 305                                                  PCIC1, PCIC0_PCISERR } },
 306 };
 307
 308 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 309                          NULL, prio_registers, NULL);
 310
 311 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 312 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 313         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 314         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 315         defined(CONFIG_CPU_SUBTYPE_SH7091)
 316 static struct intc_vect vectors_dma4[] __initdata = {
 317         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 318         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 319         INTC_VECT(DMAC, 0x6c0),
 320 };
 321
 322 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 323                          vectors_dma4, NULL,
 324                          NULL, prio_registers, NULL);
 325 #endif
 326
 327 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 328 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 329 static struct intc_vect vectors_dma8[] __initdata = {
 330         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 331         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 332         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 333         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 334         INTC_VECT(DMAC, 0x6c0),
 335 };
 336
 337 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 338                          vectors_dma8, NULL,
 339                          NULL, prio_registers, NULL);
 340 #endif
 341
 342 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 343 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 344         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 345         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 346 static struct intc_vect vectors_tmu34[] __initdata = {
 347         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 348 };
 349
 350 static struct intc_mask_reg mask_registers[] __initdata = {
 351         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 352           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 353             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 354             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 355             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 356             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 357 };
 358
 359 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 360                          vectors_tmu34, NULL,
 361                          mask_registers, prio_registers, NULL);
 362 #endif
 363
 364 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 365 static struct intc_vect vectors_irlm[] __initdata = {
 366         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 367         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 368 };
 369
 370 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 371                          NULL, prio_registers, NULL);
 372
 373 /* SH7751 and SH7751R both have PCI */
 374 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 375 static struct intc_vect vectors_pci[] __initdata = {
 376         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 377         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 378         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 379         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 380 };
 381
 382 static struct intc_group groups_pci[] __initdata = {
 383         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 384                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 385 };
 386
 387 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 388                          mask_registers, prio_registers, NULL);
 389 #endif
 390
 391 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 392         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 393         defined(CONFIG_CPU_SUBTYPE_SH7091)
 394 void __init plat_irq_setup(void)
 395 {
 396         /*
 397          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 398          * see below..
 399          */
 400         register_intc_controller(&intc_desc);
 401         register_intc_controller(&intc_desc_dma4);
 402 }
 403 #endif
 404
 405 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 406 void __init plat_irq_setup(void)
 407 {
 408         register_intc_controller(&intc_desc);
 409         register_intc_controller(&intc_desc_dma8);
 410         register_intc_controller(&intc_desc_tmu34);
 411 }
 412 #endif
 413
 414 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 415 void __init plat_irq_setup(void)
 416 {
 417         register_intc_controller(&intc_desc);
 418         register_intc_controller(&intc_desc_dma4);
 419         register_intc_controller(&intc_desc_tmu34);
 420         register_intc_controller(&intc_desc_pci);
 421 }
 422 #endif
 423
 424 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 425 void __init plat_irq_setup(void)
 426 {
 427         register_intc_controller(&intc_desc);
 428         register_intc_controller(&intc_desc_dma8);
 429         register_intc_controller(&intc_desc_tmu34);
 430         register_intc_controller(&intc_desc_pci);
 431 }
 432 #endif
 433
 434 #define INTC_ICR        0xffd00000UL
 435 #define INTC_ICR_IRLM   (1<<7)
 436
 437 void __init plat_irq_setup_pins(int mode)
 438 {
 439 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 440         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 441         return;
 442 #endif
 443
 444         switch (mode) {
 445         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 446                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 447                 register_intc_controller(&intc_desc_irlm);
 448                 break;
 449         default:
 450                 BUG();
 451         }
 452 }