arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7750/SH7751 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/serial_sci.h>
  17 #include <generated/machtypes.h>
  18
  19 static struct resource rtc_resources[] = {
  20         [0] = {
  21                 .start  = 0xffc80000,
  22                 .end    = 0xffc80000 + 0x58 - 1,
  23                 .flags  = IORESOURCE_IO,
  24         },
  25         [1] = {
  26                 /* Shared Period/Carry/Alarm IRQ */
  27                 .start  = 20,
  28                 .flags  = IORESOURCE_IRQ,
  29         },
  30 };
  31
  32 static struct platform_device rtc_device = {
  33         .name           = "sh-rtc",
  34         .id             = -1,
  35         .num_resources  = ARRAY_SIZE(rtc_resources),
  36         .resource       = rtc_resources,
  37 };
  38
  39 static struct plat_sci_port sci_platform_data = {
  40         .mapbase        = 0xffe00000,
  41         .port_reg       = 0xffe0001C
  42         .flags          = UPF_BOOT_AUTOCONF,
  43         .scscr          = SCSCR_TE | SCSCR_RE,
  44         .scbrr_algo_id  = SCBRR_ALGO_2,
  45         .type           = PORT_SCI,
  46         .irqs           = { 23, 23, 23, 0 },
  47 };
  48
  49 static struct platform_device sci_device = {
  50         .name           = "sh-sci",
  51         .id             = 0,
  52         .dev            = {
  53                 .platform_data  = &sci_platform_data,
  54         },
  55 };
  56
  57 static struct plat_sci_port scif_platform_data = {
  58         .mapbase        = 0xffe80000,
  59         .flags          = UPF_BOOT_AUTOCONF,
  60         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
  61         .scbrr_algo_id  = SCBRR_ALGO_2,
  62         .type           = PORT_SCIF,
  63         .irqs           = { 40, 40, 40, 40 },
  64 };
  65
  66 static struct platform_device scif_device = {
  67         .name           = "sh-sci",
  68         .id             = 1,
  69         .dev            = {
  70                 .platform_data  = &scif_platform_data,
  71         },
  72 };
  73
  74 static struct sh_timer_config tmu0_platform_data = {
  75         .channel_offset = 0x04,
  76         .timer_bit = 0,
  77         .clockevent_rating = 200,
  78 };
  79
  80 static struct resource tmu0_resources[] = {
  81         [0] = {
  82                 .start  = 0xffd80008,
  83                 .end    = 0xffd80013,
  84                 .flags  = IORESOURCE_MEM,
  85         },
  86         [1] = {
  87                 .start  = 16,
  88                 .flags  = IORESOURCE_IRQ,
  89         },
  90 };
  91
  92 static struct platform_device tmu0_device = {
  93         .name           = "sh_tmu",
  94         .id             = 0,
  95         .dev = {
  96                 .platform_data  = &tmu0_platform_data,
  97         },
  98         .resource       = tmu0_resources,
  99         .num_resources  = ARRAY_SIZE(tmu0_resources),
 100 };
 101
 102 static struct sh_timer_config tmu1_platform_data = {
 103         .channel_offset = 0x10,
 104         .timer_bit = 1,
 105         .clocksource_rating = 200,
 106 };
 107
 108 static struct resource tmu1_resources[] = {
 109         [0] = {
 110                 .start  = 0xffd80014,
 111                 .end    = 0xffd8001f,
 112                 .flags  = IORESOURCE_MEM,
 113         },
 114         [1] = {
 115                 .start  = 17,
 116                 .flags  = IORESOURCE_IRQ,
 117         },
 118 };
 119
 120 static struct platform_device tmu1_device = {
 121         .name           = "sh_tmu",
 122         .id             = 1,
 123         .dev = {
 124                 .platform_data  = &tmu1_platform_data,
 125         },
 126         .resource       = tmu1_resources,
 127         .num_resources  = ARRAY_SIZE(tmu1_resources),
 128 };
 129
 130 static struct sh_timer_config tmu2_platform_data = {
 131         .channel_offset = 0x1c,
 132         .timer_bit = 2,
 133 };
 134
 135 static struct resource tmu2_resources[] = {
 136         [0] = {
 137                 .start  = 0xffd80020,
 138                 .end    = 0xffd8002f,
 139                 .flags  = IORESOURCE_MEM,
 140         },
 141         [1] = {
 142                 .start  = 18,
 143                 .flags  = IORESOURCE_IRQ,
 144         },
 145 };
 146
 147 static struct platform_device tmu2_device = {
 148         .name           = "sh_tmu",
 149         .id             = 2,
 150         .dev = {
 151                 .platform_data  = &tmu2_platform_data,
 152         },
 153         .resource       = tmu2_resources,
 154         .num_resources  = ARRAY_SIZE(tmu2_resources),
 155 };
 156
 157 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 158 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 159         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 160         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 161
 162 static struct sh_timer_config tmu3_platform_data = {
 163         .channel_offset = 0x04,
 164         .timer_bit = 0,
 165 };
 166
 167 static struct resource tmu3_resources[] = {
 168         [0] = {
 169                 .start  = 0xfe100008,
 170                 .end    = 0xfe100013,
 171                 .flags  = IORESOURCE_MEM,
 172         },
 173         [1] = {
 174                 .start  = 72,
 175                 .flags  = IORESOURCE_IRQ,
 176         },
 177 };
 178
 179 static struct platform_device tmu3_device = {
 180         .name           = "sh_tmu",
 181         .id             = 3,
 182         .dev = {
 183                 .platform_data  = &tmu3_platform_data,
 184         },
 185         .resource       = tmu3_resources,
 186         .num_resources  = ARRAY_SIZE(tmu3_resources),
 187 };
 188
 189 static struct sh_timer_config tmu4_platform_data = {
 190         .channel_offset = 0x10,
 191         .timer_bit = 1,
 192 };
 193
 194 static struct resource tmu4_resources[] = {
 195         [0] = {
 196                 .start  = 0xfe100014,
 197                 .end    = 0xfe10001f,
 198                 .flags  = IORESOURCE_MEM,
 199         },
 200         [1] = {
 201                 .start  = 76,
 202                 .flags  = IORESOURCE_IRQ,
 203         },
 204 };
 205
 206 static struct platform_device tmu4_device = {
 207         .name           = "sh_tmu",
 208         .id             = 4,
 209         .dev = {
 210                 .platform_data  = &tmu4_platform_data,
 211         },
 212         .resource       = tmu4_resources,
 213         .num_resources  = ARRAY_SIZE(tmu4_resources),
 214 };
 215
 216 #endif
 217
 218 static struct platform_device *sh7750_devices[] __initdata = {
 219         &rtc_device,
 220         &tmu0_device,
 221         &tmu1_device,
 222         &tmu2_device,
 223 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 224         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 225         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 226         &tmu3_device,
 227         &tmu4_device,
 228 #endif
 229 };
 230
 231 static int __init sh7750_devices_setup(void)
 232 {
 233         if (mach_is_rts7751r2d()) {
 234                 platform_device_register(&scif_device);
 235         } else {
 236                 platform_device_register(&sci_device);
 237                 platform_device_register(&scif_device);
 238         }
 239
 240         return platform_add_devices(sh7750_devices,
 241                                     ARRAY_SIZE(sh7750_devices));
 242 }
 243 arch_initcall(sh7750_devices_setup);
 244
 245 static struct platform_device *sh7750_early_devices[] __initdata = {
 246         &tmu0_device,
 247         &tmu1_device,
 248         &tmu2_device,
 249 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 250         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 251         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 252         &tmu3_device,
 253         &tmu4_device,
 254 #endif
 255 };
 256
 257 void __init plat_early_device_setup(void)
 258 {
 259         struct platform_device *dev[1];
 260
 261         if (mach_is_rts7751r2d()) {
 262                 scif_platform_data.scscr |= SCSCR_CKE1;
 263                 dev[0] = &scif_device;
 264                 early_platform_add_devices(dev, 1);
 265         } else {
 266                 dev[0] = &sci_device;
 267                 early_platform_add_devices(dev, 1);
 268                 dev[0] = &scif_device;
 269                 early_platform_add_devices(dev, 1);
 270         }
 271
 272         early_platform_add_devices(sh7750_early_devices,
 273                                    ARRAY_SIZE(sh7750_early_devices));
 274 }
 275
 276 enum {
 277         UNUSED = 0,
 278
 279         /* interrupt sources */
 280         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 281         HUDI, GPIOI, DMAC,
 282         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 283         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 284         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 285
 286         /* interrupt groups */
 287         PCIC1,
 288 };
 289
 290 static struct intc_vect vectors[] __initdata = {
 291         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 292         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 293         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 294         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 295         INTC_VECT(RTC, 0x4c0),
 296         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 297         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 298         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 299         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 300         INTC_VECT(WDT, 0x560),
 301         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 302 };
 303
 304 static struct intc_prio_reg prio_registers[] __initdata = {
 305         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 306         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 307         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 308         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 309         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 310                                                  TMU4, TMU3,
 311                                                  PCIC1, PCIC0_PCISERR } },
 312 };
 313
 314 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 315                          NULL, prio_registers, NULL);
 316
 317 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 318 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 319         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 320         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 321         defined(CONFIG_CPU_SUBTYPE_SH7091)
 322 static struct intc_vect vectors_dma4[] __initdata = {
 323         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 324         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 325         INTC_VECT(DMAC, 0x6c0),
 326 };
 327
 328 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 329                          vectors_dma4, NULL,
 330                          NULL, prio_registers, NULL);
 331 #endif
 332
 333 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 334 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 335 static struct intc_vect vectors_dma8[] __initdata = {
 336         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 337         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 338         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 339         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 340         INTC_VECT(DMAC, 0x6c0),
 341 };
 342
 343 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 344                          vectors_dma8, NULL,
 345                          NULL, prio_registers, NULL);
 346 #endif
 347
 348 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 349 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 350         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 351         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 352 static struct intc_vect vectors_tmu34[] __initdata = {
 353         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 354 };
 355
 356 static struct intc_mask_reg mask_registers[] __initdata = {
 357         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 358           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 359             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 360             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 361             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 362             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 363 };
 364
 365 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 366                          vectors_tmu34, NULL,
 367                          mask_registers, prio_registers, NULL);
 368 #endif
 369
 370 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 371 static struct intc_vect vectors_irlm[] __initdata = {
 372         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 373         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 374 };
 375
 376 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 377                          NULL, prio_registers, NULL);
 378
 379 /* SH7751 and SH7751R both have PCI */
 380 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 381 static struct intc_vect vectors_pci[] __initdata = {
 382         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 383         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 384         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 385         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 386 };
 387
 388 static struct intc_group groups_pci[] __initdata = {
 389         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 390                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 391 };
 392
 393 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 394                          mask_registers, prio_registers, NULL);
 395 #endif
 396
 397 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 398         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 399         defined(CONFIG_CPU_SUBTYPE_SH7091)
 400 void __init plat_irq_setup(void)
 401 {
 402         /*
 403          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 404          * see below..
 405          */
 406         register_intc_controller(&intc_desc);
 407         register_intc_controller(&intc_desc_dma4);
 408 }
 409 #endif
 410
 411 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 412 void __init plat_irq_setup(void)
 413 {
 414         register_intc_controller(&intc_desc);
 415         register_intc_controller(&intc_desc_dma8);
 416         register_intc_controller(&intc_desc_tmu34);
 417 }
 418 #endif
 419
 420 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 421 void __init plat_irq_setup(void)
 422 {
 423         register_intc_controller(&intc_desc);
 424         register_intc_controller(&intc_desc_dma4);
 425         register_intc_controller(&intc_desc_tmu34);
 426         register_intc_controller(&intc_desc_pci);
 427 }
 428 #endif
 429
 430 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 431 void __init plat_irq_setup(void)
 432 {
 433         register_intc_controller(&intc_desc);
 434         register_intc_controller(&intc_desc_dma8);
 435         register_intc_controller(&intc_desc_tmu34);
 436         register_intc_controller(&intc_desc_pci);
 437 }
 438 #endif
 439
 440 #define INTC_ICR        0xffd00000UL
 441 #define INTC_ICR_IRLM   (1<<7)
 442
 443 void __init plat_irq_setup_pins(int mode)
 444 {
 445 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 446         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 447         return;
 448 #endif
 449
 450         switch (mode) {
 451         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 452                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 453                 register_intc_controller(&intc_desc_irlm);
 454                 break;
 455         default:
 456                 BUG();
 457         }
 458 }