arch/sh/kernel/cpu/sh4a/clock-sh7786.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
   3  *
   4  * SH7786 support for the clock framework
   5  *
   6  *  Copyright (C) 2010  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/clkdev.h>
  17 #include <asm/clock.h>
  18 #include <asm/freq.h>
  19
  20 /*
  21  * Default rate for the root input clock, reset this with clk_set_rate()
  22  * from the platform code.
  23  */
  24 static struct clk extal_clk = {
  25         .rate           = 33333333,
  26 };
  27
  28 static unsigned long pll_recalc(struct clk *clk)
  29 {
  30         int multiplier;
  31
  32         /*
  33          * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
  34          * while modes 3, 4, and 5 use an x32.
  35          */
  36         multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
  37
  38         return clk->parent->rate * multiplier;
  39 }
  40
  41 static struct sh_clk_ops pll_clk_ops = {
  42         .recalc         = pll_recalc,
  43 };
  44
  45 static struct clk pll_clk = {
  46         .ops            = &pll_clk_ops,
  47         .parent         = &extal_clk,
  48         .flags          = CLK_ENABLE_ON_INIT,
  49 };
  50
  51 static struct clk *clks[] = {
  52         &extal_clk,
  53         &pll_clk,
  54 };
  55
  56 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
  57                                24, 32, 36, 48 };
  58
  59 static struct clk_div_mult_table div4_div_mult_table = {
  60         .divisors = div2,
  61         .nr_divisors = ARRAY_SIZE(div2),
  62 };
  63
  64 static struct clk_div4_table div4_table = {
  65         .div_mult_table = &div4_div_mult_table,
  66 };
  67
  68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
  69
  70 #define DIV4(_bit, _mask, _flags) \
  71   SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
  72
  73 struct clk div4_clks[DIV4_NR] = {
  74         [DIV4_P] = DIV4(0, 0x0b40, 0),
  75         [DIV4_DU] = DIV4(4, 0x0010, 0),
  76         [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
  77         [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
  78         [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
  79         [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
  80 };
  81
  82 #define MSTPCR0         0xffc40030
  83 #define MSTPCR1         0xffc40034
  84
  85 enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
  86        MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
  87        MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
  88        MSTP005, MSTP004, MSTP002,
  89        MSTP112, MSTP110, MSTP109, MSTP108,
  90        MSTP105, MSTP104, MSTP103, MSTP102,
  91        MSTP_NR };
  92
  93 static struct clk mstp_clks[MSTP_NR] = {
  94         /* MSTPCR0 */
  95         [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
  96         [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
  97         [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
  98         [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
  99         [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
 100         [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
 101         [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
 102         [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
 103         [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
 104         [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
 105         [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
 106         [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
 107         [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
 108         [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
 109         [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
 110         [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
 111         [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
 112         [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
 113         [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
 114         [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
 115         [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
 116
 117         /* MSTPCR1 */
 118         [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
 119         [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
 120         [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
 121         [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
 122         [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
 123         [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
 124         [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
 125         [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
 126 };
 127
 128 static struct clk_lookup lookups[] = {
 129         /* main clocks */
 130         CLKDEV_CON_ID("extal", &extal_clk),
 131         CLKDEV_CON_ID("pll_clk", &pll_clk),
 132
 133         /* DIV4 clocks */
 134         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 135         CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
 136         CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
 137         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 138         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 139         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 140
 141         /* MSTP32 clocks */
 142         CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
 143         CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
 144         CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
 145         CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
 146         CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
 147         CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
 148
 149         CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
 150         CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
 151         CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
 152         CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
 153         CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
 154         CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
 155         CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
 156         CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
 157
 158         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]),
 159         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP008]),
 160         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP008]),
 161         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP009]),
 162         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP009]),
 163         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP009]),
 164         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP010]),
 165         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP010]),
 166         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP010]),
 167         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.9", &mstp_clks[MSTP011]),
 168         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.10", &mstp_clks[MSTP011]),
 169         CLKDEV_ICK_ID("tmu_fck", "sh_tmu.11", &mstp_clks[MSTP011]),
 170
 171         CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
 172         CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
 173         CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
 174         CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
 175         CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
 176         CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
 177         CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
 178         CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
 179         CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
 180         CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
 181         CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
 182 };
 183
 184 int __init arch_clk_init(void)
 185 {
 186         int i, ret = 0;
 187
 188         for (i = 0; i < ARRAY_SIZE(clks); i++)
 189                 ret |= clk_register(clks[i]);
 190         for (i = 0; i < ARRAY_SIZE(lookups); i++)
 191                 clkdev_add(&lookups[i]);
 192
 193         if (!ret)
 194                 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
 195                                            &div4_table);
 196         if (!ret)
 197                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 198
 199         return ret;
 200 }