arch/sh/kernel/cpu/sh4a/setup-sh7366.c

   1 /*
   2  * SH7366 Setup
   3  *
   4  *  Copyright (C) 2008 Renesas Solutions
   5  *
   6  * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/uio_driver.h>
  17 #include <asm/clock.h>
  18
  19 static struct resource iic_resources[] = {
  20         [0] = {
  21                 .name   = "IIC",
  22                 .start  = 0x04470000,
  23                 .end    = 0x04470017,
  24                 .flags  = IORESOURCE_MEM,
  25         },
  26         [1] = {
  27                 .start  = 96,
  28                 .end    = 99,
  29                 .flags  = IORESOURCE_IRQ,
  30        },
  31 };
  32
  33 static struct platform_device iic_device = {
  34         .name           = "i2c-sh_mobile",
  35         .num_resources  = ARRAY_SIZE(iic_resources),
  36         .resource       = iic_resources,
  37 };
  38
  39 static struct uio_info vpu_platform_data = {
  40         .name = "VPU5",
  41         .version = "0",
  42         .irq = 60,
  43 };
  44
  45 static struct resource vpu_resources[] = {
  46         [0] = {
  47                 .name   = "VPU",
  48                 .start  = 0xfe900000,
  49                 .end    = 0xfe902807,
  50                 .flags  = IORESOURCE_MEM,
  51         },
  52         [1] = {
  53                 /* place holder for contiguous memory */
  54         },
  55 };
  56
  57 static struct platform_device vpu_device = {
  58         .name           = "uio_pdrv_genirq",
  59         .id             = 0,
  60         .dev = {
  61                 .platform_data  = &vpu_platform_data,
  62         },
  63         .resource       = vpu_resources,
  64         .num_resources  = ARRAY_SIZE(vpu_resources),
  65 };
  66
  67 static struct uio_info veu0_platform_data = {
  68         .name = "VEU",
  69         .version = "0",
  70         .irq = 54,
  71 };
  72
  73 static struct resource veu0_resources[] = {
  74         [0] = {
  75                 .name   = "VEU(1)",
  76                 .start  = 0xfe920000,
  77                 .end    = 0xfe9200b7,
  78                 .flags  = IORESOURCE_MEM,
  79         },
  80         [1] = {
  81                 /* place holder for contiguous memory */
  82         },
  83 };
  84
  85 static struct platform_device veu0_device = {
  86         .name           = "uio_pdrv_genirq",
  87         .id             = 1,
  88         .dev = {
  89                 .platform_data  = &veu0_platform_data,
  90         },
  91         .resource       = veu0_resources,
  92         .num_resources  = ARRAY_SIZE(veu0_resources),
  93 };
  94
  95 static struct uio_info veu1_platform_data = {
  96         .name = "VEU",
  97         .version = "0",
  98         .irq = 27,
  99 };
 100
 101 static struct resource veu1_resources[] = {
 102         [0] = {
 103                 .name   = "VEU(2)",
 104                 .start  = 0xfe924000,
 105                 .end    = 0xfe9240b7,
 106                 .flags  = IORESOURCE_MEM,
 107         },
 108         [1] = {
 109                 /* place holder for contiguous memory */
 110         },
 111 };
 112
 113 static struct platform_device veu1_device = {
 114         .name           = "uio_pdrv_genirq",
 115         .id             = 2,
 116         .dev = {
 117                 .platform_data  = &veu1_platform_data,
 118         },
 119         .resource       = veu1_resources,
 120         .num_resources  = ARRAY_SIZE(veu1_resources),
 121 };
 122
 123 static struct plat_sci_port sci_platform_data[] = {
 124         {
 125                 .mapbase        = 0xffe00000,
 126                 .flags          = UPF_BOOT_AUTOCONF,
 127                 .type           = PORT_SCIF,
 128                 .irqs           = { 80, 80, 80, 80 },
 129         }, {
 130                 .flags = 0,
 131         }
 132 };
 133
 134 static struct platform_device sci_device = {
 135         .name           = "sh-sci",
 136         .id             = -1,
 137         .dev            = {
 138                 .platform_data  = sci_platform_data,
 139         },
 140 };
 141
 142 static struct platform_device *sh7366_devices[] __initdata = {
 143         &iic_device,
 144         &sci_device,
 145         &vpu_device,
 146         &veu0_device,
 147         &veu1_device,
 148 };
 149
 150 static int __init sh7366_devices_setup(void)
 151 {
 152         clk_always_enable("mstp031"); /* TLB */
 153         clk_always_enable("mstp030"); /* IC */
 154         clk_always_enable("mstp029"); /* OC */
 155         clk_always_enable("mstp028"); /* RSMEM */
 156         clk_always_enable("mstp026"); /* XYMEM */
 157         clk_always_enable("mstp023"); /* INTC3 */
 158         clk_always_enable("mstp022"); /* INTC */
 159         clk_always_enable("mstp020"); /* SuperHyway */
 160         clk_always_enable("mstp109"); /* I2C */
 161         clk_always_enable("mstp207"); /* VEU-2 */
 162         clk_always_enable("mstp202"); /* VEU-1 */
 163         clk_always_enable("mstp201"); /* VPU */
 164
 165         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 166         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 167         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 168
 169         return platform_add_devices(sh7366_devices,
 170                                     ARRAY_SIZE(sh7366_devices));
 171 }
 172 __initcall(sh7366_devices_setup);
 173
 174 enum {
 175         UNUSED=0,
 176
 177         /* interrupt sources */
 178         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 179         ICB,
 180         DMAC0, DMAC1, DMAC2, DMAC3,
 181         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 182         MFI, VPU, USB,
 183         MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
 184         DMAC4, DMAC5, DMAC_DADERR,
 185         SCIF, SCIFA1, SCIFA2,
 186         DENC, MSIOF,
 187         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 188         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 189         SDHI0, SDHI1, SDHI2, SDHI3,
 190         CMT, TSIF, SIU,
 191         TMU0, TMU1, TMU2,
 192         VEU2, LCDC,
 193
 194         /* interrupt groups */
 195
 196         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI,
 197 };
 198
 199 static struct intc_vect vectors[] __initdata = {
 200         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 201         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 202         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 203         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 204         INTC_VECT(ICB, 0x700),
 205         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 206         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 207         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 208         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 209         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
 210         INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
 211         INTC_VECT(MMC_MMC3I, 0xb40),
 212         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 213         INTC_VECT(DMAC_DADERR, 0xbc0),
 214         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
 215         INTC_VECT(SCIFA2, 0xc40),
 216         INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
 217         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 218         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 219         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 220         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 221         INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
 222         INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
 223         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 224         INTC_VECT(SIU, 0xf80),
 225         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 226         INTC_VECT(TMU2, 0x440),
 227         INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
 228 };
 229
 230 static struct intc_group groups[] __initdata = {
 231         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 232         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 233         INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
 234         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 235         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 236                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 237         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 238         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 239 };
 240
 241 static struct intc_mask_reg mask_registers[] __initdata = {
 242         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 243           { } },
 244         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 245           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 246         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 247           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 248         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 249           { 0, 0, 0, ICB } },
 250         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 251           { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
 252         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 253           { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
 254         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 255           { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
 256         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 257           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 258             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 259         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 260           { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
 261         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 262           { 0, 0, 0, CMT, 0, USB, } },
 263         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 264           { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
 265         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 266           { 0, 0, 0, 0, 0, 0, 0, TSIF } },
 267         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 268           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 269 };
 270
 271 static struct intc_prio_reg prio_registers[] __initdata = {
 272         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 273         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
 274         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 275         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 276         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 277         { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
 278         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
 279         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
 280         { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
 281         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 282         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 283         { 0xa408002c, 0, 16, 4, /* IPRL */ { } },
 284         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 285           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 286 };
 287
 288 static struct intc_sense_reg sense_registers[] __initdata = {
 289         { 0xa414001c, 16, 2, /* ICR1 */
 290           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 291 };
 292
 293 static struct intc_mask_reg ack_registers[] __initdata = {
 294         { 0xa4140024, 0, 8, /* INTREQ00 */
 295           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 296 };
 297
 298 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups,
 299                              mask_registers, prio_registers, sense_registers,
 300                              ack_registers);
 301
 302 void __init plat_irq_setup(void)
 303 {
 304         register_intc_controller(&intc_desc);
 305 }
 306
 307 void __init plat_mem_setup(void)
 308 {
 309         /* TODO: Register Node 1 */
 310 }