arch/sh/kernel/cpu/sh4a/setup-sh7366.c

   1 /*
   2  * SH7366 Setup
   3  *
   4  *  Copyright (C) 2008 Renesas Solutions
   5  *
   6  * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/uio_driver.h>
  17 #include <linux/sh_timer.h>
  18 #include <linux/usb/r8a66597.h>
  19 #include <asm/clock.h>
  20
  21 static struct plat_sci_port scif0_platform_data = {
  22         .mapbase        = 0xffe00000,
  23         .flags          = UPF_BOOT_AUTOCONF,
  24         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  25         .scbrr_algo_id  = SCBRR_ALGO_2,
  26         .type           = PORT_SCIF,
  27         .irqs           = { 80, 80, 80, 80 },
  28 };
  29
  30 static struct platform_device scif0_device = {
  31         .name           = "sh-sci",
  32         .id             = 0,
  33         .dev            = {
  34                 .platform_data  = &scif0_platform_data,
  35         },
  36 };
  37
  38 static struct resource iic_resources[] = {
  39         [0] = {
  40                 .name   = "IIC",
  41                 .start  = 0x04470000,
  42                 .end    = 0x04470017,
  43                 .flags  = IORESOURCE_MEM,
  44         },
  45         [1] = {
  46                 .start  = 96,
  47                 .end    = 99,
  48                 .flags  = IORESOURCE_IRQ,
  49        },
  50 };
  51
  52 static struct platform_device iic_device = {
  53         .name           = "i2c-sh_mobile",
  54         .id             = 0, /* "i2c0" clock */
  55         .num_resources  = ARRAY_SIZE(iic_resources),
  56         .resource       = iic_resources,
  57 };
  58
  59 static struct r8a66597_platdata r8a66597_data = {
  60         .on_chip = 1,
  61 };
  62
  63 static struct resource usb_host_resources[] = {
  64         [0] = {
  65                 .start  = 0xa4d80000,
  66                 .end    = 0xa4d800ff,
  67                 .flags  = IORESOURCE_MEM,
  68         },
  69         [1] = {
  70                 .start  = 65,
  71                 .end    = 65,
  72                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  73         },
  74 };
  75
  76 static struct platform_device usb_host_device = {
  77         .name   = "r8a66597_hcd",
  78         .id     = -1,
  79         .dev = {
  80                 .dma_mask               = NULL,
  81                 .coherent_dma_mask      = 0xffffffff,
  82                 .platform_data          = &r8a66597_data,
  83         },
  84         .num_resources  = ARRAY_SIZE(usb_host_resources),
  85         .resource       = usb_host_resources,
  86 };
  87
  88 static struct uio_info vpu_platform_data = {
  89         .name = "VPU5",
  90         .version = "0",
  91         .irq = 60,
  92 };
  93
  94 static struct resource vpu_resources[] = {
  95         [0] = {
  96                 .name   = "VPU",
  97                 .start  = 0xfe900000,
  98                 .end    = 0xfe902807,
  99                 .flags  = IORESOURCE_MEM,
 100         },
 101         [1] = {
 102                 /* place holder for contiguous memory */
 103         },
 104 };
 105
 106 static struct platform_device vpu_device = {
 107         .name           = "uio_pdrv_genirq",
 108         .id             = 0,
 109         .dev = {
 110                 .platform_data  = &vpu_platform_data,
 111         },
 112         .resource       = vpu_resources,
 113         .num_resources  = ARRAY_SIZE(vpu_resources),
 114 };
 115
 116 static struct uio_info veu0_platform_data = {
 117         .name = "VEU",
 118         .version = "0",
 119         .irq = 54,
 120 };
 121
 122 static struct resource veu0_resources[] = {
 123         [0] = {
 124                 .name   = "VEU(1)",
 125                 .start  = 0xfe920000,
 126                 .end    = 0xfe9200b7,
 127                 .flags  = IORESOURCE_MEM,
 128         },
 129         [1] = {
 130                 /* place holder for contiguous memory */
 131         },
 132 };
 133
 134 static struct platform_device veu0_device = {
 135         .name           = "uio_pdrv_genirq",
 136         .id             = 1,
 137         .dev = {
 138                 .platform_data  = &veu0_platform_data,
 139         },
 140         .resource       = veu0_resources,
 141         .num_resources  = ARRAY_SIZE(veu0_resources),
 142 };
 143
 144 static struct uio_info veu1_platform_data = {
 145         .name = "VEU",
 146         .version = "0",
 147         .irq = 27,
 148 };
 149
 150 static struct resource veu1_resources[] = {
 151         [0] = {
 152                 .name   = "VEU(2)",
 153                 .start  = 0xfe924000,
 154                 .end    = 0xfe9240b7,
 155                 .flags  = IORESOURCE_MEM,
 156         },
 157         [1] = {
 158                 /* place holder for contiguous memory */
 159         },
 160 };
 161
 162 static struct platform_device veu1_device = {
 163         .name           = "uio_pdrv_genirq",
 164         .id             = 2,
 165         .dev = {
 166                 .platform_data  = &veu1_platform_data,
 167         },
 168         .resource       = veu1_resources,
 169         .num_resources  = ARRAY_SIZE(veu1_resources),
 170 };
 171
 172 static struct sh_timer_config cmt_platform_data = {
 173         .channel_offset = 0x60,
 174         .timer_bit = 5,
 175         .clockevent_rating = 125,
 176         .clocksource_rating = 200,
 177 };
 178
 179 static struct resource cmt_resources[] = {
 180         [0] = {
 181                 .start  = 0x044a0060,
 182                 .end    = 0x044a006b,
 183                 .flags  = IORESOURCE_MEM,
 184         },
 185         [1] = {
 186                 .start  = 104,
 187                 .flags  = IORESOURCE_IRQ,
 188         },
 189 };
 190
 191 static struct platform_device cmt_device = {
 192         .name           = "sh_cmt",
 193         .id             = 0,
 194         .dev = {
 195                 .platform_data  = &cmt_platform_data,
 196         },
 197         .resource       = cmt_resources,
 198         .num_resources  = ARRAY_SIZE(cmt_resources),
 199 };
 200
 201 static struct sh_timer_config tmu0_platform_data = {
 202         .channel_offset = 0x04,
 203         .timer_bit = 0,
 204         .clockevent_rating = 200,
 205 };
 206
 207 static struct resource tmu0_resources[] = {
 208         [0] = {
 209                 .start  = 0xffd80008,
 210                 .end    = 0xffd80013,
 211                 .flags  = IORESOURCE_MEM,
 212         },
 213         [1] = {
 214                 .start  = 16,
 215                 .flags  = IORESOURCE_IRQ,
 216         },
 217 };
 218
 219 static struct platform_device tmu0_device = {
 220         .name           = "sh_tmu",
 221         .id             = 0,
 222         .dev = {
 223                 .platform_data  = &tmu0_platform_data,
 224         },
 225         .resource       = tmu0_resources,
 226         .num_resources  = ARRAY_SIZE(tmu0_resources),
 227 };
 228
 229 static struct sh_timer_config tmu1_platform_data = {
 230         .channel_offset = 0x10,
 231         .timer_bit = 1,
 232         .clocksource_rating = 200,
 233 };
 234
 235 static struct resource tmu1_resources[] = {
 236         [0] = {
 237                 .start  = 0xffd80014,
 238                 .end    = 0xffd8001f,
 239                 .flags  = IORESOURCE_MEM,
 240         },
 241         [1] = {
 242                 .start  = 17,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 static struct platform_device tmu1_device = {
 248         .name           = "sh_tmu",
 249         .id             = 1,
 250         .dev = {
 251                 .platform_data  = &tmu1_platform_data,
 252         },
 253         .resource       = tmu1_resources,
 254         .num_resources  = ARRAY_SIZE(tmu1_resources),
 255 };
 256
 257 static struct sh_timer_config tmu2_platform_data = {
 258         .channel_offset = 0x1c,
 259         .timer_bit = 2,
 260 };
 261
 262 static struct resource tmu2_resources[] = {
 263         [0] = {
 264                 .start  = 0xffd80020,
 265                 .end    = 0xffd8002b,
 266                 .flags  = IORESOURCE_MEM,
 267         },
 268         [1] = {
 269                 .start  = 18,
 270                 .flags  = IORESOURCE_IRQ,
 271         },
 272 };
 273
 274 static struct platform_device tmu2_device = {
 275         .name           = "sh_tmu",
 276         .id             = 2,
 277         .dev = {
 278                 .platform_data  = &tmu2_platform_data,
 279         },
 280         .resource       = tmu2_resources,
 281         .num_resources  = ARRAY_SIZE(tmu2_resources),
 282 };
 283
 284 static struct platform_device *sh7366_devices[] __initdata = {
 285         &scif0_device,
 286         &cmt_device,
 287         &tmu0_device,
 288         &tmu1_device,
 289         &tmu2_device,
 290         &iic_device,
 291         &usb_host_device,
 292         &vpu_device,
 293         &veu0_device,
 294         &veu1_device,
 295 };
 296
 297 static int __init sh7366_devices_setup(void)
 298 {
 299         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 300         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 301         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 302
 303         return platform_add_devices(sh7366_devices,
 304                                     ARRAY_SIZE(sh7366_devices));
 305 }
 306 arch_initcall(sh7366_devices_setup);
 307
 308 static struct platform_device *sh7366_early_devices[] __initdata = {
 309         &scif0_device,
 310         &cmt_device,
 311         &tmu0_device,
 312         &tmu1_device,
 313         &tmu2_device,
 314 };
 315
 316 void __init plat_early_device_setup(void)
 317 {
 318         early_platform_add_devices(sh7366_early_devices,
 319                                    ARRAY_SIZE(sh7366_early_devices));
 320 }
 321
 322 enum {
 323         UNUSED=0,
 324         ENABLED,
 325         DISABLED,
 326
 327         /* interrupt sources */
 328         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 329         ICB,
 330         DMAC0, DMAC1, DMAC2, DMAC3,
 331         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 332         MFI, VPU, USB,
 333         MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
 334         DMAC4, DMAC5, DMAC_DADERR,
 335         SCIF, SCIFA1, SCIFA2,
 336         DENC, MSIOF,
 337         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 338         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 339         SDHI, CMT, TSIF, SIU,
 340         TMU0, TMU1, TMU2,
 341         VEU2, LCDC,
 342
 343         /* interrupt groups */
 344
 345         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
 346 };
 347
 348 static struct intc_vect vectors[] __initdata = {
 349         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 350         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 351         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 352         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 353         INTC_VECT(ICB, 0x700),
 354         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 355         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 356         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 357         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 358         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
 359         INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
 360         INTC_VECT(MMC_MMC3I, 0xb40),
 361         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 362         INTC_VECT(DMAC_DADERR, 0xbc0),
 363         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
 364         INTC_VECT(SCIFA2, 0xc40),
 365         INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
 366         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 367         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 368         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 369         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 370         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 371         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 372         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 373         INTC_VECT(SIU, 0xf80),
 374         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 375         INTC_VECT(TMU2, 0x440),
 376         INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
 377 };
 378
 379 static struct intc_group groups[] __initdata = {
 380         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 381         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 382         INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
 383         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 384         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 385                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 386         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 387 };
 388
 389 static struct intc_mask_reg mask_registers[] __initdata = {
 390         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 391           { } },
 392         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 393           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 394         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 395           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 396         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 397           { 0, 0, 0, ICB } },
 398         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 399           { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
 400         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 401           { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
 402         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 403           { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
 404         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 405           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 406             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 407         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 408           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
 409         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 410           { 0, 0, 0, CMT, 0, USB, } },
 411         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 412           { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
 413         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 414           { 0, 0, 0, 0, 0, 0, 0, TSIF } },
 415         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 416           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 417 };
 418
 419 static struct intc_prio_reg prio_registers[] __initdata = {
 420         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 421         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
 422         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 423         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 424         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 425         { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
 426         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
 427         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
 428         { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
 429         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 430         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 431         { 0xa408002c, 0, 16, 4, /* IPRL */ { } },
 432         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 433           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 434 };
 435
 436 static struct intc_sense_reg sense_registers[] __initdata = {
 437         { 0xa414001c, 16, 2, /* ICR1 */
 438           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 439 };
 440
 441 static struct intc_mask_reg ack_registers[] __initdata = {
 442         { 0xa4140024, 0, 8, /* INTREQ00 */
 443           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 444 };
 445
 446 static struct intc_desc intc_desc __initdata = {
 447         .name = "sh7366",
 448         .force_enable = ENABLED,
 449         .force_disable = DISABLED,
 450         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 451                            prio_registers, sense_registers, ack_registers),
 452 };
 453
 454 void __init plat_irq_setup(void)
 455 {
 456         register_intc_controller(&intc_desc);
 457 }
 458
 459 void __init plat_mem_setup(void)
 460 {
 461         /* TODO: Register Node 1 */
 462 }