arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/mm.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/uio_driver.h>
  17 #include <linux/usb/m66592.h>
  18
  19 #include <asm/clock.h>
  20 #include <asm/dmaengine.h>
  21 #include <asm/mmzone.h>
  22 #include <asm/siu.h>
  23
  24 #include <cpu/dma-register.h>
  25 #include <cpu/sh7722.h>
  26
  27 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
  28         {
  29                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
  30                 .addr           = 0xffe0000c,
  31                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  32                 .mid_rid        = 0x21,
  33         }, {
  34                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
  35                 .addr           = 0xffe00014,
  36                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  37                 .mid_rid        = 0x22,
  38         }, {
  39                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
  40                 .addr           = 0xffe1000c,
  41                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  42                 .mid_rid        = 0x25,
  43         }, {
  44                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
  45                 .addr           = 0xffe10014,
  46                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  47                 .mid_rid        = 0x26,
  48         }, {
  49                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
  50                 .addr           = 0xffe2000c,
  51                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  52                 .mid_rid        = 0x29,
  53         }, {
  54                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
  55                 .addr           = 0xffe20014,
  56                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  57                 .mid_rid        = 0x2a,
  58         }, {
  59                 .slave_id       = SHDMA_SLAVE_SIUA_TX,
  60                 .addr           = 0xa454c098,
  61                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  62                 .mid_rid        = 0xb1,
  63         }, {
  64                 .slave_id       = SHDMA_SLAVE_SIUA_RX,
  65                 .addr           = 0xa454c090,
  66                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  67                 .mid_rid        = 0xb2,
  68         }, {
  69                 .slave_id       = SHDMA_SLAVE_SIUB_TX,
  70                 .addr           = 0xa454c09c,
  71                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  72                 .mid_rid        = 0xb5,
  73         }, {
  74                 .slave_id       = SHDMA_SLAVE_SIUB_RX,
  75                 .addr           = 0xa454c094,
  76                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
  77                 .mid_rid        = 0xb6,
  78         },
  79 };
  80
  81 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
  82         {
  83                 .offset = 0,
  84                 .dmars = 0,
  85                 .dmars_bit = 0,
  86         }, {
  87                 .offset = 0x10,
  88                 .dmars = 0,
  89                 .dmars_bit = 8,
  90         }, {
  91                 .offset = 0x20,
  92                 .dmars = 4,
  93                 .dmars_bit = 0,
  94         }, {
  95                 .offset = 0x30,
  96                 .dmars = 4,
  97                 .dmars_bit = 8,
  98         }, {
  99                 .offset = 0x50,
 100                 .dmars = 8,
 101                 .dmars_bit = 0,
 102         }, {
 103                 .offset = 0x60,
 104                 .dmars = 8,
 105                 .dmars_bit = 8,
 106         }
 107 };
 108
 109 static const unsigned int ts_shift[] = TS_SHIFT;
 110
 111 static struct sh_dmae_pdata dma_platform_data = {
 112         .slave          = sh7722_dmae_slaves,
 113         .slave_num      = ARRAY_SIZE(sh7722_dmae_slaves),
 114         .channel        = sh7722_dmae_channels,
 115         .channel_num    = ARRAY_SIZE(sh7722_dmae_channels),
 116         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 117         .ts_low_mask    = CHCR_TS_LOW_MASK,
 118         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 119         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 120         .ts_shift       = ts_shift,
 121         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 122         .dmaor_init     = DMAOR_INIT,
 123 };
 124
 125 static struct resource sh7722_dmae_resources[] = {
 126         [0] = {
 127                 /* Channel registers and DMAOR */
 128                 .start  = 0xfe008020,
 129                 .end    = 0xfe00808f,
 130                 .flags  = IORESOURCE_MEM,
 131         },
 132         [1] = {
 133                 /* DMARSx */
 134                 .start  = 0xfe009000,
 135                 .end    = 0xfe00900b,
 136                 .flags  = IORESOURCE_MEM,
 137         },
 138         {
 139                 /* DMA error IRQ */
 140                 .start  = 78,
 141                 .end    = 78,
 142                 .flags  = IORESOURCE_IRQ,
 143         },
 144         {
 145                 /* IRQ for channels 0-3 */
 146                 .start  = 48,
 147                 .end    = 51,
 148                 .flags  = IORESOURCE_IRQ,
 149         },
 150         {
 151                 /* IRQ for channels 4-5 */
 152                 .start  = 76,
 153                 .end    = 77,
 154                 .flags  = IORESOURCE_IRQ,
 155         },
 156 };
 157
 158 struct platform_device dma_device = {
 159         .name           = "sh-dma-engine",
 160         .id             = -1,
 161         .resource       = sh7722_dmae_resources,
 162         .num_resources  = ARRAY_SIZE(sh7722_dmae_resources),
 163         .dev            = {
 164                 .platform_data  = &dma_platform_data,
 165         },
 166         .archdata = {
 167                 .hwblk_id = HWBLK_DMAC,
 168         },
 169 };
 170
 171 /* Serial */
 172 static struct plat_sci_port scif0_platform_data = {
 173         .mapbase        = 0xffe00000,
 174         .flags          = UPF_BOOT_AUTOCONF,
 175         .type           = PORT_SCIF,
 176         .irqs           = { 80, 80, 80, 80 },
 177 };
 178
 179 static struct platform_device scif0_device = {
 180         .name           = "sh-sci",
 181         .id             = 0,
 182         .dev            = {
 183                 .platform_data  = &scif0_platform_data,
 184         },
 185 };
 186
 187 static struct plat_sci_port scif1_platform_data = {
 188         .mapbase        = 0xffe10000,
 189         .flags          = UPF_BOOT_AUTOCONF,
 190         .type           = PORT_SCIF,
 191         .irqs           = { 81, 81, 81, 81 },
 192 };
 193
 194 static struct platform_device scif1_device = {
 195         .name           = "sh-sci",
 196         .id             = 1,
 197         .dev            = {
 198                 .platform_data  = &scif1_platform_data,
 199         },
 200 };
 201
 202 static struct plat_sci_port scif2_platform_data = {
 203         .mapbase        = 0xffe20000,
 204         .flags          = UPF_BOOT_AUTOCONF,
 205         .type           = PORT_SCIF,
 206         .irqs           = { 82, 82, 82, 82 },
 207 };
 208
 209 static struct platform_device scif2_device = {
 210         .name           = "sh-sci",
 211         .id             = 2,
 212         .dev            = {
 213                 .platform_data  = &scif2_platform_data,
 214         },
 215 };
 216
 217 static struct resource rtc_resources[] = {
 218         [0] = {
 219                 .start  = 0xa465fec0,
 220                 .end    = 0xa465fec0 + 0x58 - 1,
 221                 .flags  = IORESOURCE_IO,
 222         },
 223         [1] = {
 224                 /* Period IRQ */
 225                 .start  = 45,
 226                 .flags  = IORESOURCE_IRQ,
 227         },
 228         [2] = {
 229                 /* Carry IRQ */
 230                 .start  = 46,
 231                 .flags  = IORESOURCE_IRQ,
 232         },
 233         [3] = {
 234                 /* Alarm IRQ */
 235                 .start  = 44,
 236                 .flags  = IORESOURCE_IRQ,
 237         },
 238 };
 239
 240 static struct platform_device rtc_device = {
 241         .name           = "sh-rtc",
 242         .id             = -1,
 243         .num_resources  = ARRAY_SIZE(rtc_resources),
 244         .resource       = rtc_resources,
 245         .archdata = {
 246                 .hwblk_id = HWBLK_RTC,
 247         },
 248 };
 249
 250 static struct m66592_platdata usbf_platdata = {
 251         .on_chip = 1,
 252 };
 253
 254 static struct resource usbf_resources[] = {
 255         [0] = {
 256                 .name   = "USBF",
 257                 .start  = 0x04480000,
 258                 .end    = 0x044800FF,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         [1] = {
 262                 .start  = 65,
 263                 .end    = 65,
 264                 .flags  = IORESOURCE_IRQ,
 265         },
 266 };
 267
 268 static struct platform_device usbf_device = {
 269         .name           = "m66592_udc",
 270         .id             = 0, /* "usbf0" clock */
 271         .dev = {
 272                 .dma_mask               = NULL,
 273                 .coherent_dma_mask      = 0xffffffff,
 274                 .platform_data          = &usbf_platdata,
 275         },
 276         .num_resources  = ARRAY_SIZE(usbf_resources),
 277         .resource       = usbf_resources,
 278         .archdata = {
 279                 .hwblk_id = HWBLK_USBF,
 280         },
 281 };
 282
 283 static struct resource iic_resources[] = {
 284         [0] = {
 285                 .name   = "IIC",
 286                 .start  = 0x04470000,
 287                 .end    = 0x04470017,
 288                 .flags  = IORESOURCE_MEM,
 289         },
 290         [1] = {
 291                 .start  = 96,
 292                 .end    = 99,
 293                 .flags  = IORESOURCE_IRQ,
 294        },
 295 };
 296
 297 static struct platform_device iic_device = {
 298         .name           = "i2c-sh_mobile",
 299         .id             = 0, /* "i2c0" clock */
 300         .num_resources  = ARRAY_SIZE(iic_resources),
 301         .resource       = iic_resources,
 302         .archdata = {
 303                 .hwblk_id = HWBLK_IIC,
 304         },
 305 };
 306
 307 static struct uio_info vpu_platform_data = {
 308         .name = "VPU4",
 309         .version = "0",
 310         .irq = 60,
 311 };
 312
 313 static struct resource vpu_resources[] = {
 314         [0] = {
 315                 .name   = "VPU",
 316                 .start  = 0xfe900000,
 317                 .end    = 0xfe9022eb,
 318                 .flags  = IORESOURCE_MEM,
 319         },
 320         [1] = {
 321                 /* place holder for contiguous memory */
 322         },
 323 };
 324
 325 static struct platform_device vpu_device = {
 326         .name           = "uio_pdrv_genirq",
 327         .id             = 0,
 328         .dev = {
 329                 .platform_data  = &vpu_platform_data,
 330         },
 331         .resource       = vpu_resources,
 332         .num_resources  = ARRAY_SIZE(vpu_resources),
 333         .archdata = {
 334                 .hwblk_id = HWBLK_VPU,
 335         },
 336 };
 337
 338 static struct uio_info veu_platform_data = {
 339         .name = "VEU",
 340         .version = "0",
 341         .irq = 54,
 342 };
 343
 344 static struct resource veu_resources[] = {
 345         [0] = {
 346                 .name   = "VEU",
 347                 .start  = 0xfe920000,
 348                 .end    = 0xfe9200b7,
 349                 .flags  = IORESOURCE_MEM,
 350         },
 351         [1] = {
 352                 /* place holder for contiguous memory */
 353         },
 354 };
 355
 356 static struct platform_device veu_device = {
 357         .name           = "uio_pdrv_genirq",
 358         .id             = 1,
 359         .dev = {
 360                 .platform_data  = &veu_platform_data,
 361         },
 362         .resource       = veu_resources,
 363         .num_resources  = ARRAY_SIZE(veu_resources),
 364         .archdata = {
 365                 .hwblk_id = HWBLK_VEU,
 366         },
 367 };
 368
 369 static struct uio_info jpu_platform_data = {
 370         .name = "JPU",
 371         .version = "0",
 372         .irq = 27,
 373 };
 374
 375 static struct resource jpu_resources[] = {
 376         [0] = {
 377                 .name   = "JPU",
 378                 .start  = 0xfea00000,
 379                 .end    = 0xfea102d3,
 380                 .flags  = IORESOURCE_MEM,
 381         },
 382         [1] = {
 383                 /* place holder for contiguous memory */
 384         },
 385 };
 386
 387 static struct platform_device jpu_device = {
 388         .name           = "uio_pdrv_genirq",
 389         .id             = 2,
 390         .dev = {
 391                 .platform_data  = &jpu_platform_data,
 392         },
 393         .resource       = jpu_resources,
 394         .num_resources  = ARRAY_SIZE(jpu_resources),
 395         .archdata = {
 396                 .hwblk_id = HWBLK_JPU,
 397         },
 398 };
 399
 400 static struct sh_timer_config cmt_platform_data = {
 401         .channel_offset = 0x60,
 402         .timer_bit = 5,
 403         .clockevent_rating = 125,
 404         .clocksource_rating = 125,
 405 };
 406
 407 static struct resource cmt_resources[] = {
 408         [0] = {
 409                 .start  = 0x044a0060,
 410                 .end    = 0x044a006b,
 411                 .flags  = IORESOURCE_MEM,
 412         },
 413         [1] = {
 414                 .start  = 104,
 415                 .flags  = IORESOURCE_IRQ,
 416         },
 417 };
 418
 419 static struct platform_device cmt_device = {
 420         .name           = "sh_cmt",
 421         .id             = 0,
 422         .dev = {
 423                 .platform_data  = &cmt_platform_data,
 424         },
 425         .resource       = cmt_resources,
 426         .num_resources  = ARRAY_SIZE(cmt_resources),
 427         .archdata = {
 428                 .hwblk_id = HWBLK_CMT,
 429         },
 430 };
 431
 432 static struct sh_timer_config tmu0_platform_data = {
 433         .channel_offset = 0x04,
 434         .timer_bit = 0,
 435         .clockevent_rating = 200,
 436 };
 437
 438 static struct resource tmu0_resources[] = {
 439         [0] = {
 440                 .start  = 0xffd80008,
 441                 .end    = 0xffd80013,
 442                 .flags  = IORESOURCE_MEM,
 443         },
 444         [1] = {
 445                 .start  = 16,
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448 };
 449
 450 static struct platform_device tmu0_device = {
 451         .name           = "sh_tmu",
 452         .id             = 0,
 453         .dev = {
 454                 .platform_data  = &tmu0_platform_data,
 455         },
 456         .resource       = tmu0_resources,
 457         .num_resources  = ARRAY_SIZE(tmu0_resources),
 458         .archdata = {
 459                 .hwblk_id = HWBLK_TMU,
 460         },
 461 };
 462
 463 static struct sh_timer_config tmu1_platform_data = {
 464         .channel_offset = 0x10,
 465         .timer_bit = 1,
 466         .clocksource_rating = 200,
 467 };
 468
 469 static struct resource tmu1_resources[] = {
 470         [0] = {
 471                 .start  = 0xffd80014,
 472                 .end    = 0xffd8001f,
 473                 .flags  = IORESOURCE_MEM,
 474         },
 475         [1] = {
 476                 .start  = 17,
 477                 .flags  = IORESOURCE_IRQ,
 478         },
 479 };
 480
 481 static struct platform_device tmu1_device = {
 482         .name           = "sh_tmu",
 483         .id             = 1,
 484         .dev = {
 485                 .platform_data  = &tmu1_platform_data,
 486         },
 487         .resource       = tmu1_resources,
 488         .num_resources  = ARRAY_SIZE(tmu1_resources),
 489         .archdata = {
 490                 .hwblk_id = HWBLK_TMU,
 491         },
 492 };
 493
 494 static struct sh_timer_config tmu2_platform_data = {
 495         .channel_offset = 0x1c,
 496         .timer_bit = 2,
 497 };
 498
 499 static struct resource tmu2_resources[] = {
 500         [0] = {
 501                 .start  = 0xffd80020,
 502                 .end    = 0xffd8002b,
 503                 .flags  = IORESOURCE_MEM,
 504         },
 505         [1] = {
 506                 .start  = 18,
 507                 .flags  = IORESOURCE_IRQ,
 508         },
 509 };
 510
 511 static struct platform_device tmu2_device = {
 512         .name           = "sh_tmu",
 513         .id             = 2,
 514         .dev = {
 515                 .platform_data  = &tmu2_platform_data,
 516         },
 517         .resource       = tmu2_resources,
 518         .num_resources  = ARRAY_SIZE(tmu2_resources),
 519         .archdata = {
 520                 .hwblk_id = HWBLK_TMU,
 521         },
 522 };
 523
 524 static struct siu_platform siu_platform_data = {
 525         .dma_dev        = &dma_device.dev,
 526         .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
 527         .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
 528         .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
 529         .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
 530 };
 531
 532 static struct resource siu_resources[] = {
 533         [0] = {
 534                 .start  = 0xa4540000,
 535                 .end    = 0xa454c10f,
 536                 .flags  = IORESOURCE_MEM,
 537         },
 538         [1] = {
 539                 .start  = 108,
 540                 .flags  = IORESOURCE_IRQ,
 541         },
 542 };
 543
 544 static struct platform_device siu_device = {
 545         .name           = "sh_siu",
 546         .id             = -1,
 547         .dev = {
 548                 .platform_data  = &siu_platform_data,
 549         },
 550         .resource       = siu_resources,
 551         .num_resources  = ARRAY_SIZE(siu_resources),
 552         .archdata = {
 553                 .hwblk_id = HWBLK_SIU,
 554         },
 555 };
 556
 557 static struct platform_device *sh7722_devices[] __initdata = {
 558         &scif0_device,
 559         &scif1_device,
 560         &scif2_device,
 561         &cmt_device,
 562         &tmu0_device,
 563         &tmu1_device,
 564         &tmu2_device,
 565         &rtc_device,
 566         &usbf_device,
 567         &iic_device,
 568         &vpu_device,
 569         &veu_device,
 570         &jpu_device,
 571         &siu_device,
 572         &dma_device,
 573 };
 574
 575 static int __init sh7722_devices_setup(void)
 576 {
 577         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 578         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 579         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 580
 581         return platform_add_devices(sh7722_devices,
 582                                     ARRAY_SIZE(sh7722_devices));
 583 }
 584 arch_initcall(sh7722_devices_setup);
 585
 586 static struct platform_device *sh7722_early_devices[] __initdata = {
 587         &scif0_device,
 588         &scif1_device,
 589         &scif2_device,
 590         &cmt_device,
 591         &tmu0_device,
 592         &tmu1_device,
 593         &tmu2_device,
 594 };
 595
 596 void __init plat_early_device_setup(void)
 597 {
 598         early_platform_add_devices(sh7722_early_devices,
 599                                    ARRAY_SIZE(sh7722_early_devices));
 600 }
 601
 602 enum {
 603         UNUSED=0,
 604         ENABLED,
 605         DISABLED,
 606
 607         /* interrupt sources */
 608         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 609         HUDI,
 610         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 611         RTC_ATI, RTC_PRI, RTC_CUI,
 612         DMAC0, DMAC1, DMAC2, DMAC3,
 613         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 614         VPU, TPU,
 615         USB_USBI0, USB_USBI1,
 616         DMAC4, DMAC5, DMAC_DADERR,
 617         KEYSC,
 618         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 619         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 620         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 621         CMT, TSIF, SIU, TWODG,
 622         TMU0, TMU1, TMU2,
 623         IRDA, JPU, LCDC,
 624
 625         /* interrupt groups */
 626         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 627 };
 628
 629 static struct intc_vect vectors[] __initdata = {
 630         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 631         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 632         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 633         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 634         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 635         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 636         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 637         INTC_VECT(RTC_CUI, 0x7c0),
 638         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 639         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 640         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 641         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 642         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 643         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 644         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 645         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 646         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 647         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 648         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 649         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 650         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 651         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 652         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 653         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 654         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 655         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 656         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 657         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 658         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 659         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 660 };
 661
 662 static struct intc_group groups[] __initdata = {
 663         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 664         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 665         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 666         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 667         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 668         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 669         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 670                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 671         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 672 };
 673
 674 static struct intc_mask_reg mask_registers[] __initdata = {
 675         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 676           { } },
 677         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 678           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 679         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 680           { 0, 0, 0, VPU, } },
 681         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 682           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 683         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 684           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 685         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 686           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 687         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 688           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 689         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 690           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 691             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 692         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 693           { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
 694         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 695           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 696         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 697           { } },
 698         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 699           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 700         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 701           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 702 };
 703
 704 static struct intc_prio_reg prio_registers[] __initdata = {
 705         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 706         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 707         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 708         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 709         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 710         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 711         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 712         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 713         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 714         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 715         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 716         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 717         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 718           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 719 };
 720
 721 static struct intc_sense_reg sense_registers[] __initdata = {
 722         { 0xa414001c, 16, 2, /* ICR1 */
 723           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 724 };
 725
 726 static struct intc_mask_reg ack_registers[] __initdata = {
 727         { 0xa4140024, 0, 8, /* INTREQ00 */
 728           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 729 };
 730
 731 static struct intc_desc intc_desc __initdata = {
 732         .name = "sh7722",
 733         .force_enable = ENABLED,
 734         .force_disable = DISABLED,
 735         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 736                            prio_registers, sense_registers, ack_registers),
 737 };
 738
 739 void __init plat_irq_setup(void)
 740 {
 741         register_intc_controller(&intc_desc);
 742 }
 743
 744 void __init plat_mem_setup(void)
 745 {
 746         /* Register the URAM space as Node 1 */
 747         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 748 }