arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 /*
   2  * SH7763 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2007  Yoshihiro Shimoda
   6  *  Copyright (C) 2008, 2009  Nobuhiro Iwamatsu
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17 #include <linux/serial_sci.h>
  18
  19 static struct plat_sci_port scif0_platform_data = {
  20         .mapbase        = 0xffe00000,
  21         .flags          = UPF_BOOT_AUTOCONF,
  22         .type           = PORT_SCIF,
  23         .irqs           = { 40, 40, 40, 40 },
  24 };
  25
  26 static struct platform_device scif0_device = {
  27         .name           = "sh-sci",
  28         .id             = 0,
  29         .dev            = {
  30                 .platform_data  = &scif0_platform_data,
  31         },
  32 };
  33
  34 static struct plat_sci_port scif1_platform_data = {
  35         .mapbase        = 0xffe08000,
  36         .flags          = UPF_BOOT_AUTOCONF,
  37         .type           = PORT_SCIF,
  38         .irqs           = { 76, 76, 76, 76 },
  39 };
  40
  41 static struct platform_device scif1_device = {
  42         .name           = "sh-sci",
  43         .id             = 1,
  44         .dev            = {
  45                 .platform_data  = &scif1_platform_data,
  46         },
  47 };
  48
  49 static struct plat_sci_port scif2_platform_data = {
  50         .mapbase        = 0xffe10000,
  51         .flags          = UPF_BOOT_AUTOCONF,
  52         .type           = PORT_SCIF,
  53         .irqs           = { 104, 104, 104, 104 },
  54 };
  55
  56 static struct platform_device scif2_device = {
  57         .name           = "sh-sci",
  58         .id             = 2,
  59         .dev            = {
  60                 .platform_data  = &scif2_platform_data,
  61         },
  62 };
  63
  64 static struct resource rtc_resources[] = {
  65         [0] = {
  66                 .start  = 0xffe80000,
  67                 .end    = 0xffe80000 + 0x58 - 1,
  68                 .flags  = IORESOURCE_IO,
  69         },
  70         [1] = {
  71                 /* Shared Period/Carry/Alarm IRQ */
  72                 .start  = 20,
  73                 .flags  = IORESOURCE_IRQ,
  74         },
  75 };
  76
  77 static struct platform_device rtc_device = {
  78         .name           = "sh-rtc",
  79         .id             = -1,
  80         .num_resources  = ARRAY_SIZE(rtc_resources),
  81         .resource       = rtc_resources,
  82 };
  83
  84 static struct resource usb_ohci_resources[] = {
  85         [0] = {
  86                 .start  = 0xffec8000,
  87                 .end    = 0xffec80ff,
  88                 .flags  = IORESOURCE_MEM,
  89         },
  90         [1] = {
  91                 .start  = 83,
  92                 .end    = 83,
  93                 .flags  = IORESOURCE_IRQ,
  94         },
  95 };
  96
  97 static u64 usb_ohci_dma_mask = 0xffffffffUL;
  98 static struct platform_device usb_ohci_device = {
  99         .name           = "sh_ohci",
 100         .id             = -1,
 101         .dev = {
 102                 .dma_mask               = &usb_ohci_dma_mask,
 103                 .coherent_dma_mask      = 0xffffffff,
 104         },
 105         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 106         .resource       = usb_ohci_resources,
 107 };
 108
 109 static struct resource usbf_resources[] = {
 110         [0] = {
 111                 .start  = 0xffec0000,
 112                 .end    = 0xffec00ff,
 113                 .flags  = IORESOURCE_MEM,
 114         },
 115         [1] = {
 116                 .start  = 84,
 117                 .end    = 84,
 118                 .flags  = IORESOURCE_IRQ,
 119         },
 120 };
 121
 122 static struct platform_device usbf_device = {
 123         .name           = "sh_udc",
 124         .id             = -1,
 125         .dev = {
 126                 .dma_mask               = NULL,
 127                 .coherent_dma_mask      = 0xffffffff,
 128         },
 129         .num_resources  = ARRAY_SIZE(usbf_resources),
 130         .resource       = usbf_resources,
 131 };
 132
 133 static struct sh_timer_config tmu0_platform_data = {
 134         .name = "TMU0",
 135         .channel_offset = 0x04,
 136         .timer_bit = 0,
 137         .clk = "peripheral_clk",
 138         .clockevent_rating = 200,
 139 };
 140
 141 static struct resource tmu0_resources[] = {
 142         [0] = {
 143                 .name   = "TMU0",
 144                 .start  = 0xffd80008,
 145                 .end    = 0xffd80013,
 146                 .flags  = IORESOURCE_MEM,
 147         },
 148         [1] = {
 149                 .start  = 28,
 150                 .flags  = IORESOURCE_IRQ,
 151         },
 152 };
 153
 154 static struct platform_device tmu0_device = {
 155         .name           = "sh_tmu",
 156         .id             = 0,
 157         .dev = {
 158                 .platform_data  = &tmu0_platform_data,
 159         },
 160         .resource       = tmu0_resources,
 161         .num_resources  = ARRAY_SIZE(tmu0_resources),
 162 };
 163
 164 static struct sh_timer_config tmu1_platform_data = {
 165         .name = "TMU1",
 166         .channel_offset = 0x10,
 167         .timer_bit = 1,
 168         .clk = "peripheral_clk",
 169         .clocksource_rating = 200,
 170 };
 171
 172 static struct resource tmu1_resources[] = {
 173         [0] = {
 174                 .name   = "TMU1",
 175                 .start  = 0xffd80014,
 176                 .end    = 0xffd8001f,
 177                 .flags  = IORESOURCE_MEM,
 178         },
 179         [1] = {
 180                 .start  = 29,
 181                 .flags  = IORESOURCE_IRQ,
 182         },
 183 };
 184
 185 static struct platform_device tmu1_device = {
 186         .name           = "sh_tmu",
 187         .id             = 1,
 188         .dev = {
 189                 .platform_data  = &tmu1_platform_data,
 190         },
 191         .resource       = tmu1_resources,
 192         .num_resources  = ARRAY_SIZE(tmu1_resources),
 193 };
 194
 195 static struct sh_timer_config tmu2_platform_data = {
 196         .name = "TMU2",
 197         .channel_offset = 0x1c,
 198         .timer_bit = 2,
 199         .clk = "peripheral_clk",
 200 };
 201
 202 static struct resource tmu2_resources[] = {
 203         [0] = {
 204                 .name   = "TMU2",
 205                 .start  = 0xffd80020,
 206                 .end    = 0xffd8002f,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209         [1] = {
 210                 .start  = 30,
 211                 .flags  = IORESOURCE_IRQ,
 212         },
 213 };
 214
 215 static struct platform_device tmu2_device = {
 216         .name           = "sh_tmu",
 217         .id             = 2,
 218         .dev = {
 219                 .platform_data  = &tmu2_platform_data,
 220         },
 221         .resource       = tmu2_resources,
 222         .num_resources  = ARRAY_SIZE(tmu2_resources),
 223 };
 224
 225 static struct sh_timer_config tmu3_platform_data = {
 226         .name = "TMU3",
 227         .channel_offset = 0x04,
 228         .timer_bit = 0,
 229         .clk = "peripheral_clk",
 230 };
 231
 232 static struct resource tmu3_resources[] = {
 233         [0] = {
 234                 .name   = "TMU3",
 235                 .start  = 0xffd88008,
 236                 .end    = 0xffd88013,
 237                 .flags  = IORESOURCE_MEM,
 238         },
 239         [1] = {
 240                 .start  = 96,
 241                 .flags  = IORESOURCE_IRQ,
 242         },
 243 };
 244
 245 static struct platform_device tmu3_device = {
 246         .name           = "sh_tmu",
 247         .id             = 3,
 248         .dev = {
 249                 .platform_data  = &tmu3_platform_data,
 250         },
 251         .resource       = tmu3_resources,
 252         .num_resources  = ARRAY_SIZE(tmu3_resources),
 253 };
 254
 255 static struct sh_timer_config tmu4_platform_data = {
 256         .name = "TMU4",
 257         .channel_offset = 0x10,
 258         .timer_bit = 1,
 259         .clk = "peripheral_clk",
 260 };
 261
 262 static struct resource tmu4_resources[] = {
 263         [0] = {
 264                 .name   = "TMU4",
 265                 .start  = 0xffd88014,
 266                 .end    = 0xffd8801f,
 267                 .flags  = IORESOURCE_MEM,
 268         },
 269         [1] = {
 270                 .start  = 97,
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273 };
 274
 275 static struct platform_device tmu4_device = {
 276         .name           = "sh_tmu",
 277         .id             = 4,
 278         .dev = {
 279                 .platform_data  = &tmu4_platform_data,
 280         },
 281         .resource       = tmu4_resources,
 282         .num_resources  = ARRAY_SIZE(tmu4_resources),
 283 };
 284
 285 static struct sh_timer_config tmu5_platform_data = {
 286         .name = "TMU5",
 287         .channel_offset = 0x1c,
 288         .timer_bit = 2,
 289         .clk = "peripheral_clk",
 290 };
 291
 292 static struct resource tmu5_resources[] = {
 293         [0] = {
 294                 .name   = "TMU5",
 295                 .start  = 0xffd88020,
 296                 .end    = 0xffd8802b,
 297                 .flags  = IORESOURCE_MEM,
 298         },
 299         [1] = {
 300                 .start  = 98,
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 static struct platform_device tmu5_device = {
 306         .name           = "sh_tmu",
 307         .id             = 5,
 308         .dev = {
 309                 .platform_data  = &tmu5_platform_data,
 310         },
 311         .resource       = tmu5_resources,
 312         .num_resources  = ARRAY_SIZE(tmu5_resources),
 313 };
 314
 315 static struct platform_device *sh7763_devices[] __initdata = {
 316         &scif0_device,
 317         &scif1_device,
 318         &scif2_device,
 319         &tmu0_device,
 320         &tmu1_device,
 321         &tmu2_device,
 322         &tmu3_device,
 323         &tmu4_device,
 324         &tmu5_device,
 325         &rtc_device,
 326         &usb_ohci_device,
 327         &usbf_device,
 328 };
 329
 330 static int __init sh7763_devices_setup(void)
 331 {
 332         return platform_add_devices(sh7763_devices,
 333                                     ARRAY_SIZE(sh7763_devices));
 334 }
 335 arch_initcall(sh7763_devices_setup);
 336
 337 static struct platform_device *sh7763_early_devices[] __initdata = {
 338         &scif0_device,
 339         &scif1_device,
 340         &scif2_device,
 341         &tmu0_device,
 342         &tmu1_device,
 343         &tmu2_device,
 344         &tmu3_device,
 345         &tmu4_device,
 346         &tmu5_device,
 347 };
 348
 349 void __init plat_early_device_setup(void)
 350 {
 351         early_platform_add_devices(sh7763_early_devices,
 352                                    ARRAY_SIZE(sh7763_early_devices));
 353 }
 354
 355 enum {
 356         UNUSED = 0,
 357
 358         /* interrupt sources */
 359
 360         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 361         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 362         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 363         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 364
 365         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 366         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 367         HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
 368         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 369         STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
 370         USBH, USBF, TPU, PCC, MMCIF, SIM,
 371         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 372         SCIF2, GPIO,
 373
 374         /* interrupt groups */
 375
 376         TMU012, TMU345,
 377 };
 378
 379 static struct intc_vect vectors[] __initdata = {
 380         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 381         INTC_VECT(RTC, 0x4c0),
 382         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 383         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 384         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 385         INTC_VECT(LCDC, 0x620),
 386         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 387         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 388         INTC_VECT(DMAC, 0x6c0),
 389         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 390         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 391         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 392         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 393         INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
 394         INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
 395         INTC_VECT(HAC, 0x980),
 396         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 397         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 398         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 399         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 400         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 401         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 402         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 403         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 404         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 405         INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
 406         INTC_VECT(USBF, 0xca0),
 407         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 408         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 409         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 410         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 411         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 412         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 413         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 414         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 415         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 416         INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
 417         INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
 418         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 419         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 420 };
 421
 422 static struct intc_group groups[] __initdata = {
 423         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 424         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 425 };
 426
 427 static struct intc_mask_reg mask_registers[] __initdata = {
 428         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 429           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 430             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 431             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 432             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 433         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 434           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 435             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 436             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 437             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 438 };
 439
 440 static struct intc_prio_reg prio_registers[] __initdata = {
 441         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 442                                                  TMU2, TMU2_TICPI } },
 443         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 444         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 445         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 446         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 447                                                  PCISERR, PCIINTA } },
 448         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 449                                                  PCIINTD, PCIC5 } },
 450         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 451         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 452         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 453         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 454         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 455         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 456         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 457         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 458 };
 459
 460 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 461                          mask_registers, prio_registers, NULL);
 462
 463 /* Support for external interrupt pins in IRQ mode */
 464 static struct intc_vect irq_vectors[] __initdata = {
 465         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 466         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 467         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 468         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 469 };
 470
 471 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 472         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 473           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 474 };
 475
 476 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 477         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 478                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 479 };
 480
 481 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 482         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 483                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 484 };
 485
 486 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 487         { 0xffd00024, 0, 32, /* INTREQ */
 488           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 489 };
 490
 491 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 492                              NULL, irq_mask_registers, irq_prio_registers,
 493                              irq_sense_registers, irq_ack_registers);
 494
 495
 496 /* External interrupt pins in IRL mode */
 497 static struct intc_vect irl_vectors[] __initdata = {
 498         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 499         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 500         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 501         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 502         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 503         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 504         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 505         INTC_VECT(IRL_HHHL, 0x3c0),
 506 };
 507
 508 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 509         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 510           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 511             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 512             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 513             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 514 };
 515
 516 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 517         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 518           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 519             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 520             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 521             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 522             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 523 };
 524
 525 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 526                         NULL, irl7654_mask_registers, NULL, NULL);
 527
 528 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 529                         NULL, irl3210_mask_registers, NULL, NULL);
 530
 531 #define INTC_ICR0       0xffd00000
 532 #define INTC_INTMSK0    0xffd00044
 533 #define INTC_INTMSK1    0xffd00048
 534 #define INTC_INTMSK2    0xffd40080
 535 #define INTC_INTMSKCLR1 0xffd00068
 536 #define INTC_INTMSKCLR2 0xffd40084
 537
 538 void __init plat_irq_setup(void)
 539 {
 540         /* disable IRQ7-0 */
 541         __raw_writel(0xff000000, INTC_INTMSK0);
 542
 543         /* disable IRL3-0 + IRL7-4 */
 544         __raw_writel(0xc0000000, INTC_INTMSK1);
 545         __raw_writel(0xfffefffe, INTC_INTMSK2);
 546
 547         register_intc_controller(&intc_desc);
 548 }
 549
 550 void __init plat_irq_setup_pins(int mode)
 551 {
 552         switch (mode) {
 553         case IRQ_MODE_IRQ:
 554                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 555                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 556                 register_intc_controller(&intc_irq_desc);
 557                 break;
 558         case IRQ_MODE_IRL7654:
 559                 /* enable IRL7-4 but don't provide any masking */
 560                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 561                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 562                 break;
 563         case IRQ_MODE_IRL3210:
 564                 /* enable IRL0-3 but don't provide any masking */
 565                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 566                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 567                 break;
 568         case IRQ_MODE_IRL7654_MASK:
 569                 /* enable IRL7-4 and mask using cpu intc controller */
 570                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 571                 register_intc_controller(&intc_irl7654_desc);
 572                 break;
 573         case IRQ_MODE_IRL3210_MASK:
 574                 /* enable IRL0-3 and mask using cpu intc controller */
 575                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 576                 register_intc_controller(&intc_irl3210_desc);
 577                 break;
 578         default:
 579                 BUG();
 580         }
 581 }