4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
17 #include <asm/dmaengine.h>
19 #include <cpu/dma-register.h>
21 static struct plat_sci_port scif0_platform_data
= {
22 .mapbase
= 0xffe00000,
23 .flags
= UPF_BOOT_AUTOCONF
,
25 .irqs
= { 40, 40, 40, 40 },
28 static struct platform_device scif0_device
= {
32 .platform_data
= &scif0_platform_data
,
36 static struct plat_sci_port scif1_platform_data
= {
37 .mapbase
= 0xffe10000,
38 .flags
= UPF_BOOT_AUTOCONF
,
40 .irqs
= { 76, 76, 76, 76 },
43 static struct platform_device scif1_device
= {
47 .platform_data
= &scif1_platform_data
,
51 static struct sh_timer_config tmu0_platform_data
= {
52 .channel_offset
= 0x04,
54 .clockevent_rating
= 200,
57 static struct resource tmu0_resources
[] = {
61 .flags
= IORESOURCE_MEM
,
65 .flags
= IORESOURCE_IRQ
,
69 static struct platform_device tmu0_device
= {
73 .platform_data
= &tmu0_platform_data
,
75 .resource
= tmu0_resources
,
76 .num_resources
= ARRAY_SIZE(tmu0_resources
),
79 static struct sh_timer_config tmu1_platform_data
= {
80 .channel_offset
= 0x10,
82 .clocksource_rating
= 200,
85 static struct resource tmu1_resources
[] = {
89 .flags
= IORESOURCE_MEM
,
93 .flags
= IORESOURCE_IRQ
,
97 static struct platform_device tmu1_device
= {
101 .platform_data
= &tmu1_platform_data
,
103 .resource
= tmu1_resources
,
104 .num_resources
= ARRAY_SIZE(tmu1_resources
),
107 static struct sh_timer_config tmu2_platform_data
= {
108 .channel_offset
= 0x1c,
112 static struct resource tmu2_resources
[] = {
116 .flags
= IORESOURCE_MEM
,
120 .flags
= IORESOURCE_IRQ
,
124 static struct platform_device tmu2_device
= {
128 .platform_data
= &tmu2_platform_data
,
130 .resource
= tmu2_resources
,
131 .num_resources
= ARRAY_SIZE(tmu2_resources
),
134 static struct sh_timer_config tmu3_platform_data
= {
135 .channel_offset
= 0x04,
139 static struct resource tmu3_resources
[] = {
143 .flags
= IORESOURCE_MEM
,
147 .flags
= IORESOURCE_IRQ
,
151 static struct platform_device tmu3_device
= {
155 .platform_data
= &tmu3_platform_data
,
157 .resource
= tmu3_resources
,
158 .num_resources
= ARRAY_SIZE(tmu3_resources
),
161 static struct sh_timer_config tmu4_platform_data
= {
162 .channel_offset
= 0x10,
166 static struct resource tmu4_resources
[] = {
170 .flags
= IORESOURCE_MEM
,
174 .flags
= IORESOURCE_IRQ
,
178 static struct platform_device tmu4_device
= {
182 .platform_data
= &tmu4_platform_data
,
184 .resource
= tmu4_resources
,
185 .num_resources
= ARRAY_SIZE(tmu4_resources
),
188 static struct sh_timer_config tmu5_platform_data
= {
189 .channel_offset
= 0x1c,
193 static struct resource tmu5_resources
[] = {
197 .flags
= IORESOURCE_MEM
,
201 .flags
= IORESOURCE_IRQ
,
205 static struct platform_device tmu5_device
= {
209 .platform_data
= &tmu5_platform_data
,
211 .resource
= tmu5_resources
,
212 .num_resources
= ARRAY_SIZE(tmu5_resources
),
215 static struct resource rtc_resources
[] = {
218 .end
= 0xffe80000 + 0x58 - 1,
219 .flags
= IORESOURCE_IO
,
222 /* Shared Period/Carry/Alarm IRQ */
224 .flags
= IORESOURCE_IRQ
,
228 static struct platform_device rtc_device
= {
231 .num_resources
= ARRAY_SIZE(rtc_resources
),
232 .resource
= rtc_resources
,
236 static const struct sh_dmae_channel sh7780_dmae0_channels
[] = {
264 static const struct sh_dmae_channel sh7780_dmae1_channels
[] = {
280 static const unsigned int ts_shift
[] = TS_SHIFT
;
282 static struct sh_dmae_pdata dma0_platform_data
= {
283 .channel
= sh7780_dmae0_channels
,
284 .channel_num
= ARRAY_SIZE(sh7780_dmae0_channels
),
285 .ts_low_shift
= CHCR_TS_LOW_SHIFT
,
286 .ts_low_mask
= CHCR_TS_LOW_MASK
,
287 .ts_high_shift
= CHCR_TS_HIGH_SHIFT
,
288 .ts_high_mask
= CHCR_TS_HIGH_MASK
,
289 .ts_shift
= ts_shift
,
290 .ts_shift_num
= ARRAY_SIZE(ts_shift
),
291 .dmaor_init
= DMAOR_INIT
,
294 static struct sh_dmae_pdata dma1_platform_data
= {
295 .channel
= sh7780_dmae1_channels
,
296 .channel_num
= ARRAY_SIZE(sh7780_dmae1_channels
),
297 .ts_low_shift
= CHCR_TS_LOW_SHIFT
,
298 .ts_low_mask
= CHCR_TS_LOW_MASK
,
299 .ts_high_shift
= CHCR_TS_HIGH_SHIFT
,
300 .ts_high_mask
= CHCR_TS_HIGH_MASK
,
301 .ts_shift
= ts_shift
,
302 .ts_shift_num
= ARRAY_SIZE(ts_shift
),
303 .dmaor_init
= DMAOR_INIT
,
306 static struct resource sh7780_dmae0_resources
[] = {
308 /* Channel registers and DMAOR */
311 .flags
= IORESOURCE_MEM
,
317 .flags
= IORESOURCE_MEM
,
320 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
323 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_SHAREABLE
,
327 static struct resource sh7780_dmae1_resources
[] = {
329 /* Channel registers and DMAOR */
332 .flags
= IORESOURCE_MEM
,
334 /* DMAC1 has no DMARS */
336 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
339 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_SHAREABLE
,
343 static struct platform_device dma0_device
= {
344 .name
= "sh-dma-engine",
346 .resource
= sh7780_dmae0_resources
,
347 .num_resources
= ARRAY_SIZE(sh7780_dmae0_resources
),
349 .platform_data
= &dma0_platform_data
,
353 static struct platform_device dma1_device
= {
354 .name
= "sh-dma-engine",
356 .resource
= sh7780_dmae1_resources
,
357 .num_resources
= ARRAY_SIZE(sh7780_dmae1_resources
),
359 .platform_data
= &dma1_platform_data
,
363 static struct platform_device
*sh7780_devices
[] __initdata
= {
377 static int __init
sh7780_devices_setup(void)
379 return platform_add_devices(sh7780_devices
,
380 ARRAY_SIZE(sh7780_devices
));
382 arch_initcall(sh7780_devices_setup
);
383 static struct platform_device
*sh7780_early_devices
[] __initdata
= {
394 void __init
plat_early_device_setup(void)
396 early_platform_add_devices(sh7780_early_devices
,
397 ARRAY_SIZE(sh7780_early_devices
));
403 /* interrupt sources */
405 IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
406 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
407 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
408 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
,
410 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
411 RTC
, WDT
, TMU0
, TMU1
, TMU2
, TMU2_TICPI
,
412 HUDI
, DMAC0
, SCIF0
, DMAC1
, CMT
, HAC
,
413 PCISERR
, PCIINTA
, PCIINTB
, PCIINTC
, PCIINTD
, PCIC5
,
414 SCIF1
, SIOF
, HSPI
, MMCIF
, TMU3
, TMU4
, TMU5
, SSI
, FLCTL
, GPIO
,
416 /* interrupt groups */
421 static struct intc_vect vectors
[] __initdata
= {
422 INTC_VECT(RTC
, 0x480), INTC_VECT(RTC
, 0x4a0),
423 INTC_VECT(RTC
, 0x4c0),
424 INTC_VECT(WDT
, 0x560),
425 INTC_VECT(TMU0
, 0x580), INTC_VECT(TMU1
, 0x5a0),
426 INTC_VECT(TMU2
, 0x5c0), INTC_VECT(TMU2_TICPI
, 0x5e0),
427 INTC_VECT(HUDI
, 0x600),
428 INTC_VECT(DMAC0
, 0x640), INTC_VECT(DMAC0
, 0x660),
429 INTC_VECT(DMAC0
, 0x680), INTC_VECT(DMAC0
, 0x6a0),
430 INTC_VECT(DMAC0
, 0x6c0),
431 INTC_VECT(SCIF0
, 0x700), INTC_VECT(SCIF0
, 0x720),
432 INTC_VECT(SCIF0
, 0x740), INTC_VECT(SCIF0
, 0x760),
433 INTC_VECT(DMAC0
, 0x780), INTC_VECT(DMAC0
, 0x7a0),
434 INTC_VECT(DMAC1
, 0x7c0), INTC_VECT(DMAC1
, 0x7e0),
435 INTC_VECT(CMT
, 0x900), INTC_VECT(HAC
, 0x980),
436 INTC_VECT(PCISERR
, 0xa00), INTC_VECT(PCIINTA
, 0xa20),
437 INTC_VECT(PCIINTB
, 0xa40), INTC_VECT(PCIINTC
, 0xa60),
438 INTC_VECT(PCIINTD
, 0xa80), INTC_VECT(PCIC5
, 0xaa0),
439 INTC_VECT(PCIC5
, 0xac0), INTC_VECT(PCIC5
, 0xae0),
440 INTC_VECT(PCIC5
, 0xb00), INTC_VECT(PCIC5
, 0xb20),
441 INTC_VECT(SCIF1
, 0xb80), INTC_VECT(SCIF1
, 0xba0),
442 INTC_VECT(SCIF1
, 0xbc0), INTC_VECT(SCIF1
, 0xbe0),
443 INTC_VECT(SIOF
, 0xc00), INTC_VECT(HSPI
, 0xc80),
444 INTC_VECT(MMCIF
, 0xd00), INTC_VECT(MMCIF
, 0xd20),
445 INTC_VECT(MMCIF
, 0xd40), INTC_VECT(MMCIF
, 0xd60),
446 INTC_VECT(DMAC1
, 0xd80), INTC_VECT(DMAC1
, 0xda0),
447 INTC_VECT(DMAC1
, 0xdc0), INTC_VECT(DMAC1
, 0xde0),
448 INTC_VECT(TMU3
, 0xe00), INTC_VECT(TMU4
, 0xe20),
449 INTC_VECT(TMU5
, 0xe40),
450 INTC_VECT(SSI
, 0xe80),
451 INTC_VECT(FLCTL
, 0xf00), INTC_VECT(FLCTL
, 0xf20),
452 INTC_VECT(FLCTL
, 0xf40), INTC_VECT(FLCTL
, 0xf60),
453 INTC_VECT(GPIO
, 0xf80), INTC_VECT(GPIO
, 0xfa0),
454 INTC_VECT(GPIO
, 0xfc0), INTC_VECT(GPIO
, 0xfe0),
457 static struct intc_group groups
[] __initdata
= {
458 INTC_GROUP(TMU012
, TMU0
, TMU1
, TMU2
, TMU2_TICPI
),
459 INTC_GROUP(TMU345
, TMU3
, TMU4
, TMU5
),
462 static struct intc_mask_reg mask_registers
[] __initdata
= {
463 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
464 { 0, 0, 0, 0, 0, 0, GPIO
, FLCTL
,
465 SSI
, MMCIF
, HSPI
, SIOF
, PCIC5
, PCIINTD
, PCIINTC
, PCIINTB
,
466 PCIINTA
, PCISERR
, HAC
, CMT
, 0, 0, DMAC1
, DMAC0
,
467 HUDI
, 0, WDT
, SCIF1
, SCIF0
, RTC
, TMU345
, TMU012
} },
470 static struct intc_prio_reg prio_registers
[] __initdata
= {
471 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0
, TMU1
,
472 TMU2
, TMU2_TICPI
} },
473 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3
, TMU4
, TMU5
, RTC
} },
474 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0
, SCIF1
, WDT
} },
475 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI
, DMAC0
, DMAC1
} },
476 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT
, HAC
,
477 PCISERR
, PCIINTA
, } },
478 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB
, PCIINTC
,
480 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF
, HSPI
, MMCIF
, SSI
} },
481 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL
, GPIO
} },
484 static DECLARE_INTC_DESC(intc_desc
, "sh7780", vectors
, groups
,
485 mask_registers
, prio_registers
, NULL
);
487 /* Support for external interrupt pins in IRQ mode */
489 static struct intc_vect irq_vectors
[] __initdata
= {
490 INTC_VECT(IRQ0
, 0x240), INTC_VECT(IRQ1
, 0x280),
491 INTC_VECT(IRQ2
, 0x2c0), INTC_VECT(IRQ3
, 0x300),
492 INTC_VECT(IRQ4
, 0x340), INTC_VECT(IRQ5
, 0x380),
493 INTC_VECT(IRQ6
, 0x3c0), INTC_VECT(IRQ7
, 0x200),
496 static struct intc_mask_reg irq_mask_registers
[] __initdata
= {
497 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
498 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
501 static struct intc_prio_reg irq_prio_registers
[] __initdata
= {
502 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
503 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
506 static struct intc_sense_reg irq_sense_registers
[] __initdata
= {
507 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
508 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
511 static struct intc_mask_reg irq_ack_registers
[] __initdata
= {
512 { 0xffd00024, 0, 32, /* INTREQ */
513 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
516 static DECLARE_INTC_DESC_ACK(intc_irq_desc
, "sh7780-irq", irq_vectors
,
517 NULL
, irq_mask_registers
, irq_prio_registers
,
518 irq_sense_registers
, irq_ack_registers
);
520 /* External interrupt pins in IRL mode */
522 static struct intc_vect irl_vectors
[] __initdata
= {
523 INTC_VECT(IRL_LLLL
, 0x200), INTC_VECT(IRL_LLLH
, 0x220),
524 INTC_VECT(IRL_LLHL
, 0x240), INTC_VECT(IRL_LLHH
, 0x260),
525 INTC_VECT(IRL_LHLL
, 0x280), INTC_VECT(IRL_LHLH
, 0x2a0),
526 INTC_VECT(IRL_LHHL
, 0x2c0), INTC_VECT(IRL_LHHH
, 0x2e0),
527 INTC_VECT(IRL_HLLL
, 0x300), INTC_VECT(IRL_HLLH
, 0x320),
528 INTC_VECT(IRL_HLHL
, 0x340), INTC_VECT(IRL_HLHH
, 0x360),
529 INTC_VECT(IRL_HHLL
, 0x380), INTC_VECT(IRL_HHLH
, 0x3a0),
530 INTC_VECT(IRL_HHHL
, 0x3c0),
533 static struct intc_mask_reg irl3210_mask_registers
[] __initdata
= {
534 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
535 { IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
536 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
537 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
538 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
, } },
541 static struct intc_mask_reg irl7654_mask_registers
[] __initdata
= {
542 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
543 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
544 IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
545 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
546 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
547 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
, } },
550 static DECLARE_INTC_DESC(intc_irl7654_desc
, "sh7780-irl7654", irl_vectors
,
551 NULL
, irl7654_mask_registers
, NULL
, NULL
);
553 static DECLARE_INTC_DESC(intc_irl3210_desc
, "sh7780-irl3210", irl_vectors
,
554 NULL
, irl3210_mask_registers
, NULL
, NULL
);
556 #define INTC_ICR0 0xffd00000
557 #define INTC_INTMSK0 0xffd00044
558 #define INTC_INTMSK1 0xffd00048
559 #define INTC_INTMSK2 0xffd40080
560 #define INTC_INTMSKCLR1 0xffd00068
561 #define INTC_INTMSKCLR2 0xffd40084
563 void __init
plat_irq_setup(void)
566 __raw_writel(0xff000000, INTC_INTMSK0
);
568 /* disable IRL3-0 + IRL7-4 */
569 __raw_writel(0xc0000000, INTC_INTMSK1
);
570 __raw_writel(0xfffefffe, INTC_INTMSK2
);
572 /* select IRL mode for IRL3-0 + IRL7-4 */
573 __raw_writel(__raw_readl(INTC_ICR0
) & ~0x00c00000, INTC_ICR0
);
575 /* disable holding function, ie enable "SH-4 Mode" */
576 __raw_writel(__raw_readl(INTC_ICR0
) | 0x00200000, INTC_ICR0
);
578 register_intc_controller(&intc_desc
);
581 void __init
plat_irq_setup_pins(int mode
)
585 /* select IRQ mode for IRL3-0 + IRL7-4 */
586 __raw_writel(__raw_readl(INTC_ICR0
) | 0x00c00000, INTC_ICR0
);
587 register_intc_controller(&intc_irq_desc
);
589 case IRQ_MODE_IRL7654
:
590 /* enable IRL7-4 but don't provide any masking */
591 __raw_writel(0x40000000, INTC_INTMSKCLR1
);
592 __raw_writel(0x0000fffe, INTC_INTMSKCLR2
);
594 case IRQ_MODE_IRL3210
:
595 /* enable IRL0-3 but don't provide any masking */
596 __raw_writel(0x80000000, INTC_INTMSKCLR1
);
597 __raw_writel(0xfffe0000, INTC_INTMSKCLR2
);
599 case IRQ_MODE_IRL7654_MASK
:
600 /* enable IRL7-4 and mask using cpu intc controller */
601 __raw_writel(0x40000000, INTC_INTMSKCLR1
);
602 register_intc_controller(&intc_irl7654_desc
);
604 case IRQ_MODE_IRL3210_MASK
:
605 /* enable IRL0-3 and mask using cpu intc controller */
606 __raw_writel(0x80000000, INTC_INTMSKCLR1
);
607 register_intc_controller(&intc_irl3210_desc
);