arch/sh/kernel/head.S

   1 /* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
   2  *
   3  *  arch/sh/kernel/head.S
   4  *
   5  *  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  *
  11  * Head.S contains the SH exception handlers and startup code.
  12  */
  13 #include <linux/linkage.h>
  14 #include <asm/thread_info.h>
  15
  16 #ifdef CONFIG_CPU_SH4A
  17 #define SYNCO()         synco
  18
  19 #define PREFI(label, reg)       \
  20         mov.l   label, reg;     \
  21         prefi   @reg
  22 #else
  23 #define SYNCO()
  24 #define PREFI(label, reg)
  25 #endif
  26
  27         .section        .empty_zero_page, "aw"
  28 ENTRY(empty_zero_page)
  29         .long   1               /* MOUNT_ROOT_RDONLY */
  30         .long   0               /* RAMDISK_FLAGS */
  31         .long   0x0200          /* ORIG_ROOT_DEV */
  32         .long   1               /* LOADER_TYPE */
  33         .long   0x00360000      /* INITRD_START */
  34         .long   0x000a0000      /* INITRD_SIZE */
  35         .long   0
  36         .balign 4096,0,4096
  37
  38         .text
  39 /*
  40  * Condition at the entry of _stext:
  41  *
  42  *   BSC has already been initialized.
  43  *   INTC may or may not be initialized.
  44  *   VBR may or may not be initialized.
  45  *   MMU may or may not be initialized.
  46  *   Cache may or may not be initialized.
  47  *   Hardware (including on-chip modules) may or may not be initialized.
  48  *
  49  */
  50 ENTRY(_stext)
  51         !                       Initialize Status Register
  52         mov.l   1f, r0          ! MD=1, RB=0, BL=0, IMASK=0xF
  53         ldc     r0, sr
  54         !                       Initialize global interrupt mask
  55         mov     #0, r0
  56 #ifdef CONFIG_CPU_HAS_SR_RB
  57         ldc     r0, r6_bank
  58 #endif
  59
  60         /*
  61          * Prefetch if possible to reduce cache miss penalty.
  62          *
  63          * We do this early on for SH-4A as a micro-optimization,
  64          * as later on we will have speculative execution enabled
  65          * and this will become less of an issue.
  66          */
  67         PREFI(5f, r0)
  68         PREFI(6f, r0)
  69
  70         !
  71         mov.l   2f, r0
  72         mov     r0, r15         ! Set initial r15 (stack pointer)
  73         mov     #(THREAD_SIZE >> 8), r1
  74         shll8   r1              ! r1 = THREAD_SIZE
  75         sub     r1, r0          !
  76 #ifdef CONFIG_CPU_HAS_SR_RB
  77         ldc     r0, r7_bank     ! ... and initial thread_info
  78 #endif
  79
  80         !                       Clear BSS area
  81         mov.l   3f, r1
  82         add     #4, r1
  83         mov.l   4f, r2
  84         mov     #0, r0
  85 9:      cmp/hs  r2, r1
  86         bf/s    9b              ! while (r1 < r2)
  87          mov.l  r0,@-r2
  88
  89         !                       Additional CPU initialization
  90         mov.l   6f, r0
  91         jsr     @r0
  92          nop
  93
  94         SYNCO()                 ! Wait for pending instructions..
  95
  96         !                       Start kernel
  97         mov.l   5f, r0
  98         jmp     @r0
  99          nop
 100
 101         .balign 4
 102 #if defined(CONFIG_CPU_SH2)
 103 1:      .long   0x000000F0              ! IMASK=0xF
 104 #else
 105 1:      .long   0x400080F0              ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
 106 #endif
 107 2:      .long   init_thread_union+THREAD_SIZE
 108 3:      .long   __bss_start
 109 4:      .long   _end
 110 5:      .long   start_kernel
 111 6:      .long   sh_cpu_init