arch/sh/kernel/head_32.S

   1 /* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
   2  *
   3  *  arch/sh/kernel/head.S
   4  *
   5  *  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  *
  11  * Head.S contains the SH exception handlers and startup code.
  12  */
  13 #include <linux/linkage.h>
  14 #include <asm/thread_info.h>
  15
  16 #ifdef CONFIG_CPU_SH4A
  17 #define SYNCO()         synco
  18
  19 #define PREFI(label, reg)       \
  20         mov.l   label, reg;     \
  21         prefi   @reg
  22 #else
  23 #define SYNCO()
  24 #define PREFI(label, reg)
  25 #endif
  26
  27         .section        .empty_zero_page, "aw"
  28 ENTRY(empty_zero_page)
  29         .long   1               /* MOUNT_ROOT_RDONLY */
  30         .long   0               /* RAMDISK_FLAGS */
  31         .long   0x0200          /* ORIG_ROOT_DEV */
  32         .long   1               /* LOADER_TYPE */
  33         .long   0x00360000      /* INITRD_START */
  34         .long   0x000a0000      /* INITRD_SIZE */
  35         .long   0
  36 1:
  37         .skip   PAGE_SIZE - empty_zero_page - 1b
  38
  39         .section        .text.head, "ax"
  40
  41 /*
  42  * Condition at the entry of _stext:
  43  *
  44  *   BSC has already been initialized.
  45  *   INTC may or may not be initialized.
  46  *   VBR may or may not be initialized.
  47  *   MMU may or may not be initialized.
  48  *   Cache may or may not be initialized.
  49  *   Hardware (including on-chip modules) may or may not be initialized.
  50  *
  51  */
  52 ENTRY(_stext)
  53         !                       Initialize Status Register
  54         mov.l   1f, r0          ! MD=1, RB=0, BL=0, IMASK=0xF
  55         ldc     r0, sr
  56         !                       Initialize global interrupt mask
  57 #ifdef CONFIG_CPU_HAS_SR_RB
  58         mov     #0, r0
  59         ldc     r0, r6_bank
  60 #endif
  61
  62         /*
  63          * Prefetch if possible to reduce cache miss penalty.
  64          *
  65          * We do this early on for SH-4A as a micro-optimization,
  66          * as later on we will have speculative execution enabled
  67          * and this will become less of an issue.
  68          */
  69         PREFI(5f, r0)
  70         PREFI(6f, r0)
  71
  72         !
  73         mov.l   2f, r0
  74         mov     r0, r15         ! Set initial r15 (stack pointer)
  75 #ifdef CONFIG_CPU_HAS_SR_RB
  76         mov.l   7f, r0
  77         ldc     r0, r7_bank     ! ... and initial thread_info
  78 #endif
  79
  80         !                       Clear BSS area
  81 #ifdef CONFIG_SMP
  82         mov.l   3f, r0
  83         cmp/eq  #0, r0          ! skip clear if set to zero
  84         bt      10f
  85 #endif
  86
  87         mov.l   3f, r1
  88         add     #4, r1
  89         mov.l   4f, r2
  90         mov     #0, r0
  91 9:      cmp/hs  r2, r1
  92         bf/s    9b              ! while (r1 < r2)
  93          mov.l  r0,@-r2
  94
  95 10:
  96         !                       Additional CPU initialization
  97         mov.l   6f, r0
  98         jsr     @r0
  99          nop
 100
 101         SYNCO()                 ! Wait for pending instructions..
 102
 103         !                       Start kernel
 104         mov.l   5f, r0
 105         jmp     @r0
 106          nop
 107
 108         .balign 4
 109 #if defined(CONFIG_CPU_SH2)
 110 1:      .long   0x000000F0              ! IMASK=0xF
 111 #else
 112 1:      .long   0x400080F0              ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
 113 #endif
 114 ENTRY(stack_start)
 115 2:      .long   init_thread_union+THREAD_SIZE
 116 3:      .long   __bss_start
 117 4:      .long   _end
 118 5:      .long   start_kernel
 119 6:      .long   sh_cpu_init
 120 7:      .long   init_thread_union