arch/sh/kernel/head_32.S

   1 /* $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
   2  *
   3  *  arch/sh/kernel/head.S
   4  *
   5  *  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
   6  *  Copyright (C) 2010  Matt Fleming
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  *
  12  * Head.S contains the SH exception handlers and startup code.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/linkage.h>
  16 #include <asm/thread_info.h>
  17 #include <asm/mmu.h>
  18 #include <cpu/mmu_context.h>
  19
  20 #ifdef CONFIG_CPU_SH4A
  21 #define SYNCO()         synco
  22
  23 #define PREFI(label, reg)       \
  24         mov.l   label, reg;     \
  25         prefi   @reg
  26 #else
  27 #define SYNCO()
  28 #define PREFI(label, reg)
  29 #endif
  30
  31         .section        .empty_zero_page, "aw"
  32 ENTRY(empty_zero_page)
  33         .long   1               /* MOUNT_ROOT_RDONLY */
  34         .long   0               /* RAMDISK_FLAGS */
  35         .long   0x0200          /* ORIG_ROOT_DEV */
  36         .long   1               /* LOADER_TYPE */
  37         .long   0x00000000      /* INITRD_START */
  38         .long   0x00000000      /* INITRD_SIZE */
  39 #ifdef CONFIG_32BIT
  40         .long   0x53453f00 + 32 /* "SE?" = 32 bit */
  41 #else
  42         .long   0x53453f00 + 29 /* "SE?" = 29 bit */
  43 #endif
  44 1:
  45         .skip   PAGE_SIZE - empty_zero_page - 1b
  46
  47         __HEAD
  48
  49 /*
  50  * Condition at the entry of _stext:
  51  *
  52  *   BSC has already been initialized.
  53  *   INTC may or may not be initialized.
  54  *   VBR may or may not be initialized.
  55  *   MMU may or may not be initialized.
  56  *   Cache may or may not be initialized.
  57  *   Hardware (including on-chip modules) may or may not be initialized.
  58  *
  59  */
  60 ENTRY(_stext)
  61         !                       Initialize Status Register
  62         mov.l   1f, r0          ! MD=1, RB=0, BL=0, IMASK=0xF
  63         ldc     r0, sr
  64         !                       Initialize global interrupt mask
  65 #ifdef CONFIG_CPU_HAS_SR_RB
  66         mov     #0, r0
  67         ldc     r0, r6_bank
  68 #endif
  69
  70         /*
  71          * Prefetch if possible to reduce cache miss penalty.
  72          *
  73          * We do this early on for SH-4A as a micro-optimization,
  74          * as later on we will have speculative execution enabled
  75          * and this will become less of an issue.
  76          */
  77         PREFI(5f, r0)
  78         PREFI(6f, r0)
  79
  80         !
  81         mov.l   2f, r0
  82         mov     r0, r15         ! Set initial r15 (stack pointer)
  83 #ifdef CONFIG_CPU_HAS_SR_RB
  84         mov.l   7f, r0
  85         ldc     r0, r7_bank     ! ... and initial thread_info
  86 #endif
  87
  88 #if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
  89         /*
  90          * Reconfigure the initial PMB mappings setup by the hardware.
  91          *
  92          * When we boot in 32-bit MMU mode there are 2 PMB entries already
  93          * setup for us.
  94          *
  95          * Entry       VPN         PPN      V   SZ      C       UB      WT
  96          * ---------------------------------------------------------------
  97          *   0      0x80000000 0x00000000   1  512MB    1       0       1
  98          *   1      0xA0000000 0x00000000   1  512MB    0       0       0
  99          *
 100          * But we reprogram them here because we want complete control over
 101          * our address space and the initial mappings may not map PAGE_OFFSET
 102          * to __MEMORY_START (or even map all of our RAM).
 103          *
 104          * Once we've setup cached and uncached mappings for all of RAM we
 105          * clear the rest of the PMB entries.
 106          *
 107          * This clearing also deals with the fact that PMB entries can persist
 108          * across reboots. The PMB could have been left in any state when the
 109          * reboot occurred, so to be safe we clear all entries and start with
 110          * with a clean slate.
 111          */
 112
 113         mov.l   .LMMUCR, r1     /* Flush the TLB */
 114         mov.l   @r1, r0
 115         or      #MMUCR_TI, r0
 116         mov.l   r0, @r1
 117
 118         mov.l   .LMEMORY_SIZE, r5
 119         mov     r5, r7
 120
 121         mov     #PMB_E_SHIFT, r0
 122         mov     #0x1, r4
 123         shld    r0, r4
 124
 125         mov.l   .LFIRST_DATA_ENTRY, r0
 126         mov.l   .LPMB_DATA, r1
 127         mov.l   .LFIRST_ADDR_ENTRY, r2
 128         mov.l   .LPMB_ADDR, r3
 129
 130         mov     #0, r10
 131
 132         /*
 133          * r0 = PMB_DATA data field
 134          * r1 = PMB_DATA address field
 135          * r2 = PMB_ADDR data field
 136          * r3 = PMB_ADDR address field
 137          * r4 = PMB_E_SHIFT
 138          * r5 = remaining amount of RAM to map
 139          * r6 = PMB mapping size we're trying to use
 140          * r7 = cached_to_uncached
 141          * r8 = scratch register
 142          * r9 = scratch register
 143          * r10 = number of PMB entries we've setup
 144          */
 145 .L512:
 146         mov     #(512 >> 4), r6
 147         shll16  r6
 148         shll8   r6
 149
 150         cmp/hi  r5, r6
 151         bt      .L128
 152
 153         mov     #(PMB_SZ_512M >> 2), r9
 154         shll2   r9
 155
 156         /*
 157          * Cached mapping
 158          */
 159         mov     #PMB_C, r8
 160         or      r0, r8
 161         or      r9, r8
 162         mov.l   r8, @r1
 163         mov.l   r2, @r3
 164
 165         add     r4, r1          /* Increment to the next PMB_DATA entry */
 166         add     r4, r3          /* Increment to the next PMB_ADDR entry */
 167
 168         add     #1, r10         /* Increment number of PMB entries */
 169
 170         /*
 171          * Uncached mapping
 172          */
 173         mov     #(PMB_UB >> 8), r8
 174         shll8   r8
 175
 176         or      r0, r8
 177         or      r9, r8
 178         mov.l   r8, @r1
 179         mov     r2, r8
 180         add     r7, r8
 181         mov.l   r8, @r3
 182
 183         add     r4, r1          /* Increment to the next PMB_DATA entry */
 184         add     r4, r3          /* Increment to the next PMB_ADDR entry */
 185
 186         add     #1, r10         /* Increment number of PMB entries */
 187
 188         sub     r6, r5
 189         add     r6, r0
 190         add     r6, r2
 191
 192         bra     .L512
 193
 194 .L128:
 195         mov     #(128 >> 4), r6
 196         shll16  r6
 197         shll8   r6
 198
 199         cmp/hi  r5, r6
 200         bt      .L64
 201
 202         mov     #(PMB_SZ_128M >> 2), r9
 203         shll2   r9
 204
 205         /*
 206          * Cached mapping
 207          */
 208         mov     #PMB_C, r8
 209         or      r0, r8
 210         or      r9, r8
 211         mov.l   r8, @r1
 212         mov.l   r2, @r3
 213
 214         add     r4, r1          /* Increment to the next PMB_DATA entry */
 215         add     r4, r3          /* Increment to the next PMB_ADDR entry */
 216
 217         add     #1, r10         /* Increment number of PMB entries */
 218
 219         /*
 220          * Uncached mapping
 221          */
 222         mov     #(PMB_UB >> 8), r8
 223         shll8   r8
 224
 225         or      r0, r8
 226         or      r9, r8
 227         mov.l   r8, @r1
 228         mov     r2, r8
 229         add     r7, r8
 230         mov.l   r8, @r3
 231
 232         add     r4, r1          /* Increment to the next PMB_DATA entry */
 233         add     r4, r3          /* Increment to the next PMB_ADDR entry */
 234
 235         add     #1, r10         /* Increment number of PMB entries */
 236
 237         sub     r6, r5
 238         add     r6, r0
 239         add     r6, r2
 240
 241         bra     .L128
 242
 243 .L64:
 244         mov     #(64 >> 4), r6
 245         shll16  r6
 246         shll8   r6
 247
 248         cmp/hi  r5, r6
 249         bt      .Ldone
 250
 251         mov     #(PMB_SZ_64M >> 2), r9
 252         shll2   r9
 253
 254         /*
 255          * Cached mapping
 256          */
 257         mov     #PMB_C, r8
 258         or      r0, r8
 259         or      r9, r8
 260         mov.l   r8, @r1
 261         mov.l   r2, @r3
 262
 263         add     r4, r1          /* Increment to the next PMB_DATA entry */
 264         add     r4, r3          /* Increment to the next PMB_ADDR entry */
 265
 266         add     #1, r10         /* Increment number of PMB entries */
 267
 268         /*
 269          * Uncached mapping
 270          */
 271         mov     #(PMB_UB >> 8), r8
 272         shll8   r8
 273
 274         or      r0, r8
 275         or      r9, r8
 276         mov.l   r8, @r1
 277         mov     r2, r8
 278         add     r7, r8
 279         mov.l   r8, @r3
 280
 281         add     r4, r1          /* Increment to the next PMB_DATA entry */
 282         add     r4, r3          /* Increment to the next PMB_ADDR entry */
 283
 284         add     #1, r10         /* Increment number of PMB entries */
 285
 286         sub     r6, r5
 287         add     r6, r0
 288         add     r6, r2
 289
 290         bra     .L64
 291
 292 .Ldone:
 293         /* Update cached_to_uncached */
 294         mov.l   .Lcached_to_uncached, r0
 295         mov.l   r7, @r0
 296
 297         /*
 298          * Clear the remaining PMB entries.
 299          *
 300          * r3 = entry to begin clearing from
 301          * r10 = number of entries we've setup so far
 302          */
 303         mov     #0, r1
 304         mov     #PMB_ENTRY_MAX, r0
 305
 306 .Lagain:
 307         mov.l   r1, @r3         /* Clear PMB_ADDR entry */
 308         add     #1, r10         /* Increment the loop counter */
 309         cmp/eq  r0, r10
 310         bf/s    .Lagain
 311          add    r4, r3          /* Increment to the next PMB_ADDR entry */
 312
 313         mov.l   6f, r0
 314         icbi    @r0
 315
 316 #endif /* !CONFIG_PMB_LEGACY */
 317
 318 #ifndef CONFIG_SH_NO_BSS_INIT
 319         /*
 320          * Don't clear BSS if running on slow platforms such as an RTL simulation,
 321          * remote memory via SHdebug link, etc.  For these the memory can be guaranteed
 322          * to be all zero on boot anyway.
 323          */
 324                                 ! Clear BSS area
 325 #ifdef CONFIG_SMP
 326         mov.l   3f, r0
 327         cmp/eq  #0, r0          ! skip clear if set to zero
 328         bt      10f
 329 #endif
 330
 331         mov.l   3f, r1
 332         add     #4, r1
 333         mov.l   4f, r2
 334         mov     #0, r0
 335 9:      cmp/hs  r2, r1
 336         bf/s    9b              ! while (r1 < r2)
 337          mov.l  r0,@-r2
 338
 339 10:
 340 #endif
 341
 342         !                       Additional CPU initialization
 343         mov.l   6f, r0
 344         jsr     @r0
 345          nop
 346
 347         SYNCO()                 ! Wait for pending instructions..
 348
 349         !                       Start kernel
 350         mov.l   5f, r0
 351         jmp     @r0
 352          nop
 353
 354         .balign 4
 355 #if defined(CONFIG_CPU_SH2)
 356 1:      .long   0x000000F0              ! IMASK=0xF
 357 #else
 358 1:      .long   0x400080F0              ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
 359 #endif
 360 ENTRY(stack_start)
 361 2:      .long   init_thread_union+THREAD_SIZE
 362 3:      .long   __bss_start
 363 4:      .long   _end
 364 5:      .long   start_kernel
 365 6:      .long   sh_cpu_init
 366 7:      .long   init_thread_union
 367
 368 #if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
 369 .LPMB_ADDR:             .long   PMB_ADDR
 370 .LPMB_DATA:             .long   PMB_DATA
 371 .LFIRST_ADDR_ENTRY:     .long   PAGE_OFFSET | PMB_V
 372 .LFIRST_DATA_ENTRY:     .long   __MEMORY_START | PMB_V
 373 .LMMUCR:                .long   MMUCR
 374 .Lcached_to_uncached:   .long   cached_to_uncached
 375 .LMEMORY_SIZE:          .long   __MEMORY_SIZE
 376 #endif