2 * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
4 * Copyright (C) 2005 Paul Mundt
6 * Based off of arch/sh/kernel/timers/timer-tmu.c
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/seqlock.h>
16 #include <asm/timer.h>
19 #include <asm/clock.h>
22 * We use channel 1 for our lowly system timer. Channel 2 would be the other
23 * likely candidate, but we leave it alone as it has higher divisors that
24 * would be of more use to other more interesting applications.
26 * TODO: Presently we only implement a 16-bit single-channel system timer.
27 * However, we can implement channel cascade if we go the overflow route and
28 * get away with using 2 MTU2 channels as a 32-bit timer.
30 #define MTU2_TSTR 0xfffe4280
31 #define MTU2_TCR_1 0xfffe4380
32 #define MTU2_TMDR_1 0xfffe4381
33 #define MTU2_TIOR_1 0xfffe4382
34 #define MTU2_TIER_1 0xfffe4384
35 #define MTU2_TSR_1 0xfffe4385
36 #define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
37 #define MTU2_TGRA_1 0xfffe438a
39 #define STBCR3 0xfffe0408
41 #define MTU2_TSTR_CST1 (1 << 1) /* Counter Start 1 */
43 #define MTU2_TSR_TGFA (1 << 0) /* GRA compare match */
45 #define MTU2_TIER_TGIEA (1 << 0) /* GRA compare match interrupt enable */
47 #define MTU2_TCR_INIT 0x22
49 #define MTU2_TCR_CALIB 0x00
51 static unsigned long mtu2_timer_get_offset(void)
54 static int count_p
= 0x7fff; /* for the first call after boot */
55 static unsigned long jiffies_p
= 0;
58 * cache volatile jiffies temporarily; we have IRQs turned off.
60 unsigned long jiffies_t
;
62 /* timer count may underflow right here */
63 count
= ctrl_inw(MTU2_TCNT_1
); /* read the latched count */
68 * avoiding timer inconsistencies (they are rare, but they happen)...
69 * there is one kind of problem that must be avoided here:
70 * 1. the timer counter underflows
73 if (jiffies_t
== jiffies_p
) {
74 if (count
> count_p
) {
75 if (ctrl_inb(MTU2_TSR_1
) & MTU2_TSR_TGFA
) {
78 printk("%s (): hardware timer problem?\n",
83 jiffies_p
= jiffies_t
;
87 count
= ((LATCH
-1) - count
) * TICK_SIZE
;
88 count
= (count
+ LATCH
/2) / LATCH
;
93 static irqreturn_t
mtu2_timer_interrupt(int irq
, void *dev_id
)
95 unsigned long timer_status
;
98 timer_status
= ctrl_inb(MTU2_TSR_1
);
99 timer_status
&= ~MTU2_TSR_TGFA
;
100 ctrl_outb(timer_status
, MTU2_TSR_1
);
103 write_seqlock(&xtime_lock
);
105 write_sequnlock(&xtime_lock
);
110 static struct irqaction mtu2_irq
= {
112 .handler
= mtu2_timer_interrupt
,
113 .flags
= IRQF_DISABLED
| IRQF_TIMER
,
114 .mask
= CPU_MASK_NONE
,
117 static unsigned int divisors
[] = { 1, 4, 16, 64, 1, 1, 256 };
119 static void mtu2_clk_init(struct clk
*clk
)
121 u8 idx
= MTU2_TCR_INIT
& 0x7;
123 clk
->rate
= clk
->parent
->rate
/ divisors
[idx
];
124 /* Start TCNT counting */
125 ctrl_outb(ctrl_inb(MTU2_TSTR
) | MTU2_TSTR_CST1
, MTU2_TSTR
);
129 static void mtu2_clk_recalc(struct clk
*clk
)
131 u8 idx
= ctrl_inb(MTU2_TCR_1
) & 0x7;
132 clk
->rate
= clk
->parent
->rate
/ divisors
[idx
];
135 static struct clk_ops mtu2_clk_ops
= {
136 .init
= mtu2_clk_init
,
137 .recalc
= mtu2_clk_recalc
,
140 static struct clk mtu2_clk1
= {
142 .ops
= &mtu2_clk_ops
,
145 static int mtu2_timer_start(void)
147 ctrl_outb(ctrl_inb(MTU2_TSTR
) | MTU2_TSTR_CST1
, MTU2_TSTR
);
151 static int mtu2_timer_stop(void)
153 ctrl_outb(ctrl_inb(MTU2_TSTR
) & ~MTU2_TSTR_CST1
, MTU2_TSTR
);
157 static int mtu2_timer_init(void)
160 unsigned long interval
;
162 setup_irq(CONFIG_SH_TIMER_IRQ
, &mtu2_irq
);
164 mtu2_clk1
.parent
= clk_get(NULL
, "module_clk");
166 ctrl_outb(ctrl_inb(STBCR3
) & (~0x20), STBCR3
);
168 /* Normal operation */
169 ctrl_outb(0, MTU2_TMDR_1
);
170 ctrl_outb(MTU2_TCR_INIT
, MTU2_TCR_1
);
171 ctrl_outb(0x01, MTU2_TIOR_1
);
173 /* Enable underflow interrupt */
174 ctrl_outb(ctrl_inb(MTU2_TIER_1
) | MTU2_TIER_TGIEA
, MTU2_TIER_1
);
176 interval
= CONFIG_SH_PCLK_FREQ
/ 16 / HZ
;
177 printk(KERN_INFO
"Interval = %ld\n", interval
);
179 ctrl_outw(interval
, MTU2_TGRA_1
);
180 ctrl_outw(0, MTU2_TCNT_1
);
182 clk_register(&mtu2_clk1
);
183 clk_enable(&mtu2_clk1
);
188 struct sys_timer_ops mtu2_timer_ops
= {
189 .init
= mtu2_timer_init
,
190 .start
= mtu2_timer_start
,
191 .stop
= mtu2_timer_stop
,
192 #ifndef CONFIG_GENERIC_TIME
193 .get_offset
= mtu2_timer_get_offset
,
197 struct sys_timer mtu2_timer
= {
199 .ops
= &mtu2_timer_ops
,