1 /* pci.c: UltraSparc PCI controller support.
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
24 #include <asm/uaccess.h>
25 #include <asm/pgtable.h>
32 /* List of all PCI controllers found in the system. */
33 struct pci_pbm_info
*pci_pbm_root
= NULL
;
35 /* Each PBM found gets a unique index. */
38 volatile int pci_poke_in_progress
;
39 volatile int pci_poke_cpu
= -1;
40 volatile int pci_poke_faulted
;
42 static DEFINE_SPINLOCK(pci_poke_lock
);
44 void pci_config_read8(u8
*addr
, u8
*ret
)
49 spin_lock_irqsave(&pci_poke_lock
, flags
);
50 pci_poke_cpu
= smp_processor_id();
51 pci_poke_in_progress
= 1;
53 __asm__
__volatile__("membar #Sync\n\t"
54 "lduba [%1] %2, %0\n\t"
57 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
59 pci_poke_in_progress
= 0;
61 if (!pci_poke_faulted
)
63 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
66 void pci_config_read16(u16
*addr
, u16
*ret
)
71 spin_lock_irqsave(&pci_poke_lock
, flags
);
72 pci_poke_cpu
= smp_processor_id();
73 pci_poke_in_progress
= 1;
75 __asm__
__volatile__("membar #Sync\n\t"
76 "lduha [%1] %2, %0\n\t"
79 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
81 pci_poke_in_progress
= 0;
83 if (!pci_poke_faulted
)
85 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
88 void pci_config_read32(u32
*addr
, u32
*ret
)
93 spin_lock_irqsave(&pci_poke_lock
, flags
);
94 pci_poke_cpu
= smp_processor_id();
95 pci_poke_in_progress
= 1;
97 __asm__
__volatile__("membar #Sync\n\t"
98 "lduwa [%1] %2, %0\n\t"
101 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
103 pci_poke_in_progress
= 0;
105 if (!pci_poke_faulted
)
107 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
110 void pci_config_write8(u8
*addr
, u8 val
)
114 spin_lock_irqsave(&pci_poke_lock
, flags
);
115 pci_poke_cpu
= smp_processor_id();
116 pci_poke_in_progress
= 1;
117 pci_poke_faulted
= 0;
118 __asm__
__volatile__("membar #Sync\n\t"
119 "stba %0, [%1] %2\n\t"
122 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
124 pci_poke_in_progress
= 0;
126 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
129 void pci_config_write16(u16
*addr
, u16 val
)
133 spin_lock_irqsave(&pci_poke_lock
, flags
);
134 pci_poke_cpu
= smp_processor_id();
135 pci_poke_in_progress
= 1;
136 pci_poke_faulted
= 0;
137 __asm__
__volatile__("membar #Sync\n\t"
138 "stha %0, [%1] %2\n\t"
141 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
143 pci_poke_in_progress
= 0;
145 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
148 void pci_config_write32(u32
*addr
, u32 val
)
152 spin_lock_irqsave(&pci_poke_lock
, flags
);
153 pci_poke_cpu
= smp_processor_id();
154 pci_poke_in_progress
= 1;
155 pci_poke_faulted
= 0;
156 __asm__
__volatile__("membar #Sync\n\t"
157 "stwa %0, [%1] %2\n\t"
160 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
162 pci_poke_in_progress
= 0;
164 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
167 static int ofpci_verbose
;
169 static int __init
ofpci_debug(char *str
)
173 get_option(&str
, &val
);
179 __setup("ofpci_debug=", ofpci_debug
);
181 static unsigned long pci_parse_of_flags(u32 addr0
)
183 unsigned long flags
= 0;
185 if (addr0
& 0x02000000) {
186 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
187 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
188 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
189 if (addr0
& 0x40000000)
190 flags
|= IORESOURCE_PREFETCH
191 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
192 } else if (addr0
& 0x01000000)
193 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
197 /* The of_device layer has translated all of the assigned-address properties
198 * into physical address resources, we only have to figure out the register
201 static void pci_parse_of_addrs(struct of_device
*op
,
202 struct device_node
*node
,
205 struct resource
*op_res
;
209 addrs
= of_get_property(node
, "assigned-addresses", &proplen
);
213 printk(" parse addresses (%d bytes) @ %p\n",
215 op_res
= &op
->resource
[0];
216 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5, op_res
++) {
217 struct resource
*res
;
221 flags
= pci_parse_of_flags(addrs
[0]);
226 printk(" start: %llx, end: %llx, i: %x\n",
227 op_res
->start
, op_res
->end
, i
);
229 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
230 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
231 } else if (i
== dev
->rom_base_reg
) {
232 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
233 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
235 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
238 res
->start
= op_res
->start
;
239 res
->end
= op_res
->end
;
241 res
->name
= pci_name(dev
);
245 static struct pci_dev
*of_create_pci_dev(struct pci_pbm_info
*pbm
,
246 struct device_node
*node
,
247 struct pci_bus
*bus
, int devfn
)
249 struct dev_archdata
*sd
;
250 struct pci_slot
*slot
;
251 struct of_device
*op
;
256 dev
= alloc_pci_dev();
260 sd
= &dev
->dev
.archdata
;
261 sd
->iommu
= pbm
->iommu
;
263 sd
->host_controller
= pbm
;
264 sd
->prom_node
= node
;
265 dev
->dev
.of_node
= node
;
266 sd
->op
= op
= of_find_device_by_node(node
);
267 sd
->numa_node
= pbm
->numa_node
;
269 sd
= &op
->dev
.archdata
;
270 sd
->iommu
= pbm
->iommu
;
272 sd
->numa_node
= pbm
->numa_node
;
274 if (!strcmp(node
->name
, "ebus"))
275 of_propagate_archdata(op
);
277 type
= of_get_property(node
, "device_type", NULL
);
282 printk(" create device, devfn: %x, type: %s\n",
287 dev
->dev
.parent
= bus
->bridge
;
288 dev
->dev
.bus
= &pci_bus_type
;
290 dev
->multifunction
= 0; /* maybe a lie? */
291 set_pcie_port_type(dev
);
293 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
294 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
297 dev
->vendor
= of_getintprop_default(node
, "vendor-id", 0xffff);
298 dev
->device
= of_getintprop_default(node
, "device-id", 0xffff);
299 dev
->subsystem_vendor
=
300 of_getintprop_default(node
, "subsystem-vendor-id", 0);
301 dev
->subsystem_device
=
302 of_getintprop_default(node
, "subsystem-id", 0);
304 dev
->cfg_size
= pci_cfg_space_size(dev
);
306 /* We can't actually use the firmware value, we have
307 * to read what is in the register right now. One
308 * reason is that in the case of IDE interfaces the
309 * firmware can sample the value before the the IDE
310 * interface is programmed into native mode.
312 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
313 dev
->class = class >> 8;
314 dev
->revision
= class & 0xff;
316 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
317 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
320 printk(" class: 0x%x device name: %s\n",
321 dev
->class, pci_name(dev
));
323 /* I have seen IDE devices which will not respond to
324 * the bmdma simplex check reads if bus mastering is
327 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
330 dev
->current_state
= 4; /* unknown power state */
331 dev
->error_state
= pci_channel_io_normal
;
332 dev
->dma_mask
= 0xffffffff;
334 if (!strcmp(node
->name
, "pci")) {
335 /* a PCI-PCI bridge */
336 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
337 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
338 } else if (!strcmp(type
, "cardbus")) {
339 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
341 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
342 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
344 dev
->irq
= sd
->op
->irqs
[0];
345 if (dev
->irq
== 0xffffffff)
346 dev
->irq
= PCI_IRQ_NONE
;
349 pci_parse_of_addrs(sd
->op
, node
, dev
);
352 printk(" adding to system ...\n");
354 pci_device_add(dev
, bus
);
359 static void __devinit
apb_calc_first_last(u8 map
, u32
*first_p
, u32
*last_p
)
361 u32 idx
, first
, last
;
365 for (idx
= 0; idx
< 8; idx
++) {
366 if ((map
& (1 << idx
)) != 0) {
378 static void pci_resource_adjust(struct resource
*res
,
379 struct resource
*root
)
381 res
->start
+= root
->start
;
382 res
->end
+= root
->start
;
385 /* For PCI bus devices which lack a 'ranges' property we interrogate
386 * the config space values to set the resources, just like the generic
387 * Linux PCI probing code does.
389 static void __devinit
pci_cfg_fake_ranges(struct pci_dev
*dev
,
391 struct pci_pbm_info
*pbm
)
393 struct resource
*res
;
394 u8 io_base_lo
, io_limit_lo
;
395 u16 mem_base_lo
, mem_limit_lo
;
396 unsigned long base
, limit
;
398 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
399 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
400 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
401 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
403 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
404 u16 io_base_hi
, io_limit_hi
;
406 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
407 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
408 base
|= (io_base_hi
<< 16);
409 limit
|= (io_limit_hi
<< 16);
412 res
= bus
->resource
[0];
414 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
418 res
->end
= limit
+ 0xfff;
419 pci_resource_adjust(res
, &pbm
->io_space
);
422 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
423 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
424 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
425 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
427 res
= bus
->resource
[1];
429 res
->flags
= ((mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) |
432 res
->end
= limit
+ 0xfffff;
433 pci_resource_adjust(res
, &pbm
->mem_space
);
436 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
437 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
438 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
439 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
441 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
442 u32 mem_base_hi
, mem_limit_hi
;
444 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
445 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
448 * Some bridges set the base > limit by default, and some
449 * (broken) BIOSes do not initialize them. If we find
450 * this, just assume they are not being used.
452 if (mem_base_hi
<= mem_limit_hi
) {
453 base
|= ((long) mem_base_hi
) << 32;
454 limit
|= ((long) mem_limit_hi
) << 32;
458 res
= bus
->resource
[2];
460 res
->flags
= ((mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) |
461 IORESOURCE_MEM
| IORESOURCE_PREFETCH
);
463 res
->end
= limit
+ 0xfffff;
464 pci_resource_adjust(res
, &pbm
->mem_space
);
468 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
469 * a proper 'ranges' property.
471 static void __devinit
apb_fake_ranges(struct pci_dev
*dev
,
473 struct pci_pbm_info
*pbm
)
475 struct resource
*res
;
479 pci_read_config_byte(dev
, APB_IO_ADDRESS_MAP
, &map
);
480 apb_calc_first_last(map
, &first
, &last
);
481 res
= bus
->resource
[0];
482 res
->start
= (first
<< 21);
483 res
->end
= (last
<< 21) + ((1 << 21) - 1);
484 res
->flags
= IORESOURCE_IO
;
485 pci_resource_adjust(res
, &pbm
->io_space
);
487 pci_read_config_byte(dev
, APB_MEM_ADDRESS_MAP
, &map
);
488 apb_calc_first_last(map
, &first
, &last
);
489 res
= bus
->resource
[1];
490 res
->start
= (first
<< 21);
491 res
->end
= (last
<< 21) + ((1 << 21) - 1);
492 res
->flags
= IORESOURCE_MEM
;
493 pci_resource_adjust(res
, &pbm
->mem_space
);
496 static void __devinit
pci_of_scan_bus(struct pci_pbm_info
*pbm
,
497 struct device_node
*node
,
498 struct pci_bus
*bus
);
500 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
502 static void __devinit
of_scan_pci_bridge(struct pci_pbm_info
*pbm
,
503 struct device_node
*node
,
507 const u32
*busrange
, *ranges
;
509 struct resource
*res
;
514 printk("of_scan_pci_bridge(%s)\n", node
->full_name
);
516 /* parse bus-range property */
517 busrange
= of_get_property(node
, "bus-range", &len
);
518 if (busrange
== NULL
|| len
!= 8) {
519 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
523 ranges
= of_get_property(node
, "ranges", &len
);
525 if (ranges
== NULL
) {
526 const char *model
= of_get_property(node
, "model", NULL
);
527 if (model
&& !strcmp(model
, "SUNW,simba"))
531 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
533 printk(KERN_ERR
"Failed to create pci bus for %s\n",
538 bus
->primary
= dev
->bus
->number
;
539 bus
->subordinate
= busrange
[1];
542 /* parse ranges property, or cook one up by hand for Simba */
543 /* PCI #address-cells == 3 and #size-cells == 2 always */
544 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
545 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
547 bus
->resource
[i
] = res
;
551 apb_fake_ranges(dev
, bus
, pbm
);
553 } else if (ranges
== NULL
) {
554 pci_cfg_fake_ranges(dev
, bus
, pbm
);
558 for (; len
>= 32; len
-= 32, ranges
+= 8) {
559 struct resource
*root
;
561 flags
= pci_parse_of_flags(ranges
[0]);
562 size
= GET_64BIT(ranges
, 6);
563 if (flags
== 0 || size
== 0)
565 if (flags
& IORESOURCE_IO
) {
566 res
= bus
->resource
[0];
568 printk(KERN_ERR
"PCI: ignoring extra I/O range"
569 " for bridge %s\n", node
->full_name
);
572 root
= &pbm
->io_space
;
574 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
575 printk(KERN_ERR
"PCI: too many memory ranges"
576 " for bridge %s\n", node
->full_name
);
579 res
= bus
->resource
[i
];
581 root
= &pbm
->mem_space
;
584 res
->start
= GET_64BIT(ranges
, 1);
585 res
->end
= res
->start
+ size
- 1;
588 /* Another way to implement this would be to add an of_device
589 * layer routine that can calculate a resource for a given
590 * range property value in a PCI device.
592 pci_resource_adjust(res
, root
);
595 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
598 printk(" bus name: %s\n", bus
->name
);
600 pci_of_scan_bus(pbm
, node
, bus
);
603 static void __devinit
pci_of_scan_bus(struct pci_pbm_info
*pbm
,
604 struct device_node
*node
,
607 struct device_node
*child
;
609 int reglen
, devfn
, prev_devfn
;
613 printk("PCI: scan_bus[%s] bus no %d\n",
614 node
->full_name
, bus
->number
);
618 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
620 printk(" * %s\n", child
->full_name
);
621 reg
= of_get_property(child
, "reg", ®len
);
622 if (reg
== NULL
|| reglen
< 20)
625 devfn
= (reg
[0] >> 8) & 0xff;
627 /* This is a workaround for some device trees
628 * which list PCI devices twice. On the V100
629 * for example, device number 3 is listed twice.
630 * Once as "pm" and once again as "lomp".
632 if (devfn
== prev_devfn
)
636 /* create a new pci_dev for this device */
637 dev
= of_create_pci_dev(pbm
, child
, bus
, devfn
);
641 printk("PCI: dev header type: %x\n",
644 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
645 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
646 of_scan_pci_bridge(pbm
, child
, dev
);
651 show_pciobppath_attr(struct device
* dev
, struct device_attribute
* attr
, char * buf
)
653 struct pci_dev
*pdev
;
654 struct device_node
*dp
;
656 pdev
= to_pci_dev(dev
);
657 dp
= pdev
->dev
.archdata
.prom_node
;
659 return snprintf (buf
, PAGE_SIZE
, "%s\n", dp
->full_name
);
662 static DEVICE_ATTR(obppath
, S_IRUSR
| S_IRGRP
| S_IROTH
, show_pciobppath_attr
, NULL
);
664 static void __devinit
pci_bus_register_of_sysfs(struct pci_bus
*bus
)
667 struct pci_bus
*child_bus
;
670 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
671 /* we don't really care if we can create this file or
672 * not, but we need to assign the result of the call
673 * or the world will fall under alien invasion and
674 * everybody will be frozen on a spaceship ready to be
675 * eaten on alpha centauri by some green and jelly
678 err
= sysfs_create_file(&dev
->dev
.kobj
, &dev_attr_obppath
.attr
);
680 list_for_each_entry(child_bus
, &bus
->children
, node
)
681 pci_bus_register_of_sysfs(child_bus
);
684 struct pci_bus
* __devinit
pci_scan_one_pbm(struct pci_pbm_info
*pbm
,
685 struct device
*parent
)
687 struct device_node
*node
= pbm
->op
->node
;
690 printk("PCI: Scanning PBM %s\n", node
->full_name
);
692 bus
= pci_create_bus(parent
, pbm
->pci_first_busno
, pbm
->pci_ops
, pbm
);
694 printk(KERN_ERR
"Failed to create bus for %s\n",
698 bus
->secondary
= pbm
->pci_first_busno
;
699 bus
->subordinate
= pbm
->pci_last_busno
;
701 bus
->resource
[0] = &pbm
->io_space
;
702 bus
->resource
[1] = &pbm
->mem_space
;
704 pci_of_scan_bus(pbm
, node
, bus
);
705 pci_bus_add_devices(bus
);
706 pci_bus_register_of_sysfs(bus
);
711 void __devinit
pcibios_fixup_bus(struct pci_bus
*pbus
)
713 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
715 /* Generic PCI bus probing sets these to point at
716 * &io{port,mem}_resouce which is wrong for us.
718 pbus
->resource
[0] = &pbm
->io_space
;
719 pbus
->resource
[1] = &pbm
->mem_space
;
722 void pcibios_update_irq(struct pci_dev
*pdev
, int irq
)
726 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
727 resource_size_t size
, resource_size_t align
)
732 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
737 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
740 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
741 struct resource
*res
= &dev
->resource
[i
];
743 /* Only set up the requested stuff */
744 if (!(mask
& (1<<i
)))
747 if (res
->flags
& IORESOURCE_IO
)
748 cmd
|= PCI_COMMAND_IO
;
749 if (res
->flags
& IORESOURCE_MEM
)
750 cmd
|= PCI_COMMAND_MEMORY
;
754 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
756 /* Enable the appropriate bits in the PCI command register. */
757 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
762 void pcibios_resource_to_bus(struct pci_dev
*pdev
, struct pci_bus_region
*region
,
763 struct resource
*res
)
765 struct pci_pbm_info
*pbm
= pdev
->bus
->sysdata
;
766 struct resource zero_res
, *root
;
770 zero_res
.flags
= res
->flags
;
772 if (res
->flags
& IORESOURCE_IO
)
773 root
= &pbm
->io_space
;
775 root
= &pbm
->mem_space
;
777 pci_resource_adjust(&zero_res
, root
);
779 region
->start
= res
->start
- zero_res
.start
;
780 region
->end
= res
->end
- zero_res
.start
;
782 EXPORT_SYMBOL(pcibios_resource_to_bus
);
784 void pcibios_bus_to_resource(struct pci_dev
*pdev
, struct resource
*res
,
785 struct pci_bus_region
*region
)
787 struct pci_pbm_info
*pbm
= pdev
->bus
->sysdata
;
788 struct resource
*root
;
790 res
->start
= region
->start
;
791 res
->end
= region
->end
;
793 if (res
->flags
& IORESOURCE_IO
)
794 root
= &pbm
->io_space
;
796 root
= &pbm
->mem_space
;
798 pci_resource_adjust(res
, root
);
800 EXPORT_SYMBOL(pcibios_bus_to_resource
);
802 char * __devinit
pcibios_setup(char *str
)
807 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
809 /* If the user uses a host-bridge as the PCI device, he may use
810 * this to perform a raw mmap() of the I/O or MEM space behind
813 * This can be useful for execution of x86 PCI bios initialization code
814 * on a PCI card, like the xfree86 int10 stuff does.
816 static int __pci_mmap_make_offset_bus(struct pci_dev
*pdev
, struct vm_area_struct
*vma
,
817 enum pci_mmap_state mmap_state
)
819 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
820 unsigned long space_size
, user_offset
, user_size
;
822 if (mmap_state
== pci_mmap_io
) {
823 space_size
= (pbm
->io_space
.end
-
824 pbm
->io_space
.start
) + 1;
826 space_size
= (pbm
->mem_space
.end
-
827 pbm
->mem_space
.start
) + 1;
830 /* Make sure the request is in range. */
831 user_offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
832 user_size
= vma
->vm_end
- vma
->vm_start
;
834 if (user_offset
>= space_size
||
835 (user_offset
+ user_size
) > space_size
)
838 if (mmap_state
== pci_mmap_io
) {
839 vma
->vm_pgoff
= (pbm
->io_space
.start
+
840 user_offset
) >> PAGE_SHIFT
;
842 vma
->vm_pgoff
= (pbm
->mem_space
.start
+
843 user_offset
) >> PAGE_SHIFT
;
849 /* Adjust vm_pgoff of VMA such that it is the physical page offset
850 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
852 * Basically, the user finds the base address for his device which he wishes
853 * to mmap. They read the 32-bit value from the config space base register,
854 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
855 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
857 * Returns negative error code on failure, zero on success.
859 static int __pci_mmap_make_offset(struct pci_dev
*pdev
,
860 struct vm_area_struct
*vma
,
861 enum pci_mmap_state mmap_state
)
863 unsigned long user_paddr
, user_size
;
866 /* First compute the physical address in vma->vm_pgoff,
867 * making sure the user offset is within range in the
868 * appropriate PCI space.
870 err
= __pci_mmap_make_offset_bus(pdev
, vma
, mmap_state
);
874 /* If this is a mapping on a host bridge, any address
877 if ((pdev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
)
880 /* Otherwise make sure it's in the range for one of the
881 * device's resources.
883 user_paddr
= vma
->vm_pgoff
<< PAGE_SHIFT
;
884 user_size
= vma
->vm_end
- vma
->vm_start
;
886 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
887 struct resource
*rp
= &pdev
->resource
[i
];
888 resource_size_t aligned_end
;
895 if (i
== PCI_ROM_RESOURCE
) {
896 if (mmap_state
!= pci_mmap_mem
)
899 if ((mmap_state
== pci_mmap_io
&&
900 (rp
->flags
& IORESOURCE_IO
) == 0) ||
901 (mmap_state
== pci_mmap_mem
&&
902 (rp
->flags
& IORESOURCE_MEM
) == 0))
906 /* Align the resource end to the next page address.
907 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
908 * because actually we need the address of the next byte
911 aligned_end
= (rp
->end
+ PAGE_SIZE
) & PAGE_MASK
;
913 if ((rp
->start
<= user_paddr
) &&
914 (user_paddr
+ user_size
) <= aligned_end
)
918 if (i
> PCI_ROM_RESOURCE
)
924 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
927 static void __pci_mmap_set_flags(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
928 enum pci_mmap_state mmap_state
)
930 vma
->vm_flags
|= (VM_IO
| VM_RESERVED
);
933 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
936 static void __pci_mmap_set_pgprot(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
937 enum pci_mmap_state mmap_state
)
939 /* Our io_remap_pfn_range takes care of this, do nothing. */
942 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
943 * for this architecture. The region in the process to map is described by vm_start
944 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
945 * The pci device structure is provided so that architectures may make mapping
946 * decisions on a per-device or per-bus basis.
948 * Returns a negative error code on failure, zero on success.
950 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
951 enum pci_mmap_state mmap_state
,
956 ret
= __pci_mmap_make_offset(dev
, vma
, mmap_state
);
960 __pci_mmap_set_flags(dev
, vma
, mmap_state
);
961 __pci_mmap_set_pgprot(dev
, vma
, mmap_state
);
963 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
964 ret
= io_remap_pfn_range(vma
, vma
->vm_start
,
966 vma
->vm_end
- vma
->vm_start
,
975 int pcibus_to_node(struct pci_bus
*pbus
)
977 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
979 return pbm
->numa_node
;
981 EXPORT_SYMBOL(pcibus_to_node
);
984 /* Return the domain number for this pci bus */
986 int pci_domain_nr(struct pci_bus
*pbus
)
988 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
999 EXPORT_SYMBOL(pci_domain_nr
);
1001 #ifdef CONFIG_PCI_MSI
1002 int arch_setup_msi_irq(struct pci_dev
*pdev
, struct msi_desc
*desc
)
1004 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1005 unsigned int virt_irq
;
1007 if (!pbm
->setup_msi_irq
)
1010 return pbm
->setup_msi_irq(&virt_irq
, pdev
, desc
);
1013 void arch_teardown_msi_irq(unsigned int virt_irq
)
1015 struct msi_desc
*entry
= get_irq_msi(virt_irq
);
1016 struct pci_dev
*pdev
= entry
->dev
;
1017 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1019 if (pbm
->teardown_msi_irq
)
1020 pbm
->teardown_msi_irq(virt_irq
, pdev
);
1022 #endif /* !(CONFIG_PCI_MSI) */
1024 struct device_node
*pci_device_to_OF_node(struct pci_dev
*pdev
)
1026 return pdev
->dev
.archdata
.prom_node
;
1028 EXPORT_SYMBOL(pci_device_to_OF_node
);
1030 static void ali_sound_dma_hack(struct pci_dev
*pdev
, int set_bit
)
1032 struct pci_dev
*ali_isa_bridge
;
1035 /* ALI sound chips generate 31-bits of DMA, a special register
1036 * determines what bit 31 is emitted as.
1038 ali_isa_bridge
= pci_get_device(PCI_VENDOR_ID_AL
,
1039 PCI_DEVICE_ID_AL_M1533
,
1042 pci_read_config_byte(ali_isa_bridge
, 0x7e, &val
);
1047 pci_write_config_byte(ali_isa_bridge
, 0x7e, val
);
1048 pci_dev_put(ali_isa_bridge
);
1051 int pci64_dma_supported(struct pci_dev
*pdev
, u64 device_mask
)
1056 dma_addr_mask
= 0xffffffff;
1058 struct iommu
*iommu
= pdev
->dev
.archdata
.iommu
;
1060 dma_addr_mask
= iommu
->dma_addr_mask
;
1062 if (pdev
->vendor
== PCI_VENDOR_ID_AL
&&
1063 pdev
->device
== PCI_DEVICE_ID_AL_M5451
&&
1064 device_mask
== 0x7fffffff) {
1065 ali_sound_dma_hack(pdev
,
1066 (dma_addr_mask
& 0x80000000) != 0);
1071 if (device_mask
>= (1UL << 32UL))
1074 return (device_mask
& dma_addr_mask
) == dma_addr_mask
;
1077 void pci_resource_to_user(const struct pci_dev
*pdev
, int bar
,
1078 const struct resource
*rp
, resource_size_t
*start
,
1079 resource_size_t
*end
)
1081 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1082 unsigned long offset
;
1084 if (rp
->flags
& IORESOURCE_IO
)
1085 offset
= pbm
->io_space
.start
;
1087 offset
= pbm
->mem_space
.start
;
1089 *start
= rp
->start
- offset
;
1090 *end
= rp
->end
- offset
;
1093 static int __init
pcibios_init(void)
1095 pci_dfl_cache_line_size
= 64 >> 2;
1098 subsys_initcall(pcibios_init
);
1101 static void __devinit
pci_bus_slot_names(struct device_node
*node
,
1102 struct pci_bus
*bus
)
1104 const struct pci_slot_names
{
1112 prop
= of_get_property(node
, "slot-names", &len
);
1116 mask
= prop
->slot_mask
;
1120 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
1121 node
->full_name
, mask
);
1125 struct pci_slot
*pci_slot
;
1126 u32 this_bit
= 1 << i
;
1128 if (!(mask
& this_bit
)) {
1134 printk("PCI: Making slot [%s]\n", sp
);
1136 pci_slot
= pci_create_slot(bus
, i
, sp
, NULL
);
1137 if (IS_ERR(pci_slot
))
1138 printk(KERN_ERR
"PCI: pci_create_slot returned %ld\n",
1141 sp
+= strlen(sp
) + 1;
1147 static int __init
of_pci_slot_init(void)
1149 struct pci_bus
*pbus
= NULL
;
1151 while ((pbus
= pci_find_next_bus(pbus
)) != NULL
) {
1152 struct device_node
*node
;
1155 struct dev_archdata
*sd
= pbus
->self
->sysdata
;
1157 /* PCI->PCI bridge */
1158 node
= sd
->prom_node
;
1160 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
1162 /* Host PCI controller */
1163 node
= pbm
->op
->node
;
1166 pci_bus_slot_names(node
, pbus
);
1172 module_init(of_pci_slot_init
);