1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/export.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/bootmem.h>
24 #include <linux/vmalloc.h>
25 #include <linux/ftrace.h>
26 #include <linux/cpu.h>
27 #include <linux/slab.h>
30 #include <asm/ptrace.h>
31 #include <linux/atomic.h>
32 #include <asm/tlbflush.h>
33 #include <asm/mmu_context.h>
34 #include <asm/cpudata.h>
35 #include <asm/hvtramp.h>
37 #include <asm/timer.h>
40 #include <asm/irq_regs.h>
42 #include <asm/pgtable.h>
43 #include <asm/oplib.h>
44 #include <asm/uaccess.h>
45 #include <asm/starfire.h>
47 #include <asm/sections.h>
49 #include <asm/mdesc.h>
51 #include <asm/hypervisor.h>
56 int sparc64_multi_core __read_mostly
;
58 DEFINE_PER_CPU(cpumask_t
, cpu_sibling_map
) = CPU_MASK_NONE
;
59 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
=
60 { [0 ... NR_CPUS
-1] = CPU_MASK_NONE
};
62 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
63 EXPORT_SYMBOL(cpu_core_map
);
65 static cpumask_t smp_commenced_mask
;
67 void smp_info(struct seq_file
*m
)
71 seq_printf(m
, "State:\n");
72 for_each_online_cpu(i
)
73 seq_printf(m
, "CPU%d:\t\tonline\n", i
);
76 void smp_bogo(struct seq_file
*m
)
80 for_each_online_cpu(i
)
82 "Cpu%dClkTck\t: %016lx\n",
83 i
, cpu_data(i
).clock_tick
);
86 extern void setup_sparc64_timer(void);
88 static volatile unsigned long callin_flag
= 0;
90 void __cpuinit
smp_callin(void)
92 int cpuid
= hard_smp_processor_id();
94 __local_per_cpu_offset
= __per_cpu_offset(cpuid
);
96 if (tlb_type
== hypervisor
)
97 sun4v_ktsb_register();
101 setup_sparc64_timer();
103 if (cheetah_pcache_forced_on
)
104 cheetah_enable_pcache();
109 __asm__
__volatile__("membar #Sync\n\t"
110 "flush %%g6" : : : "memory");
112 /* Clear this or we will die instantly when we
113 * schedule back to this idler...
115 current_thread_info()->new_child
= 0;
117 /* Attach to the address space of init_task. */
118 atomic_inc(&init_mm
.mm_count
);
119 current
->active_mm
= &init_mm
;
121 /* inform the notifiers about the new cpu */
122 notify_cpu_starting(cpuid
);
124 while (!cpumask_test_cpu(cpuid
, &smp_commenced_mask
))
128 set_cpu_online(cpuid
, true);
129 ipi_call_unlock_irq();
131 /* idle thread is expected to have preempt disabled */
137 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
138 panic("SMP bolixed\n");
141 /* This tick register synchronization scheme is taken entirely from
142 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
144 * The only change I've made is to rework it so that the master
145 * initiates the synchonization instead of the slave. -DaveM
149 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
151 #define NUM_ROUNDS 64 /* magic value */
152 #define NUM_ITERS 5 /* likewise */
154 static DEFINE_SPINLOCK(itc_sync_lock
);
155 static unsigned long go
[SLAVE
+ 1];
157 #define DEBUG_TICK_SYNC 0
159 static inline long get_delta (long *rt
, long *master
)
161 unsigned long best_t0
= 0, best_t1
= ~0UL, best_tm
= 0;
162 unsigned long tcenter
, t0
, t1
, tm
;
165 for (i
= 0; i
< NUM_ITERS
; i
++) {
166 t0
= tick_ops
->get_tick();
168 membar_safe("#StoreLoad");
169 while (!(tm
= go
[SLAVE
]))
173 t1
= tick_ops
->get_tick();
175 if (t1
- t0
< best_t1
- best_t0
)
176 best_t0
= t0
, best_t1
= t1
, best_tm
= tm
;
179 *rt
= best_t1
- best_t0
;
180 *master
= best_tm
- best_t0
;
182 /* average best_t0 and best_t1 without overflow: */
183 tcenter
= (best_t0
/2 + best_t1
/2);
184 if (best_t0
% 2 + best_t1
% 2 == 2)
186 return tcenter
- best_tm
;
189 void smp_synchronize_tick_client(void)
191 long i
, delta
, adj
, adjust_latency
= 0, done
= 0;
192 unsigned long flags
, rt
, master_time_stamp
;
195 long rt
; /* roundtrip time */
196 long master
; /* master's timestamp */
197 long diff
; /* difference between midpoint and master's timestamp */
198 long lat
; /* estimate of itc adjustment latency */
207 local_irq_save(flags
);
209 for (i
= 0; i
< NUM_ROUNDS
; i
++) {
210 delta
= get_delta(&rt
, &master_time_stamp
);
212 done
= 1; /* let's lock on to this... */
216 adjust_latency
+= -delta
;
217 adj
= -delta
+ adjust_latency
/4;
221 tick_ops
->add_tick(adj
);
225 t
[i
].master
= master_time_stamp
;
227 t
[i
].lat
= adjust_latency
/4;
231 local_irq_restore(flags
);
234 for (i
= 0; i
< NUM_ROUNDS
; i
++)
235 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
236 t
[i
].rt
, t
[i
].master
, t
[i
].diff
, t
[i
].lat
);
239 printk(KERN_INFO
"CPU %d: synchronized TICK with master CPU "
240 "(last diff %ld cycles, maxerr %lu cycles)\n",
241 smp_processor_id(), delta
, rt
);
244 static void smp_start_sync_tick_client(int cpu
);
246 static void smp_synchronize_one_tick(int cpu
)
248 unsigned long flags
, i
;
252 smp_start_sync_tick_client(cpu
);
254 /* wait for client to be ready */
258 /* now let the client proceed into his loop */
260 membar_safe("#StoreLoad");
262 spin_lock_irqsave(&itc_sync_lock
, flags
);
264 for (i
= 0; i
< NUM_ROUNDS
*NUM_ITERS
; i
++) {
269 go
[SLAVE
] = tick_ops
->get_tick();
270 membar_safe("#StoreLoad");
273 spin_unlock_irqrestore(&itc_sync_lock
, flags
);
276 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
277 /* XXX Put this in some common place. XXX */
278 static unsigned long kimage_addr_to_ra(void *p
)
280 unsigned long val
= (unsigned long) p
;
282 return kern_base
+ (val
- KERNBASE
);
285 static void __cpuinit
ldom_startcpu_cpuid(unsigned int cpu
, unsigned long thread_reg
, void **descrp
)
287 extern unsigned long sparc64_ttable_tl0
;
288 extern unsigned long kern_locked_tte_data
;
289 struct hvtramp_descr
*hdesc
;
290 unsigned long trampoline_ra
;
291 struct trap_per_cpu
*tb
;
292 u64 tte_vaddr
, tte_data
;
293 unsigned long hv_err
;
296 hdesc
= kzalloc(sizeof(*hdesc
) +
297 (sizeof(struct hvtramp_mapping
) *
298 num_kernel_image_mappings
- 1),
301 printk(KERN_ERR
"ldom_startcpu_cpuid: Cannot allocate "
308 hdesc
->num_mappings
= num_kernel_image_mappings
;
310 tb
= &trap_block
[cpu
];
312 hdesc
->fault_info_va
= (unsigned long) &tb
->fault_info
;
313 hdesc
->fault_info_pa
= kimage_addr_to_ra(&tb
->fault_info
);
315 hdesc
->thread_reg
= thread_reg
;
317 tte_vaddr
= (unsigned long) KERNBASE
;
318 tte_data
= kern_locked_tte_data
;
320 for (i
= 0; i
< hdesc
->num_mappings
; i
++) {
321 hdesc
->maps
[i
].vaddr
= tte_vaddr
;
322 hdesc
->maps
[i
].tte
= tte_data
;
323 tte_vaddr
+= 0x400000;
324 tte_data
+= 0x400000;
327 trampoline_ra
= kimage_addr_to_ra(hv_cpu_startup
);
329 hv_err
= sun4v_cpu_start(cpu
, trampoline_ra
,
330 kimage_addr_to_ra(&sparc64_ttable_tl0
),
333 printk(KERN_ERR
"ldom_startcpu_cpuid: sun4v_cpu_start() "
334 "gives error %lu\n", hv_err
);
338 extern unsigned long sparc64_cpu_startup
;
340 /* The OBP cpu startup callback truncates the 3rd arg cookie to
341 * 32-bits (I think) so to be safe we have it read the pointer
342 * contained here so we work on >4GB machines. -DaveM
344 static struct thread_info
*cpu_new_thread
= NULL
;
346 static int __cpuinit
smp_boot_one_cpu(unsigned int cpu
, struct task_struct
*idle
)
348 unsigned long entry
=
349 (unsigned long)(&sparc64_cpu_startup
);
350 unsigned long cookie
=
351 (unsigned long)(&cpu_new_thread
);
356 cpu_new_thread
= task_thread_info(idle
);
358 if (tlb_type
== hypervisor
) {
359 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
360 if (ldom_domaining_enabled
)
361 ldom_startcpu_cpuid(cpu
,
362 (unsigned long) cpu_new_thread
,
366 prom_startcpu_cpuid(cpu
, entry
, cookie
);
368 struct device_node
*dp
= of_find_node_by_cpuid(cpu
);
370 prom_startcpu(dp
->phandle
, entry
, cookie
);
373 for (timeout
= 0; timeout
< 50000; timeout
++) {
382 printk("Processor %d is stuck.\n", cpu
);
385 cpu_new_thread
= NULL
;
392 static void spitfire_xcall_helper(u64 data0
, u64 data1
, u64 data2
, u64 pstate
, unsigned long cpu
)
397 if (this_is_starfire
) {
398 /* map to real upaid */
399 cpu
= (((cpu
& 0x3c) << 1) |
400 ((cpu
& 0x40) >> 4) |
404 target
= (cpu
<< 14) | 0x70;
406 /* Ok, this is the real Spitfire Errata #54.
407 * One must read back from a UDB internal register
408 * after writes to the UDB interrupt dispatch, but
409 * before the membar Sync for that write.
410 * So we use the high UDB control register (ASI 0x7f,
411 * ADDR 0x20) for the dummy read. -DaveM
414 __asm__
__volatile__(
415 "wrpr %1, %2, %%pstate\n\t"
416 "stxa %4, [%0] %3\n\t"
417 "stxa %5, [%0+%8] %3\n\t"
419 "stxa %6, [%0+%8] %3\n\t"
421 "stxa %%g0, [%7] %3\n\t"
424 "ldxa [%%g1] 0x7f, %%g0\n\t"
427 : "r" (pstate
), "i" (PSTATE_IE
), "i" (ASI_INTR_W
),
428 "r" (data0
), "r" (data1
), "r" (data2
), "r" (target
),
429 "r" (0x10), "0" (tmp
)
432 /* NOTE: PSTATE_IE is still clear. */
435 __asm__
__volatile__("ldxa [%%g0] %1, %0"
437 : "i" (ASI_INTR_DISPATCH_STAT
));
439 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
446 } while (result
& 0x1);
447 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
450 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
451 smp_processor_id(), result
);
458 static void spitfire_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
460 u64
*mondo
, data0
, data1
, data2
;
465 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
466 cpu_list
= __va(tb
->cpu_list_pa
);
467 mondo
= __va(tb
->cpu_mondo_block_pa
);
471 for (i
= 0; i
< cnt
; i
++)
472 spitfire_xcall_helper(data0
, data1
, data2
, pstate
, cpu_list
[i
]);
475 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
476 * packet, but we have no use for that. However we do take advantage of
477 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
479 static void cheetah_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
481 int nack_busy_id
, is_jbus
, need_more
;
482 u64
*mondo
, pstate
, ver
, busy_mask
;
485 cpu_list
= __va(tb
->cpu_list_pa
);
486 mondo
= __va(tb
->cpu_mondo_block_pa
);
488 /* Unfortunately, someone at Sun had the brilliant idea to make the
489 * busy/nack fields hard-coded by ITID number for this Ultra-III
490 * derivative processor.
492 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
493 is_jbus
= ((ver
>> 32) == __JALAPENO_ID
||
494 (ver
>> 32) == __SERRANO_ID
);
496 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
500 __asm__
__volatile__("wrpr %0, %1, %%pstate\n\t"
501 : : "r" (pstate
), "i" (PSTATE_IE
));
503 /* Setup the dispatch data registers. */
504 __asm__
__volatile__("stxa %0, [%3] %6\n\t"
505 "stxa %1, [%4] %6\n\t"
506 "stxa %2, [%5] %6\n\t"
509 : "r" (mondo
[0]), "r" (mondo
[1]), "r" (mondo
[2]),
510 "r" (0x40), "r" (0x50), "r" (0x60),
518 for (i
= 0; i
< cnt
; i
++) {
525 target
= (nr
<< 14) | 0x70;
527 busy_mask
|= (0x1UL
<< (nr
* 2));
529 target
|= (nack_busy_id
<< 24);
530 busy_mask
|= (0x1UL
<<
533 __asm__
__volatile__(
534 "stxa %%g0, [%0] %1\n\t"
537 : "r" (target
), "i" (ASI_INTR_W
));
539 if (nack_busy_id
== 32) {
546 /* Now, poll for completion. */
548 u64 dispatch_stat
, nack_mask
;
551 stuck
= 100000 * nack_busy_id
;
552 nack_mask
= busy_mask
<< 1;
554 __asm__
__volatile__("ldxa [%%g0] %1, %0"
555 : "=r" (dispatch_stat
)
556 : "i" (ASI_INTR_DISPATCH_STAT
));
557 if (!(dispatch_stat
& (busy_mask
| nack_mask
))) {
558 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
560 if (unlikely(need_more
)) {
562 for (i
= 0; i
< cnt
; i
++) {
563 if (cpu_list
[i
] == 0xffff)
565 cpu_list
[i
] = 0xffff;
576 } while (dispatch_stat
& busy_mask
);
578 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
581 if (dispatch_stat
& busy_mask
) {
582 /* Busy bits will not clear, continue instead
583 * of freezing up on this cpu.
585 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
586 smp_processor_id(), dispatch_stat
);
588 int i
, this_busy_nack
= 0;
590 /* Delay some random time with interrupts enabled
591 * to prevent deadlock.
593 udelay(2 * nack_busy_id
);
595 /* Clear out the mask bits for cpus which did not
598 for (i
= 0; i
< cnt
; i
++) {
606 check_mask
= (0x2UL
<< (2*nr
));
608 check_mask
= (0x2UL
<<
610 if ((dispatch_stat
& check_mask
) == 0)
611 cpu_list
[i
] = 0xffff;
613 if (this_busy_nack
== 64)
622 /* Multi-cpu list version. */
623 static void hypervisor_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
625 int retries
, this_cpu
, prev_sent
, i
, saw_cpu_error
;
626 unsigned long status
;
629 this_cpu
= smp_processor_id();
631 cpu_list
= __va(tb
->cpu_list_pa
);
637 int forward_progress
, n_sent
;
639 status
= sun4v_cpu_mondo_send(cnt
,
641 tb
->cpu_mondo_block_pa
);
643 /* HV_EOK means all cpus received the xcall, we're done. */
644 if (likely(status
== HV_EOK
))
647 /* First, see if we made any forward progress.
649 * The hypervisor indicates successful sends by setting
650 * cpu list entries to the value 0xffff.
653 for (i
= 0; i
< cnt
; i
++) {
654 if (likely(cpu_list
[i
] == 0xffff))
658 forward_progress
= 0;
659 if (n_sent
> prev_sent
)
660 forward_progress
= 1;
664 /* If we get a HV_ECPUERROR, then one or more of the cpus
665 * in the list are in error state. Use the cpu_state()
666 * hypervisor call to find out which cpus are in error state.
668 if (unlikely(status
== HV_ECPUERROR
)) {
669 for (i
= 0; i
< cnt
; i
++) {
677 err
= sun4v_cpu_state(cpu
);
678 if (err
== HV_CPU_STATE_ERROR
) {
679 saw_cpu_error
= (cpu
+ 1);
680 cpu_list
[i
] = 0xffff;
683 } else if (unlikely(status
!= HV_EWOULDBLOCK
))
684 goto fatal_mondo_error
;
686 /* Don't bother rewriting the CPU list, just leave the
687 * 0xffff and non-0xffff entries in there and the
688 * hypervisor will do the right thing.
690 * Only advance timeout state if we didn't make any
693 if (unlikely(!forward_progress
)) {
694 if (unlikely(++retries
> 10000))
695 goto fatal_mondo_timeout
;
697 /* Delay a little bit to let other cpus catch up
698 * on their cpu mondo queue work.
704 if (unlikely(saw_cpu_error
))
705 goto fatal_mondo_cpu_error
;
709 fatal_mondo_cpu_error
:
710 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo cpu error, some target cpus "
711 "(including %d) were in error state\n",
712 this_cpu
, saw_cpu_error
- 1);
716 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo timeout, no forward "
717 " progress after %d retries.\n",
719 goto dump_cpu_list_and_out
;
722 printk(KERN_CRIT
"CPU[%d]: Unexpected SUN4V mondo error %lu\n",
724 printk(KERN_CRIT
"CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
725 "mondo_block_pa(%lx)\n",
726 this_cpu
, cnt
, tb
->cpu_list_pa
, tb
->cpu_mondo_block_pa
);
728 dump_cpu_list_and_out
:
729 printk(KERN_CRIT
"CPU[%d]: CPU list [ ", this_cpu
);
730 for (i
= 0; i
< cnt
; i
++)
731 printk("%u ", cpu_list
[i
]);
735 static void (*xcall_deliver_impl
)(struct trap_per_cpu
*, int);
737 static void xcall_deliver(u64 data0
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
739 struct trap_per_cpu
*tb
;
740 int this_cpu
, i
, cnt
;
745 /* We have to do this whole thing with interrupts fully disabled.
746 * Otherwise if we send an xcall from interrupt context it will
747 * corrupt both our mondo block and cpu list state.
749 * One consequence of this is that we cannot use timeout mechanisms
750 * that depend upon interrupts being delivered locally. So, for
751 * example, we cannot sample jiffies and expect it to advance.
753 * Fortunately, udelay() uses %stick/%tick so we can use that.
755 local_irq_save(flags
);
757 this_cpu
= smp_processor_id();
758 tb
= &trap_block
[this_cpu
];
760 mondo
= __va(tb
->cpu_mondo_block_pa
);
766 cpu_list
= __va(tb
->cpu_list_pa
);
768 /* Setup the initial cpu list. */
770 for_each_cpu(i
, mask
) {
771 if (i
== this_cpu
|| !cpu_online(i
))
777 xcall_deliver_impl(tb
, cnt
);
779 local_irq_restore(flags
);
782 /* Send cross call to all processors mentioned in MASK_P
783 * except self. Really, there are only two cases currently,
784 * "cpu_online_mask" and "mm_cpumask(mm)".
786 static void smp_cross_call_masked(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
788 u64 data0
= (((u64
)ctx
)<<32 | (((u64
)func
) & 0xffffffff));
790 xcall_deliver(data0
, data1
, data2
, mask
);
793 /* Send cross call to all processors except self. */
794 static void smp_cross_call(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
)
796 smp_cross_call_masked(func
, ctx
, data1
, data2
, cpu_online_mask
);
799 extern unsigned long xcall_sync_tick
;
801 static void smp_start_sync_tick_client(int cpu
)
803 xcall_deliver((u64
) &xcall_sync_tick
, 0, 0,
807 extern unsigned long xcall_call_function
;
809 void arch_send_call_function_ipi_mask(const struct cpumask
*mask
)
811 xcall_deliver((u64
) &xcall_call_function
, 0, 0, mask
);
814 extern unsigned long xcall_call_function_single
;
816 void arch_send_call_function_single_ipi(int cpu
)
818 xcall_deliver((u64
) &xcall_call_function_single
, 0, 0,
822 void __irq_entry
smp_call_function_client(int irq
, struct pt_regs
*regs
)
824 clear_softint(1 << irq
);
825 generic_smp_call_function_interrupt();
828 void __irq_entry
smp_call_function_single_client(int irq
, struct pt_regs
*regs
)
830 clear_softint(1 << irq
);
831 generic_smp_call_function_single_interrupt();
834 static void tsb_sync(void *info
)
836 struct trap_per_cpu
*tp
= &trap_block
[raw_smp_processor_id()];
837 struct mm_struct
*mm
= info
;
839 /* It is not valid to test "current->active_mm == mm" here.
841 * The value of "current" is not changed atomically with
842 * switch_mm(). But that's OK, we just need to check the
843 * current cpu's trap block PGD physical address.
845 if (tp
->pgd_paddr
== __pa(mm
->pgd
))
846 tsb_context_switch(mm
);
849 void smp_tsb_sync(struct mm_struct
*mm
)
851 smp_call_function_many(mm_cpumask(mm
), tsb_sync
, mm
, 1);
854 extern unsigned long xcall_flush_tlb_mm
;
855 extern unsigned long xcall_flush_tlb_pending
;
856 extern unsigned long xcall_flush_tlb_kernel_range
;
857 extern unsigned long xcall_fetch_glob_regs
;
858 extern unsigned long xcall_receive_signal
;
859 extern unsigned long xcall_new_mmu_context_version
;
861 extern unsigned long xcall_kgdb_capture
;
864 #ifdef DCACHE_ALIASING_POSSIBLE
865 extern unsigned long xcall_flush_dcache_page_cheetah
;
867 extern unsigned long xcall_flush_dcache_page_spitfire
;
869 #ifdef CONFIG_DEBUG_DCFLUSH
870 extern atomic_t dcpage_flushes
;
871 extern atomic_t dcpage_flushes_xcall
;
874 static inline void __local_flush_dcache_page(struct page
*page
)
876 #ifdef DCACHE_ALIASING_POSSIBLE
877 __flush_dcache_page(page_address(page
),
878 ((tlb_type
== spitfire
) &&
879 page_mapping(page
) != NULL
));
881 if (page_mapping(page
) != NULL
&&
882 tlb_type
== spitfire
)
883 __flush_icache_page(__pa(page_address(page
)));
887 void smp_flush_dcache_page_impl(struct page
*page
, int cpu
)
891 if (tlb_type
== hypervisor
)
894 #ifdef CONFIG_DEBUG_DCFLUSH
895 atomic_inc(&dcpage_flushes
);
898 this_cpu
= get_cpu();
900 if (cpu
== this_cpu
) {
901 __local_flush_dcache_page(page
);
902 } else if (cpu_online(cpu
)) {
903 void *pg_addr
= page_address(page
);
906 if (tlb_type
== spitfire
) {
907 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
908 if (page_mapping(page
) != NULL
)
909 data0
|= ((u64
)1 << 32);
910 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
911 #ifdef DCACHE_ALIASING_POSSIBLE
912 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
916 xcall_deliver(data0
, __pa(pg_addr
),
917 (u64
) pg_addr
, cpumask_of(cpu
));
918 #ifdef CONFIG_DEBUG_DCFLUSH
919 atomic_inc(&dcpage_flushes_xcall
);
927 void flush_dcache_page_all(struct mm_struct
*mm
, struct page
*page
)
932 if (tlb_type
== hypervisor
)
937 #ifdef CONFIG_DEBUG_DCFLUSH
938 atomic_inc(&dcpage_flushes
);
941 pg_addr
= page_address(page
);
942 if (tlb_type
== spitfire
) {
943 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
944 if (page_mapping(page
) != NULL
)
945 data0
|= ((u64
)1 << 32);
946 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
947 #ifdef DCACHE_ALIASING_POSSIBLE
948 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
952 xcall_deliver(data0
, __pa(pg_addr
),
953 (u64
) pg_addr
, cpu_online_mask
);
954 #ifdef CONFIG_DEBUG_DCFLUSH
955 atomic_inc(&dcpage_flushes_xcall
);
958 __local_flush_dcache_page(page
);
963 void __irq_entry
smp_new_mmu_context_version_client(int irq
, struct pt_regs
*regs
)
965 struct mm_struct
*mm
;
968 clear_softint(1 << irq
);
970 /* See if we need to allocate a new TLB context because
971 * the version of the one we are using is now out of date.
973 mm
= current
->active_mm
;
974 if (unlikely(!mm
|| (mm
== &init_mm
)))
977 spin_lock_irqsave(&mm
->context
.lock
, flags
);
979 if (unlikely(!CTX_VALID(mm
->context
)))
980 get_new_mmu_context(mm
);
982 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
984 load_secondary_context(mm
);
985 __flush_tlb_mm(CTX_HWBITS(mm
->context
),
989 void smp_new_mmu_context_version(void)
991 smp_cross_call(&xcall_new_mmu_context_version
, 0, 0, 0);
995 void kgdb_roundup_cpus(unsigned long flags
)
997 smp_cross_call(&xcall_kgdb_capture
, 0, 0, 0);
1001 void smp_fetch_global_regs(void)
1003 smp_cross_call(&xcall_fetch_glob_regs
, 0, 0, 0);
1006 /* We know that the window frames of the user have been flushed
1007 * to the stack before we get here because all callers of us
1008 * are flush_tlb_*() routines, and these run after flush_cache_*()
1009 * which performs the flushw.
1011 * The SMP TLB coherency scheme we use works as follows:
1013 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1014 * space has (potentially) executed on, this is the heuristic
1015 * we use to avoid doing cross calls.
1017 * Also, for flushing from kswapd and also for clones, we
1018 * use cpu_vm_mask as the list of cpus to make run the TLB.
1020 * 2) TLB context numbers are shared globally across all processors
1021 * in the system, this allows us to play several games to avoid
1024 * One invariant is that when a cpu switches to a process, and
1025 * that processes tsk->active_mm->cpu_vm_mask does not have the
1026 * current cpu's bit set, that tlb context is flushed locally.
1028 * If the address space is non-shared (ie. mm->count == 1) we avoid
1029 * cross calls when we want to flush the currently running process's
1030 * tlb state. This is done by clearing all cpu bits except the current
1031 * processor's in current->mm->cpu_vm_mask and performing the
1032 * flush locally only. This will force any subsequent cpus which run
1033 * this task to flush the context from the local tlb if the process
1034 * migrates to another cpu (again).
1036 * 3) For shared address spaces (threads) and swapping we bite the
1037 * bullet for most cases and perform the cross call (but only to
1038 * the cpus listed in cpu_vm_mask).
1040 * The performance gain from "optimizing" away the cross call for threads is
1041 * questionable (in theory the big win for threads is the massive sharing of
1042 * address space state across processors).
1045 /* This currently is only used by the hugetlb arch pre-fault
1046 * hook on UltraSPARC-III+ and later when changing the pagesize
1047 * bits of the context register for an address space.
1049 void smp_flush_tlb_mm(struct mm_struct
*mm
)
1051 u32 ctx
= CTX_HWBITS(mm
->context
);
1052 int cpu
= get_cpu();
1054 if (atomic_read(&mm
->mm_users
) == 1) {
1055 cpumask_copy(mm_cpumask(mm
), cpumask_of(cpu
));
1056 goto local_flush_and_out
;
1059 smp_cross_call_masked(&xcall_flush_tlb_mm
,
1063 local_flush_and_out
:
1064 __flush_tlb_mm(ctx
, SECONDARY_CONTEXT
);
1069 void smp_flush_tlb_pending(struct mm_struct
*mm
, unsigned long nr
, unsigned long *vaddrs
)
1071 u32 ctx
= CTX_HWBITS(mm
->context
);
1072 int cpu
= get_cpu();
1074 if (mm
== current
->mm
&& atomic_read(&mm
->mm_users
) == 1)
1075 cpumask_copy(mm_cpumask(mm
), cpumask_of(cpu
));
1077 smp_cross_call_masked(&xcall_flush_tlb_pending
,
1078 ctx
, nr
, (unsigned long) vaddrs
,
1081 __flush_tlb_pending(ctx
, nr
, vaddrs
);
1086 void smp_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
1089 end
= PAGE_ALIGN(end
);
1091 smp_cross_call(&xcall_flush_tlb_kernel_range
,
1094 __flush_tlb_kernel_range(start
, end
);
1099 /* #define CAPTURE_DEBUG */
1100 extern unsigned long xcall_capture
;
1102 static atomic_t smp_capture_depth
= ATOMIC_INIT(0);
1103 static atomic_t smp_capture_registry
= ATOMIC_INIT(0);
1104 static unsigned long penguins_are_doing_time
;
1106 void smp_capture(void)
1108 int result
= atomic_add_ret(1, &smp_capture_depth
);
1111 int ncpus
= num_online_cpus();
1113 #ifdef CAPTURE_DEBUG
1114 printk("CPU[%d]: Sending penguins to jail...",
1115 smp_processor_id());
1117 penguins_are_doing_time
= 1;
1118 atomic_inc(&smp_capture_registry
);
1119 smp_cross_call(&xcall_capture
, 0, 0, 0);
1120 while (atomic_read(&smp_capture_registry
) != ncpus
)
1122 #ifdef CAPTURE_DEBUG
1128 void smp_release(void)
1130 if (atomic_dec_and_test(&smp_capture_depth
)) {
1131 #ifdef CAPTURE_DEBUG
1132 printk("CPU[%d]: Giving pardon to "
1133 "imprisoned penguins\n",
1134 smp_processor_id());
1136 penguins_are_doing_time
= 0;
1137 membar_safe("#StoreLoad");
1138 atomic_dec(&smp_capture_registry
);
1142 /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1143 * set, so they can service tlb flush xcalls...
1145 extern void prom_world(int);
1147 void __irq_entry
smp_penguin_jailcell(int irq
, struct pt_regs
*regs
)
1149 clear_softint(1 << irq
);
1153 __asm__
__volatile__("flushw");
1155 atomic_inc(&smp_capture_registry
);
1156 membar_safe("#StoreLoad");
1157 while (penguins_are_doing_time
)
1159 atomic_dec(&smp_capture_registry
);
1165 /* /proc/profile writes can call this, don't __init it please. */
1166 int setup_profiling_timer(unsigned int multiplier
)
1171 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1175 void __devinit
smp_prepare_boot_cpu(void)
1179 void __init
smp_setup_processor_id(void)
1181 if (tlb_type
== spitfire
)
1182 xcall_deliver_impl
= spitfire_xcall_deliver
;
1183 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1184 xcall_deliver_impl
= cheetah_xcall_deliver
;
1186 xcall_deliver_impl
= hypervisor_xcall_deliver
;
1189 void __devinit
smp_fill_in_sib_core_maps(void)
1193 for_each_present_cpu(i
) {
1196 cpumask_clear(&cpu_core_map
[i
]);
1197 if (cpu_data(i
).core_id
== 0) {
1198 cpumask_set_cpu(i
, &cpu_core_map
[i
]);
1202 for_each_present_cpu(j
) {
1203 if (cpu_data(i
).core_id
==
1204 cpu_data(j
).core_id
)
1205 cpumask_set_cpu(j
, &cpu_core_map
[i
]);
1209 for_each_present_cpu(i
) {
1212 cpumask_clear(&per_cpu(cpu_sibling_map
, i
));
1213 if (cpu_data(i
).proc_id
== -1) {
1214 cpumask_set_cpu(i
, &per_cpu(cpu_sibling_map
, i
));
1218 for_each_present_cpu(j
) {
1219 if (cpu_data(i
).proc_id
==
1220 cpu_data(j
).proc_id
)
1221 cpumask_set_cpu(j
, &per_cpu(cpu_sibling_map
, i
));
1226 int __cpuinit
__cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1228 int ret
= smp_boot_one_cpu(cpu
, tidle
);
1231 cpumask_set_cpu(cpu
, &smp_commenced_mask
);
1232 while (!cpu_online(cpu
))
1234 if (!cpu_online(cpu
)) {
1237 /* On SUN4V, writes to %tick and %stick are
1240 if (tlb_type
!= hypervisor
)
1241 smp_synchronize_one_tick(cpu
);
1247 #ifdef CONFIG_HOTPLUG_CPU
1248 void cpu_play_dead(void)
1250 int cpu
= smp_processor_id();
1251 unsigned long pstate
;
1255 if (tlb_type
== hypervisor
) {
1256 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1258 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO
,
1259 tb
->cpu_mondo_pa
, 0);
1260 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO
,
1261 tb
->dev_mondo_pa
, 0);
1262 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR
,
1263 tb
->resum_mondo_pa
, 0);
1264 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR
,
1265 tb
->nonresum_mondo_pa
, 0);
1268 cpumask_clear_cpu(cpu
, &smp_commenced_mask
);
1269 membar_safe("#Sync");
1271 local_irq_disable();
1273 __asm__
__volatile__(
1274 "rdpr %%pstate, %0\n\t"
1275 "wrpr %0, %1, %%pstate"
1283 int __cpu_disable(void)
1285 int cpu
= smp_processor_id();
1289 for_each_cpu(i
, &cpu_core_map
[cpu
])
1290 cpumask_clear_cpu(cpu
, &cpu_core_map
[i
]);
1291 cpumask_clear(&cpu_core_map
[cpu
]);
1293 for_each_cpu(i
, &per_cpu(cpu_sibling_map
, cpu
))
1294 cpumask_clear_cpu(cpu
, &per_cpu(cpu_sibling_map
, i
));
1295 cpumask_clear(&per_cpu(cpu_sibling_map
, cpu
));
1304 /* Make sure no interrupts point to this cpu. */
1309 local_irq_disable();
1312 set_cpu_online(cpu
, false);
1320 void __cpu_die(unsigned int cpu
)
1324 for (i
= 0; i
< 100; i
++) {
1326 if (!cpumask_test_cpu(cpu
, &smp_commenced_mask
))
1330 if (cpumask_test_cpu(cpu
, &smp_commenced_mask
)) {
1331 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1333 #if defined(CONFIG_SUN_LDOMS)
1334 unsigned long hv_err
;
1338 hv_err
= sun4v_cpu_stop(cpu
);
1339 if (hv_err
== HV_EOK
) {
1340 set_cpu_present(cpu
, false);
1343 } while (--limit
> 0);
1345 printk(KERN_ERR
"sun4v_cpu_stop() fails err=%lu\n",
1353 void __init
smp_cpus_done(unsigned int max_cpus
)
1358 void smp_send_reschedule(int cpu
)
1360 xcall_deliver((u64
) &xcall_receive_signal
, 0, 0,
1364 void __irq_entry
smp_receive_signal_client(int irq
, struct pt_regs
*regs
)
1366 clear_softint(1 << irq
);
1370 /* This is a nop because we capture all other cpus
1371 * anyways when making the PROM active.
1373 void smp_send_stop(void)
1378 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1379 * @cpu: cpu to allocate for
1380 * @size: size allocation in bytes
1383 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1384 * does the right thing for NUMA regardless of the current
1388 * Pointer to the allocated area on success, NULL on failure.
1390 static void * __init
pcpu_alloc_bootmem(unsigned int cpu
, size_t size
,
1393 const unsigned long goal
= __pa(MAX_DMA_ADDRESS
);
1394 #ifdef CONFIG_NEED_MULTIPLE_NODES
1395 int node
= cpu_to_node(cpu
);
1398 if (!node_online(node
) || !NODE_DATA(node
)) {
1399 ptr
= __alloc_bootmem(size
, align
, goal
);
1400 pr_info("cpu %d has no node %d or node-local memory\n",
1402 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1403 cpu
, size
, __pa(ptr
));
1405 ptr
= __alloc_bootmem_node(NODE_DATA(node
),
1407 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1408 "%016lx\n", cpu
, size
, node
, __pa(ptr
));
1412 return __alloc_bootmem(size
, align
, goal
);
1416 static void __init
pcpu_free_bootmem(void *ptr
, size_t size
)
1418 free_bootmem(__pa(ptr
), size
);
1421 static int __init
pcpu_cpu_distance(unsigned int from
, unsigned int to
)
1423 if (cpu_to_node(from
) == cpu_to_node(to
))
1424 return LOCAL_DISTANCE
;
1426 return REMOTE_DISTANCE
;
1429 static void __init
pcpu_populate_pte(unsigned long addr
)
1431 pgd_t
*pgd
= pgd_offset_k(addr
);
1435 pud
= pud_offset(pgd
, addr
);
1436 if (pud_none(*pud
)) {
1439 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1440 pud_populate(&init_mm
, pud
, new);
1443 pmd
= pmd_offset(pud
, addr
);
1444 if (!pmd_present(*pmd
)) {
1447 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1448 pmd_populate_kernel(&init_mm
, pmd
, new);
1452 void __init
setup_per_cpu_areas(void)
1454 unsigned long delta
;
1458 if (pcpu_chosen_fc
!= PCPU_FC_PAGE
) {
1459 rc
= pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE
,
1460 PERCPU_DYNAMIC_RESERVE
, 4 << 20,
1465 pr_warning("PERCPU: %s allocator failed (%d), "
1466 "falling back to page size\n",
1467 pcpu_fc_names
[pcpu_chosen_fc
], rc
);
1470 rc
= pcpu_page_first_chunk(PERCPU_MODULE_RESERVE
,
1475 panic("cannot initialize percpu area (err=%d)", rc
);
1477 delta
= (unsigned long)pcpu_base_addr
- (unsigned long)__per_cpu_start
;
1478 for_each_possible_cpu(cpu
)
1479 __per_cpu_offset(cpu
) = delta
+ pcpu_unit_offsets
[cpu
];
1481 /* Setup %g5 for the boot cpu. */
1482 __local_per_cpu_offset
= __per_cpu_offset(smp_processor_id());
1484 of_fill_in_cpu_data();
1485 if (tlb_type
== hypervisor
)
1486 mdesc_fill_in_cpu_data(cpu_all_mask
);