1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/lmb.h>
24 #include <linux/cpu.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
32 #include <asm/hvtramp.h>
34 #include <asm/timer.h>
37 #include <asm/irq_regs.h>
39 #include <asm/pgtable.h>
40 #include <asm/oplib.h>
41 #include <asm/uaccess.h>
42 #include <asm/starfire.h>
44 #include <asm/sections.h>
46 #include <asm/mdesc.h>
48 #include <asm/hypervisor.h>
50 int sparc64_multi_core __read_mostly
;
52 cpumask_t cpu_possible_map __read_mostly
= CPU_MASK_NONE
;
53 cpumask_t cpu_online_map __read_mostly
= CPU_MASK_NONE
;
54 DEFINE_PER_CPU(cpumask_t
, cpu_sibling_map
) = CPU_MASK_NONE
;
55 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
=
56 { [0 ... NR_CPUS
-1] = CPU_MASK_NONE
};
58 EXPORT_SYMBOL(cpu_possible_map
);
59 EXPORT_SYMBOL(cpu_online_map
);
60 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
61 EXPORT_SYMBOL(cpu_core_map
);
63 static cpumask_t smp_commenced_mask
;
65 void smp_info(struct seq_file
*m
)
69 seq_printf(m
, "State:\n");
70 for_each_online_cpu(i
)
71 seq_printf(m
, "CPU%d:\t\tonline\n", i
);
74 void smp_bogo(struct seq_file
*m
)
78 for_each_online_cpu(i
)
80 "Cpu%dClkTck\t: %016lx\n",
81 i
, cpu_data(i
).clock_tick
);
84 extern void setup_sparc64_timer(void);
86 static volatile unsigned long callin_flag
= 0;
88 void __cpuinit
smp_callin(void)
90 int cpuid
= hard_smp_processor_id();
92 __local_per_cpu_offset
= __per_cpu_offset(cpuid
);
94 if (tlb_type
== hypervisor
)
95 sun4v_ktsb_register();
99 setup_sparc64_timer();
101 if (cheetah_pcache_forced_on
)
102 cheetah_enable_pcache();
107 __asm__
__volatile__("membar #Sync\n\t"
108 "flush %%g6" : : : "memory");
110 /* Clear this or we will die instantly when we
111 * schedule back to this idler...
113 current_thread_info()->new_child
= 0;
115 /* Attach to the address space of init_task. */
116 atomic_inc(&init_mm
.mm_count
);
117 current
->active_mm
= &init_mm
;
119 /* inform the notifiers about the new cpu */
120 notify_cpu_starting(cpuid
);
122 while (!cpu_isset(cpuid
, smp_commenced_mask
))
126 cpu_set(cpuid
, cpu_online_map
);
129 /* idle thread is expected to have preempt disabled */
135 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
136 panic("SMP bolixed\n");
139 /* This tick register synchronization scheme is taken entirely from
140 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
142 * The only change I've made is to rework it so that the master
143 * initiates the synchonization instead of the slave. -DaveM
147 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
149 #define NUM_ROUNDS 64 /* magic value */
150 #define NUM_ITERS 5 /* likewise */
152 static DEFINE_SPINLOCK(itc_sync_lock
);
153 static unsigned long go
[SLAVE
+ 1];
155 #define DEBUG_TICK_SYNC 0
157 static inline long get_delta (long *rt
, long *master
)
159 unsigned long best_t0
= 0, best_t1
= ~0UL, best_tm
= 0;
160 unsigned long tcenter
, t0
, t1
, tm
;
163 for (i
= 0; i
< NUM_ITERS
; i
++) {
164 t0
= tick_ops
->get_tick();
166 membar_safe("#StoreLoad");
167 while (!(tm
= go
[SLAVE
]))
171 t1
= tick_ops
->get_tick();
173 if (t1
- t0
< best_t1
- best_t0
)
174 best_t0
= t0
, best_t1
= t1
, best_tm
= tm
;
177 *rt
= best_t1
- best_t0
;
178 *master
= best_tm
- best_t0
;
180 /* average best_t0 and best_t1 without overflow: */
181 tcenter
= (best_t0
/2 + best_t1
/2);
182 if (best_t0
% 2 + best_t1
% 2 == 2)
184 return tcenter
- best_tm
;
187 void smp_synchronize_tick_client(void)
189 long i
, delta
, adj
, adjust_latency
= 0, done
= 0;
190 unsigned long flags
, rt
, master_time_stamp
, bound
;
193 long rt
; /* roundtrip time */
194 long master
; /* master's timestamp */
195 long diff
; /* difference between midpoint and master's timestamp */
196 long lat
; /* estimate of itc adjustment latency */
205 local_irq_save(flags
);
207 for (i
= 0; i
< NUM_ROUNDS
; i
++) {
208 delta
= get_delta(&rt
, &master_time_stamp
);
210 done
= 1; /* let's lock on to this... */
216 adjust_latency
+= -delta
;
217 adj
= -delta
+ adjust_latency
/4;
221 tick_ops
->add_tick(adj
);
225 t
[i
].master
= master_time_stamp
;
227 t
[i
].lat
= adjust_latency
/4;
231 local_irq_restore(flags
);
234 for (i
= 0; i
< NUM_ROUNDS
; i
++)
235 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
236 t
[i
].rt
, t
[i
].master
, t
[i
].diff
, t
[i
].lat
);
239 printk(KERN_INFO
"CPU %d: synchronized TICK with master CPU "
240 "(last diff %ld cycles, maxerr %lu cycles)\n",
241 smp_processor_id(), delta
, rt
);
244 static void smp_start_sync_tick_client(int cpu
);
246 static void smp_synchronize_one_tick(int cpu
)
248 unsigned long flags
, i
;
252 smp_start_sync_tick_client(cpu
);
254 /* wait for client to be ready */
258 /* now let the client proceed into his loop */
260 membar_safe("#StoreLoad");
262 spin_lock_irqsave(&itc_sync_lock
, flags
);
264 for (i
= 0; i
< NUM_ROUNDS
*NUM_ITERS
; i
++) {
269 go
[SLAVE
] = tick_ops
->get_tick();
270 membar_safe("#StoreLoad");
273 spin_unlock_irqrestore(&itc_sync_lock
, flags
);
276 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
277 /* XXX Put this in some common place. XXX */
278 static unsigned long kimage_addr_to_ra(void *p
)
280 unsigned long val
= (unsigned long) p
;
282 return kern_base
+ (val
- KERNBASE
);
285 static void __cpuinit
ldom_startcpu_cpuid(unsigned int cpu
, unsigned long thread_reg
)
287 extern unsigned long sparc64_ttable_tl0
;
288 extern unsigned long kern_locked_tte_data
;
289 struct hvtramp_descr
*hdesc
;
290 unsigned long trampoline_ra
;
291 struct trap_per_cpu
*tb
;
292 u64 tte_vaddr
, tte_data
;
293 unsigned long hv_err
;
296 hdesc
= kzalloc(sizeof(*hdesc
) +
297 (sizeof(struct hvtramp_mapping
) *
298 num_kernel_image_mappings
- 1),
301 printk(KERN_ERR
"ldom_startcpu_cpuid: Cannot allocate "
307 hdesc
->num_mappings
= num_kernel_image_mappings
;
309 tb
= &trap_block
[cpu
];
312 hdesc
->fault_info_va
= (unsigned long) &tb
->fault_info
;
313 hdesc
->fault_info_pa
= kimage_addr_to_ra(&tb
->fault_info
);
315 hdesc
->thread_reg
= thread_reg
;
317 tte_vaddr
= (unsigned long) KERNBASE
;
318 tte_data
= kern_locked_tte_data
;
320 for (i
= 0; i
< hdesc
->num_mappings
; i
++) {
321 hdesc
->maps
[i
].vaddr
= tte_vaddr
;
322 hdesc
->maps
[i
].tte
= tte_data
;
323 tte_vaddr
+= 0x400000;
324 tte_data
+= 0x400000;
327 trampoline_ra
= kimage_addr_to_ra(hv_cpu_startup
);
329 hv_err
= sun4v_cpu_start(cpu
, trampoline_ra
,
330 kimage_addr_to_ra(&sparc64_ttable_tl0
),
333 printk(KERN_ERR
"ldom_startcpu_cpuid: sun4v_cpu_start() "
334 "gives error %lu\n", hv_err
);
338 extern unsigned long sparc64_cpu_startup
;
340 /* The OBP cpu startup callback truncates the 3rd arg cookie to
341 * 32-bits (I think) so to be safe we have it read the pointer
342 * contained here so we work on >4GB machines. -DaveM
344 static struct thread_info
*cpu_new_thread
= NULL
;
346 static int __cpuinit
smp_boot_one_cpu(unsigned int cpu
)
348 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
349 unsigned long entry
=
350 (unsigned long)(&sparc64_cpu_startup
);
351 unsigned long cookie
=
352 (unsigned long)(&cpu_new_thread
);
353 struct task_struct
*p
;
360 cpu_new_thread
= task_thread_info(p
);
362 if (tlb_type
== hypervisor
) {
363 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
364 if (ldom_domaining_enabled
)
365 ldom_startcpu_cpuid(cpu
,
366 (unsigned long) cpu_new_thread
);
369 prom_startcpu_cpuid(cpu
, entry
, cookie
);
371 struct device_node
*dp
= of_find_node_by_cpuid(cpu
);
373 prom_startcpu(dp
->node
, entry
, cookie
);
376 for (timeout
= 0; timeout
< 50000; timeout
++) {
385 printk("Processor %d is stuck.\n", cpu
);
388 cpu_new_thread
= NULL
;
398 static void spitfire_xcall_helper(u64 data0
, u64 data1
, u64 data2
, u64 pstate
, unsigned long cpu
)
403 if (this_is_starfire
) {
404 /* map to real upaid */
405 cpu
= (((cpu
& 0x3c) << 1) |
406 ((cpu
& 0x40) >> 4) |
410 target
= (cpu
<< 14) | 0x70;
412 /* Ok, this is the real Spitfire Errata #54.
413 * One must read back from a UDB internal register
414 * after writes to the UDB interrupt dispatch, but
415 * before the membar Sync for that write.
416 * So we use the high UDB control register (ASI 0x7f,
417 * ADDR 0x20) for the dummy read. -DaveM
420 __asm__
__volatile__(
421 "wrpr %1, %2, %%pstate\n\t"
422 "stxa %4, [%0] %3\n\t"
423 "stxa %5, [%0+%8] %3\n\t"
425 "stxa %6, [%0+%8] %3\n\t"
427 "stxa %%g0, [%7] %3\n\t"
430 "ldxa [%%g1] 0x7f, %%g0\n\t"
433 : "r" (pstate
), "i" (PSTATE_IE
), "i" (ASI_INTR_W
),
434 "r" (data0
), "r" (data1
), "r" (data2
), "r" (target
),
435 "r" (0x10), "0" (tmp
)
438 /* NOTE: PSTATE_IE is still clear. */
441 __asm__
__volatile__("ldxa [%%g0] %1, %0"
443 : "i" (ASI_INTR_DISPATCH_STAT
));
445 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
452 } while (result
& 0x1);
453 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
456 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
457 smp_processor_id(), result
);
464 static void spitfire_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
466 u64
*mondo
, data0
, data1
, data2
;
471 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
472 cpu_list
= __va(tb
->cpu_list_pa
);
473 mondo
= __va(tb
->cpu_mondo_block_pa
);
477 for (i
= 0; i
< cnt
; i
++)
478 spitfire_xcall_helper(data0
, data1
, data2
, pstate
, cpu_list
[i
]);
481 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
482 * packet, but we have no use for that. However we do take advantage of
483 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
485 static void cheetah_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
487 int nack_busy_id
, is_jbus
, need_more
;
488 u64
*mondo
, pstate
, ver
, busy_mask
;
491 cpu_list
= __va(tb
->cpu_list_pa
);
492 mondo
= __va(tb
->cpu_mondo_block_pa
);
494 /* Unfortunately, someone at Sun had the brilliant idea to make the
495 * busy/nack fields hard-coded by ITID number for this Ultra-III
496 * derivative processor.
498 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
499 is_jbus
= ((ver
>> 32) == __JALAPENO_ID
||
500 (ver
>> 32) == __SERRANO_ID
);
502 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
506 __asm__
__volatile__("wrpr %0, %1, %%pstate\n\t"
507 : : "r" (pstate
), "i" (PSTATE_IE
));
509 /* Setup the dispatch data registers. */
510 __asm__
__volatile__("stxa %0, [%3] %6\n\t"
511 "stxa %1, [%4] %6\n\t"
512 "stxa %2, [%5] %6\n\t"
515 : "r" (mondo
[0]), "r" (mondo
[1]), "r" (mondo
[2]),
516 "r" (0x40), "r" (0x50), "r" (0x60),
524 for (i
= 0; i
< cnt
; i
++) {
531 target
= (nr
<< 14) | 0x70;
533 busy_mask
|= (0x1UL
<< (nr
* 2));
535 target
|= (nack_busy_id
<< 24);
536 busy_mask
|= (0x1UL
<<
539 __asm__
__volatile__(
540 "stxa %%g0, [%0] %1\n\t"
543 : "r" (target
), "i" (ASI_INTR_W
));
545 if (nack_busy_id
== 32) {
552 /* Now, poll for completion. */
554 u64 dispatch_stat
, nack_mask
;
557 stuck
= 100000 * nack_busy_id
;
558 nack_mask
= busy_mask
<< 1;
560 __asm__
__volatile__("ldxa [%%g0] %1, %0"
561 : "=r" (dispatch_stat
)
562 : "i" (ASI_INTR_DISPATCH_STAT
));
563 if (!(dispatch_stat
& (busy_mask
| nack_mask
))) {
564 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
566 if (unlikely(need_more
)) {
568 for (i
= 0; i
< cnt
; i
++) {
569 if (cpu_list
[i
] == 0xffff)
571 cpu_list
[i
] = 0xffff;
582 } while (dispatch_stat
& busy_mask
);
584 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
587 if (dispatch_stat
& busy_mask
) {
588 /* Busy bits will not clear, continue instead
589 * of freezing up on this cpu.
591 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
592 smp_processor_id(), dispatch_stat
);
594 int i
, this_busy_nack
= 0;
596 /* Delay some random time with interrupts enabled
597 * to prevent deadlock.
599 udelay(2 * nack_busy_id
);
601 /* Clear out the mask bits for cpus which did not
604 for (i
= 0; i
< cnt
; i
++) {
612 check_mask
= (0x2UL
<< (2*nr
));
614 check_mask
= (0x2UL
<<
616 if ((dispatch_stat
& check_mask
) == 0)
617 cpu_list
[i
] = 0xffff;
619 if (this_busy_nack
== 64)
628 /* Multi-cpu list version. */
629 static void hypervisor_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
631 int retries
, this_cpu
, prev_sent
, i
, saw_cpu_error
;
632 unsigned long status
;
635 this_cpu
= smp_processor_id();
637 cpu_list
= __va(tb
->cpu_list_pa
);
643 int forward_progress
, n_sent
;
645 status
= sun4v_cpu_mondo_send(cnt
,
647 tb
->cpu_mondo_block_pa
);
649 /* HV_EOK means all cpus received the xcall, we're done. */
650 if (likely(status
== HV_EOK
))
653 /* First, see if we made any forward progress.
655 * The hypervisor indicates successful sends by setting
656 * cpu list entries to the value 0xffff.
659 for (i
= 0; i
< cnt
; i
++) {
660 if (likely(cpu_list
[i
] == 0xffff))
664 forward_progress
= 0;
665 if (n_sent
> prev_sent
)
666 forward_progress
= 1;
670 /* If we get a HV_ECPUERROR, then one or more of the cpus
671 * in the list are in error state. Use the cpu_state()
672 * hypervisor call to find out which cpus are in error state.
674 if (unlikely(status
== HV_ECPUERROR
)) {
675 for (i
= 0; i
< cnt
; i
++) {
683 err
= sun4v_cpu_state(cpu
);
684 if (err
== HV_CPU_STATE_ERROR
) {
685 saw_cpu_error
= (cpu
+ 1);
686 cpu_list
[i
] = 0xffff;
689 } else if (unlikely(status
!= HV_EWOULDBLOCK
))
690 goto fatal_mondo_error
;
692 /* Don't bother rewriting the CPU list, just leave the
693 * 0xffff and non-0xffff entries in there and the
694 * hypervisor will do the right thing.
696 * Only advance timeout state if we didn't make any
699 if (unlikely(!forward_progress
)) {
700 if (unlikely(++retries
> 10000))
701 goto fatal_mondo_timeout
;
703 /* Delay a little bit to let other cpus catch up
704 * on their cpu mondo queue work.
710 if (unlikely(saw_cpu_error
))
711 goto fatal_mondo_cpu_error
;
715 fatal_mondo_cpu_error
:
716 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo cpu error, some target cpus "
717 "(including %d) were in error state\n",
718 this_cpu
, saw_cpu_error
- 1);
722 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo timeout, no forward "
723 " progress after %d retries.\n",
725 goto dump_cpu_list_and_out
;
728 printk(KERN_CRIT
"CPU[%d]: Unexpected SUN4V mondo error %lu\n",
730 printk(KERN_CRIT
"CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
731 "mondo_block_pa(%lx)\n",
732 this_cpu
, cnt
, tb
->cpu_list_pa
, tb
->cpu_mondo_block_pa
);
734 dump_cpu_list_and_out
:
735 printk(KERN_CRIT
"CPU[%d]: CPU list [ ", this_cpu
);
736 for (i
= 0; i
< cnt
; i
++)
737 printk("%u ", cpu_list
[i
]);
741 static void (*xcall_deliver_impl
)(struct trap_per_cpu
*, int);
743 static void xcall_deliver(u64 data0
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
745 struct trap_per_cpu
*tb
;
746 int this_cpu
, i
, cnt
;
751 /* We have to do this whole thing with interrupts fully disabled.
752 * Otherwise if we send an xcall from interrupt context it will
753 * corrupt both our mondo block and cpu list state.
755 * One consequence of this is that we cannot use timeout mechanisms
756 * that depend upon interrupts being delivered locally. So, for
757 * example, we cannot sample jiffies and expect it to advance.
759 * Fortunately, udelay() uses %stick/%tick so we can use that.
761 local_irq_save(flags
);
763 this_cpu
= smp_processor_id();
764 tb
= &trap_block
[this_cpu
];
766 mondo
= __va(tb
->cpu_mondo_block_pa
);
772 cpu_list
= __va(tb
->cpu_list_pa
);
774 /* Setup the initial cpu list. */
776 for_each_cpu_mask_nr(i
, *mask
) {
777 if (i
== this_cpu
|| !cpu_online(i
))
783 xcall_deliver_impl(tb
, cnt
);
785 local_irq_restore(flags
);
788 /* Send cross call to all processors mentioned in MASK_P
789 * except self. Really, there are only two cases currently,
790 * "&cpu_online_map" and "&mm->cpu_vm_mask".
792 static void smp_cross_call_masked(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
794 u64 data0
= (((u64
)ctx
)<<32 | (((u64
)func
) & 0xffffffff));
796 xcall_deliver(data0
, data1
, data2
, mask
);
799 /* Send cross call to all processors except self. */
800 static void smp_cross_call(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
)
802 smp_cross_call_masked(func
, ctx
, data1
, data2
, &cpu_online_map
);
805 extern unsigned long xcall_sync_tick
;
807 static void smp_start_sync_tick_client(int cpu
)
809 xcall_deliver((u64
) &xcall_sync_tick
, 0, 0,
810 &cpumask_of_cpu(cpu
));
813 extern unsigned long xcall_call_function
;
815 void arch_send_call_function_ipi(cpumask_t mask
)
817 xcall_deliver((u64
) &xcall_call_function
, 0, 0, &mask
);
820 extern unsigned long xcall_call_function_single
;
822 void arch_send_call_function_single_ipi(int cpu
)
824 xcall_deliver((u64
) &xcall_call_function_single
, 0, 0,
825 &cpumask_of_cpu(cpu
));
828 void smp_call_function_client(int irq
, struct pt_regs
*regs
)
830 clear_softint(1 << irq
);
831 generic_smp_call_function_interrupt();
834 void smp_call_function_single_client(int irq
, struct pt_regs
*regs
)
836 clear_softint(1 << irq
);
837 generic_smp_call_function_single_interrupt();
840 static void tsb_sync(void *info
)
842 struct trap_per_cpu
*tp
= &trap_block
[raw_smp_processor_id()];
843 struct mm_struct
*mm
= info
;
845 /* It is not valid to test "currrent->active_mm == mm" here.
847 * The value of "current" is not changed atomically with
848 * switch_mm(). But that's OK, we just need to check the
849 * current cpu's trap block PGD physical address.
851 if (tp
->pgd_paddr
== __pa(mm
->pgd
))
852 tsb_context_switch(mm
);
855 void smp_tsb_sync(struct mm_struct
*mm
)
857 smp_call_function_mask(mm
->cpu_vm_mask
, tsb_sync
, mm
, 1);
860 extern unsigned long xcall_flush_tlb_mm
;
861 extern unsigned long xcall_flush_tlb_pending
;
862 extern unsigned long xcall_flush_tlb_kernel_range
;
863 extern unsigned long xcall_fetch_glob_regs
;
864 extern unsigned long xcall_receive_signal
;
865 extern unsigned long xcall_new_mmu_context_version
;
867 extern unsigned long xcall_kgdb_capture
;
870 #ifdef DCACHE_ALIASING_POSSIBLE
871 extern unsigned long xcall_flush_dcache_page_cheetah
;
873 extern unsigned long xcall_flush_dcache_page_spitfire
;
875 #ifdef CONFIG_DEBUG_DCFLUSH
876 extern atomic_t dcpage_flushes
;
877 extern atomic_t dcpage_flushes_xcall
;
880 static inline void __local_flush_dcache_page(struct page
*page
)
882 #ifdef DCACHE_ALIASING_POSSIBLE
883 __flush_dcache_page(page_address(page
),
884 ((tlb_type
== spitfire
) &&
885 page_mapping(page
) != NULL
));
887 if (page_mapping(page
) != NULL
&&
888 tlb_type
== spitfire
)
889 __flush_icache_page(__pa(page_address(page
)));
893 void smp_flush_dcache_page_impl(struct page
*page
, int cpu
)
897 if (tlb_type
== hypervisor
)
900 #ifdef CONFIG_DEBUG_DCFLUSH
901 atomic_inc(&dcpage_flushes
);
904 this_cpu
= get_cpu();
906 if (cpu
== this_cpu
) {
907 __local_flush_dcache_page(page
);
908 } else if (cpu_online(cpu
)) {
909 void *pg_addr
= page_address(page
);
912 if (tlb_type
== spitfire
) {
913 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
914 if (page_mapping(page
) != NULL
)
915 data0
|= ((u64
)1 << 32);
916 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
917 #ifdef DCACHE_ALIASING_POSSIBLE
918 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
922 xcall_deliver(data0
, __pa(pg_addr
),
923 (u64
) pg_addr
, &cpumask_of_cpu(cpu
));
924 #ifdef CONFIG_DEBUG_DCFLUSH
925 atomic_inc(&dcpage_flushes_xcall
);
933 void flush_dcache_page_all(struct mm_struct
*mm
, struct page
*page
)
939 if (tlb_type
== hypervisor
)
942 this_cpu
= get_cpu();
944 #ifdef CONFIG_DEBUG_DCFLUSH
945 atomic_inc(&dcpage_flushes
);
948 pg_addr
= page_address(page
);
949 if (tlb_type
== spitfire
) {
950 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
951 if (page_mapping(page
) != NULL
)
952 data0
|= ((u64
)1 << 32);
953 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
954 #ifdef DCACHE_ALIASING_POSSIBLE
955 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
959 xcall_deliver(data0
, __pa(pg_addr
),
960 (u64
) pg_addr
, &cpu_online_map
);
961 #ifdef CONFIG_DEBUG_DCFLUSH
962 atomic_inc(&dcpage_flushes_xcall
);
965 __local_flush_dcache_page(page
);
970 void smp_new_mmu_context_version_client(int irq
, struct pt_regs
*regs
)
972 struct mm_struct
*mm
;
975 clear_softint(1 << irq
);
977 /* See if we need to allocate a new TLB context because
978 * the version of the one we are using is now out of date.
980 mm
= current
->active_mm
;
981 if (unlikely(!mm
|| (mm
== &init_mm
)))
984 spin_lock_irqsave(&mm
->context
.lock
, flags
);
986 if (unlikely(!CTX_VALID(mm
->context
)))
987 get_new_mmu_context(mm
);
989 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
991 load_secondary_context(mm
);
992 __flush_tlb_mm(CTX_HWBITS(mm
->context
),
996 void smp_new_mmu_context_version(void)
998 smp_cross_call(&xcall_new_mmu_context_version
, 0, 0, 0);
1002 void kgdb_roundup_cpus(unsigned long flags
)
1004 smp_cross_call(&xcall_kgdb_capture
, 0, 0, 0);
1008 void smp_fetch_global_regs(void)
1010 smp_cross_call(&xcall_fetch_glob_regs
, 0, 0, 0);
1013 /* We know that the window frames of the user have been flushed
1014 * to the stack before we get here because all callers of us
1015 * are flush_tlb_*() routines, and these run after flush_cache_*()
1016 * which performs the flushw.
1018 * The SMP TLB coherency scheme we use works as follows:
1020 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1021 * space has (potentially) executed on, this is the heuristic
1022 * we use to avoid doing cross calls.
1024 * Also, for flushing from kswapd and also for clones, we
1025 * use cpu_vm_mask as the list of cpus to make run the TLB.
1027 * 2) TLB context numbers are shared globally across all processors
1028 * in the system, this allows us to play several games to avoid
1031 * One invariant is that when a cpu switches to a process, and
1032 * that processes tsk->active_mm->cpu_vm_mask does not have the
1033 * current cpu's bit set, that tlb context is flushed locally.
1035 * If the address space is non-shared (ie. mm->count == 1) we avoid
1036 * cross calls when we want to flush the currently running process's
1037 * tlb state. This is done by clearing all cpu bits except the current
1038 * processor's in current->active_mm->cpu_vm_mask and performing the
1039 * flush locally only. This will force any subsequent cpus which run
1040 * this task to flush the context from the local tlb if the process
1041 * migrates to another cpu (again).
1043 * 3) For shared address spaces (threads) and swapping we bite the
1044 * bullet for most cases and perform the cross call (but only to
1045 * the cpus listed in cpu_vm_mask).
1047 * The performance gain from "optimizing" away the cross call for threads is
1048 * questionable (in theory the big win for threads is the massive sharing of
1049 * address space state across processors).
1052 /* This currently is only used by the hugetlb arch pre-fault
1053 * hook on UltraSPARC-III+ and later when changing the pagesize
1054 * bits of the context register for an address space.
1056 void smp_flush_tlb_mm(struct mm_struct
*mm
)
1058 u32 ctx
= CTX_HWBITS(mm
->context
);
1059 int cpu
= get_cpu();
1061 if (atomic_read(&mm
->mm_users
) == 1) {
1062 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1063 goto local_flush_and_out
;
1066 smp_cross_call_masked(&xcall_flush_tlb_mm
,
1070 local_flush_and_out
:
1071 __flush_tlb_mm(ctx
, SECONDARY_CONTEXT
);
1076 void smp_flush_tlb_pending(struct mm_struct
*mm
, unsigned long nr
, unsigned long *vaddrs
)
1078 u32 ctx
= CTX_HWBITS(mm
->context
);
1079 int cpu
= get_cpu();
1081 if (mm
== current
->active_mm
&& atomic_read(&mm
->mm_users
) == 1)
1082 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1084 smp_cross_call_masked(&xcall_flush_tlb_pending
,
1085 ctx
, nr
, (unsigned long) vaddrs
,
1088 __flush_tlb_pending(ctx
, nr
, vaddrs
);
1093 void smp_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
1096 end
= PAGE_ALIGN(end
);
1098 smp_cross_call(&xcall_flush_tlb_kernel_range
,
1101 __flush_tlb_kernel_range(start
, end
);
1106 /* #define CAPTURE_DEBUG */
1107 extern unsigned long xcall_capture
;
1109 static atomic_t smp_capture_depth
= ATOMIC_INIT(0);
1110 static atomic_t smp_capture_registry
= ATOMIC_INIT(0);
1111 static unsigned long penguins_are_doing_time
;
1113 void smp_capture(void)
1115 int result
= atomic_add_ret(1, &smp_capture_depth
);
1118 int ncpus
= num_online_cpus();
1120 #ifdef CAPTURE_DEBUG
1121 printk("CPU[%d]: Sending penguins to jail...",
1122 smp_processor_id());
1124 penguins_are_doing_time
= 1;
1125 atomic_inc(&smp_capture_registry
);
1126 smp_cross_call(&xcall_capture
, 0, 0, 0);
1127 while (atomic_read(&smp_capture_registry
) != ncpus
)
1129 #ifdef CAPTURE_DEBUG
1135 void smp_release(void)
1137 if (atomic_dec_and_test(&smp_capture_depth
)) {
1138 #ifdef CAPTURE_DEBUG
1139 printk("CPU[%d]: Giving pardon to "
1140 "imprisoned penguins\n",
1141 smp_processor_id());
1143 penguins_are_doing_time
= 0;
1144 membar_safe("#StoreLoad");
1145 atomic_dec(&smp_capture_registry
);
1149 /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1150 * set, so they can service tlb flush xcalls...
1152 extern void prom_world(int);
1154 void smp_penguin_jailcell(int irq
, struct pt_regs
*regs
)
1156 clear_softint(1 << irq
);
1160 __asm__
__volatile__("flushw");
1162 atomic_inc(&smp_capture_registry
);
1163 membar_safe("#StoreLoad");
1164 while (penguins_are_doing_time
)
1166 atomic_dec(&smp_capture_registry
);
1172 /* /proc/profile writes can call this, don't __init it please. */
1173 int setup_profiling_timer(unsigned int multiplier
)
1178 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1182 void __devinit
smp_prepare_boot_cpu(void)
1186 void __init
smp_setup_processor_id(void)
1188 if (tlb_type
== spitfire
)
1189 xcall_deliver_impl
= spitfire_xcall_deliver
;
1190 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1191 xcall_deliver_impl
= cheetah_xcall_deliver
;
1193 xcall_deliver_impl
= hypervisor_xcall_deliver
;
1196 void __devinit
smp_fill_in_sib_core_maps(void)
1200 for_each_present_cpu(i
) {
1203 cpus_clear(cpu_core_map
[i
]);
1204 if (cpu_data(i
).core_id
== 0) {
1205 cpu_set(i
, cpu_core_map
[i
]);
1209 for_each_present_cpu(j
) {
1210 if (cpu_data(i
).core_id
==
1211 cpu_data(j
).core_id
)
1212 cpu_set(j
, cpu_core_map
[i
]);
1216 for_each_present_cpu(i
) {
1219 cpus_clear(per_cpu(cpu_sibling_map
, i
));
1220 if (cpu_data(i
).proc_id
== -1) {
1221 cpu_set(i
, per_cpu(cpu_sibling_map
, i
));
1225 for_each_present_cpu(j
) {
1226 if (cpu_data(i
).proc_id
==
1227 cpu_data(j
).proc_id
)
1228 cpu_set(j
, per_cpu(cpu_sibling_map
, i
));
1233 int __cpuinit
__cpu_up(unsigned int cpu
)
1235 int ret
= smp_boot_one_cpu(cpu
);
1238 cpu_set(cpu
, smp_commenced_mask
);
1239 while (!cpu_isset(cpu
, cpu_online_map
))
1241 if (!cpu_isset(cpu
, cpu_online_map
)) {
1244 /* On SUN4V, writes to %tick and %stick are
1247 if (tlb_type
!= hypervisor
)
1248 smp_synchronize_one_tick(cpu
);
1254 #ifdef CONFIG_HOTPLUG_CPU
1255 void cpu_play_dead(void)
1257 int cpu
= smp_processor_id();
1258 unsigned long pstate
;
1262 if (tlb_type
== hypervisor
) {
1263 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1265 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO
,
1266 tb
->cpu_mondo_pa
, 0);
1267 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO
,
1268 tb
->dev_mondo_pa
, 0);
1269 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR
,
1270 tb
->resum_mondo_pa
, 0);
1271 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR
,
1272 tb
->nonresum_mondo_pa
, 0);
1275 cpu_clear(cpu
, smp_commenced_mask
);
1276 membar_safe("#Sync");
1278 local_irq_disable();
1280 __asm__
__volatile__(
1281 "rdpr %%pstate, %0\n\t"
1282 "wrpr %0, %1, %%pstate"
1290 int __cpu_disable(void)
1292 int cpu
= smp_processor_id();
1296 for_each_cpu_mask(i
, cpu_core_map
[cpu
])
1297 cpu_clear(cpu
, cpu_core_map
[i
]);
1298 cpus_clear(cpu_core_map
[cpu
]);
1300 for_each_cpu_mask(i
, per_cpu(cpu_sibling_map
, cpu
))
1301 cpu_clear(cpu
, per_cpu(cpu_sibling_map
, i
));
1302 cpus_clear(per_cpu(cpu_sibling_map
, cpu
));
1311 /* Make sure no interrupts point to this cpu. */
1316 local_irq_disable();
1319 cpu_clear(cpu
, cpu_online_map
);
1325 void __cpu_die(unsigned int cpu
)
1329 for (i
= 0; i
< 100; i
++) {
1331 if (!cpu_isset(cpu
, smp_commenced_mask
))
1335 if (cpu_isset(cpu
, smp_commenced_mask
)) {
1336 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1338 #if defined(CONFIG_SUN_LDOMS)
1339 unsigned long hv_err
;
1343 hv_err
= sun4v_cpu_stop(cpu
);
1344 if (hv_err
== HV_EOK
) {
1345 cpu_clear(cpu
, cpu_present_map
);
1348 } while (--limit
> 0);
1350 printk(KERN_ERR
"sun4v_cpu_stop() fails err=%lu\n",
1358 void __init
smp_cpus_done(unsigned int max_cpus
)
1362 void smp_send_reschedule(int cpu
)
1364 xcall_deliver((u64
) &xcall_receive_signal
, 0, 0,
1365 &cpumask_of_cpu(cpu
));
1368 void smp_receive_signal_client(int irq
, struct pt_regs
*regs
)
1370 clear_softint(1 << irq
);
1373 /* This is a nop because we capture all other cpus
1374 * anyways when making the PROM active.
1376 void smp_send_stop(void)
1380 unsigned long __per_cpu_base __read_mostly
;
1381 unsigned long __per_cpu_shift __read_mostly
;
1383 EXPORT_SYMBOL(__per_cpu_base
);
1384 EXPORT_SYMBOL(__per_cpu_shift
);
1386 void __init
real_setup_per_cpu_areas(void)
1388 unsigned long paddr
, goal
, size
, i
;
1391 /* Copy section for each CPU (we discard the original) */
1392 goal
= PERCPU_ENOUGH_ROOM
;
1394 __per_cpu_shift
= PAGE_SHIFT
;
1395 for (size
= PAGE_SIZE
; size
< goal
; size
<<= 1UL)
1398 paddr
= lmb_alloc(size
* NR_CPUS
, PAGE_SIZE
);
1400 prom_printf("Cannot allocate per-cpu memory.\n");
1405 __per_cpu_base
= ptr
- __per_cpu_start
;
1407 for (i
= 0; i
< NR_CPUS
; i
++, ptr
+= size
)
1408 memcpy(ptr
, __per_cpu_start
, __per_cpu_end
- __per_cpu_start
);
1410 /* Setup %g5 for the boot cpu. */
1411 __local_per_cpu_offset
= __per_cpu_offset(smp_processor_id());