arch/sparc/kernel/sun4c_irq.c

   1 /*  sun4c_irq.c
   2  *  arch/sparc/kernel/sun4c_irq.c:
   3  *
   4  *  djhr: Hacked out of irq.c into a CPU dependent version.
   5  *
   6  *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
   8  *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
   9  *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/linkage.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/sched.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include "irq.h"
  22
  23 #include <asm/ptrace.h>
  24 #include <asm/processor.h>
  25 #include <asm/system.h>
  26 #include <asm/psr.h>
  27 #include <asm/vaddrs.h>
  28 #include <asm/timer.h>
  29 #include <asm/openprom.h>
  30 #include <asm/oplib.h>
  31 #include <asm/traps.h>
  32 #include <asm/irq.h>
  33 #include <asm/io.h>
  34 #include <asm/sun4paddr.h>
  35 #include <asm/idprom.h>
  36 #include <asm/machines.h>
  37 #include <asm/sbus.h>
  38
  39 #if 0
  40 static struct resource sun4c_timer_eb = { "sun4c_timer" };
  41 static struct resource sun4c_intr_eb = { "sun4c_intr" };
  42 #endif
  43
  44 /*
  45  * Bit field defines for the interrupt registers on various
  46  * Sparc machines.
  47  */
  48
  49 /* The sun4c interrupt register. */
  50 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  51 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  52 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  53 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  54 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  55 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  56 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  57
  58 /* Pointer to the interrupt enable byte
  59  *
  60  * Dave Redman (djhr@tadpole.co.uk)
  61  * What you may not be aware of is that entry.S requires this variable.
  62  *
  63  *  --- linux_trap_nmi_sun4c --
  64  *
  65  * so don't go making it static, like I tried. sigh.
  66  */
  67 unsigned char *interrupt_enable = NULL;
  68
  69 static void sun4c_disable_irq(unsigned int irq_nr)
  70 {
  71         unsigned long flags;
  72         unsigned char current_mask, new_mask;
  73
  74         local_irq_save(flags);
  75         irq_nr &= (NR_IRQS - 1);
  76         current_mask = *interrupt_enable;
  77         switch(irq_nr) {
  78         case 1:
  79                 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
  80                 break;
  81         case 8:
  82                 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
  83                 break;
  84         case 10:
  85                 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
  86                 break;
  87         case 14:
  88                 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
  89                 break;
  90         default:
  91                 local_irq_restore(flags);
  92                 return;
  93         }
  94         *interrupt_enable = new_mask;
  95         local_irq_restore(flags);
  96 }
  97
  98 static void sun4c_enable_irq(unsigned int irq_nr)
  99 {
 100         unsigned long flags;
 101         unsigned char current_mask, new_mask;
 102
 103         local_irq_save(flags);
 104         irq_nr &= (NR_IRQS - 1);
 105         current_mask = *interrupt_enable;
 106         switch(irq_nr) {
 107         case 1:
 108                 new_mask = ((current_mask) | SUN4C_INT_E1);
 109                 break;
 110         case 8:
 111                 new_mask = ((current_mask) | SUN4C_INT_E8);
 112                 break;
 113         case 10:
 114                 new_mask = ((current_mask) | SUN4C_INT_E10);
 115                 break;
 116         case 14:
 117                 new_mask = ((current_mask) | SUN4C_INT_E14);
 118                 break;
 119         default:
 120                 local_irq_restore(flags);
 121                 return;
 122         }
 123         *interrupt_enable = new_mask;
 124         local_irq_restore(flags);
 125 }
 126
 127 #define TIMER_IRQ       10    /* Also at level 14, but we ignore that one. */
 128 #define PROFILE_IRQ     14    /* Level14 ticker.. used by OBP for polling */
 129
 130 volatile struct sun4c_timer_info *sun4c_timers;
 131
 132 #ifdef CONFIG_SUN4
 133 /* This is an ugly hack to work around the
 134    current timer code, and make it work with
 135    the sun4/260 intersil
 136    */
 137 volatile struct sun4c_timer_info sun4_timer;
 138 #endif
 139
 140 static void sun4c_clear_clock_irq(void)
 141 {
 142         volatile unsigned int clear_intr;
 143 #ifdef CONFIG_SUN4
 144         if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
 145           clear_intr = sun4_timer.timer_limit10;
 146         else
 147 #endif
 148         clear_intr = sun4c_timers->timer_limit10;
 149 }
 150
 151 static void sun4c_clear_profile_irq(int cpu)
 152 {
 153         /* Errm.. not sure how to do this.. */
 154 }
 155
 156 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
 157 {
 158         /* Errm.. not sure how to do this.. */
 159 }
 160
 161 static void __init sun4c_init_timers(irq_handler_t counter_fn)
 162 {
 163         int irq;
 164
 165         /* Map the Timer chip, this is implemented in hardware inside
 166          * the cache chip on the sun4c.
 167          */
 168 #ifdef CONFIG_SUN4
 169         if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
 170                 sun4c_timers = &sun4_timer;
 171         else
 172 #endif
 173         sun4c_timers = ioremap(SUN_TIMER_PHYSADDR,
 174             sizeof(struct sun4c_timer_info));
 175
 176         /* Have the level 10 timer tick at 100HZ.  We don't touch the
 177          * level 14 timer limit since we are letting the prom handle
 178          * them until we have a real console driver so L1-A works.
 179          */
 180         sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10);
 181         master_l10_counter = &sun4c_timers->cur_count10;
 182         master_l10_limit = &sun4c_timers->timer_limit10;
 183
 184         irq = request_irq(TIMER_IRQ,
 185                           counter_fn,
 186                           (IRQF_DISABLED | SA_STATIC_ALLOC),
 187                           "timer", NULL);
 188         if (irq) {
 189                 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
 190                 prom_halt();
 191         }
 192
 193 #if 0
 194         /* This does not work on 4/330 */
 195         sun4c_enable_irq(10);
 196 #endif
 197         claim_ticker14(NULL, PROFILE_IRQ, 0);
 198 }
 199
 200 #ifdef CONFIG_SMP
 201 static void sun4c_nop(void) {}
 202 #endif
 203
 204 void __init sun4c_init_IRQ(void)
 205 {
 206         struct linux_prom_registers int_regs[2];
 207         int ie_node;
 208
 209         if (ARCH_SUN4) {
 210                 interrupt_enable = (char *)
 211                     ioremap(sun4_ie_physaddr, PAGE_SIZE);
 212         } else {
 213                 struct resource phyres;
 214
 215                 ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
 216                                         "interrupt-enable");
 217                 if(ie_node == 0)
 218                         panic("Cannot find /interrupt-enable node");
 219
 220                 /* Depending on the "address" property is bad news... */
 221                 interrupt_enable = NULL;
 222                 if (prom_getproperty(ie_node, "reg", (char *) int_regs,
 223                                      sizeof(int_regs)) != -1) {
 224                         memset(&phyres, 0, sizeof(struct resource));
 225                         phyres.flags = int_regs[0].which_io;
 226                         phyres.start = int_regs[0].phys_addr;
 227                         interrupt_enable = (char *) sbus_ioremap(&phyres, 0,
 228                             int_regs[0].reg_size, "sun4c_intr");
 229                 }
 230         }
 231         if (!interrupt_enable)
 232                 panic("Cannot map interrupt_enable");
 233
 234         BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 235         BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 236         BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 237         BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 238         BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
 239         BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
 240         BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
 241         sparc_init_timers = sun4c_init_timers;
 242 #ifdef CONFIG_SMP
 243         BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 244         BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 245         BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
 246 #endif
 247         *interrupt_enable = (SUN4C_INT_ENABLE);
 248         /* Cannot enable interrupts until OBP ticker is disabled. */
 249 }