arch/sparc/kernel/sun4c_irq.c

   1 /*  sun4c_irq.c
   2  *  arch/sparc/kernel/sun4c_irq.c:
   3  *
   4  *  djhr: Hacked out of irq.c into a CPU dependent version.
   5  *
   6  *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
   8  *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
   9  *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/linkage.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/sched.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include "irq.h"
  24
  25 #include <asm/ptrace.h>
  26 #include <asm/processor.h>
  27 #include <asm/system.h>
  28 #include <asm/psr.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/timer.h>
  31 #include <asm/openprom.h>
  32 #include <asm/oplib.h>
  33 #include <asm/traps.h>
  34 #include <asm/irq.h>
  35 #include <asm/io.h>
  36 #include <asm/idprom.h>
  37 #include <asm/machines.h>
  38
  39 /*
  40  * Bit field defines for the interrupt registers on various
  41  * Sparc machines.
  42  */
  43
  44 /* The sun4c interrupt register. */
  45 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  46 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  47 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  48 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  49 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  50 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  51 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  52
  53 /* Pointer to the interrupt enable byte
  54  *
  55  * Dave Redman (djhr@tadpole.co.uk)
  56  * What you may not be aware of is that entry.S requires this variable.
  57  *
  58  *  --- linux_trap_nmi_sun4c --
  59  *
  60  * so don't go making it static, like I tried. sigh.
  61  */
  62 unsigned char *interrupt_enable = NULL;
  63
  64 static void sun4c_disable_irq(unsigned int irq_nr)
  65 {
  66         unsigned long flags;
  67         unsigned char current_mask, new_mask;
  68
  69         local_irq_save(flags);
  70         irq_nr &= (NR_IRQS - 1);
  71         current_mask = *interrupt_enable;
  72         switch(irq_nr) {
  73         case 1:
  74                 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
  75                 break;
  76         case 8:
  77                 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
  78                 break;
  79         case 10:
  80                 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
  81                 break;
  82         case 14:
  83                 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
  84                 break;
  85         default:
  86                 local_irq_restore(flags);
  87                 return;
  88         }
  89         *interrupt_enable = new_mask;
  90         local_irq_restore(flags);
  91 }
  92
  93 static void sun4c_enable_irq(unsigned int irq_nr)
  94 {
  95         unsigned long flags;
  96         unsigned char current_mask, new_mask;
  97
  98         local_irq_save(flags);
  99         irq_nr &= (NR_IRQS - 1);
 100         current_mask = *interrupt_enable;
 101         switch(irq_nr) {
 102         case 1:
 103                 new_mask = ((current_mask) | SUN4C_INT_E1);
 104                 break;
 105         case 8:
 106                 new_mask = ((current_mask) | SUN4C_INT_E8);
 107                 break;
 108         case 10:
 109                 new_mask = ((current_mask) | SUN4C_INT_E10);
 110                 break;
 111         case 14:
 112                 new_mask = ((current_mask) | SUN4C_INT_E14);
 113                 break;
 114         default:
 115                 local_irq_restore(flags);
 116                 return;
 117         }
 118         *interrupt_enable = new_mask;
 119         local_irq_restore(flags);
 120 }
 121
 122 #define TIMER_IRQ       10    /* Also at level 14, but we ignore that one. */
 123 #define PROFILE_IRQ     14    /* Level14 ticker.. used by OBP for polling */
 124
 125 volatile struct sun4c_timer_info *sun4c_timers;
 126
 127 static void sun4c_clear_clock_irq(void)
 128 {
 129         volatile unsigned int clear_intr;
 130
 131         clear_intr = sun4c_timers->timer_limit10;
 132 }
 133
 134 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
 135 {
 136         /* Errm.. not sure how to do this.. */
 137 }
 138
 139 static void __init sun4c_init_timers(irq_handler_t counter_fn)
 140 {
 141         int irq;
 142
 143         /* Map the Timer chip, this is implemented in hardware inside
 144          * the cache chip on the sun4c.
 145          */
 146         sun4c_timers = ioremap(SUN_TIMER_PHYSADDR,
 147             sizeof(struct sun4c_timer_info));
 148
 149         /* Have the level 10 timer tick at 100HZ.  We don't touch the
 150          * level 14 timer limit since we are letting the prom handle
 151          * them until we have a real console driver so L1-A works.
 152          */
 153         sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10);
 154         master_l10_counter = &sun4c_timers->cur_count10;
 155         master_l10_limit = &sun4c_timers->timer_limit10;
 156
 157         irq = request_irq(TIMER_IRQ,
 158                           counter_fn,
 159                           (IRQF_DISABLED | SA_STATIC_ALLOC),
 160                           "timer", NULL);
 161         if (irq) {
 162                 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
 163                 prom_halt();
 164         }
 165
 166         claim_ticker14(NULL, PROFILE_IRQ, 0);
 167 }
 168
 169 #ifdef CONFIG_SMP
 170 static void sun4c_nop(void) {}
 171 #endif
 172
 173 void __init sun4c_init_IRQ(void)
 174 {
 175         struct linux_prom_registers int_regs[2];
 176         int ie_node;
 177         struct resource phyres;
 178
 179         ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
 180                                        "interrupt-enable");
 181         if(ie_node == 0)
 182                 panic("Cannot find /interrupt-enable node");
 183
 184         /* Depending on the "address" property is bad news... */
 185         interrupt_enable = NULL;
 186         if (prom_getproperty(ie_node, "reg", (char *) int_regs,
 187                              sizeof(int_regs)) != -1) {
 188                 memset(&phyres, 0, sizeof(struct resource));
 189                 phyres.flags = int_regs[0].which_io;
 190                 phyres.start = int_regs[0].phys_addr;
 191                 interrupt_enable = (char *) of_ioremap(&phyres, 0,
 192                     int_regs[0].reg_size, "sun4c_intr");
 193         }
 194         if (!interrupt_enable)
 195                 panic("Cannot map interrupt_enable");
 196
 197         BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 198         BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 199         BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 200         BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 201         BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
 202         BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
 203         sparc_init_timers = sun4c_init_timers;
 204 #ifdef CONFIG_SMP
 205         BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 206         BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 207         BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
 208 #endif
 209         *interrupt_enable = (SUN4C_INT_ENABLE);
 210         /* Cannot enable interrupts until OBP ticker is disabled. */
 211 }