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sparc32,sun4m: percpu and global register definitions moved to irq.h
[deliverable/linux.git] / arch / sparc / kernel / sun4m_irq.c
1 /*
2 * sun4m irq support
3 *
4 * djhr: Hacked out of irq.c into a CPU dependent version.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
10 */
11
12 #include <asm/timer.h>
13 #include <asm/traps.h>
14 #include <asm/pgalloc.h>
15 #include <asm/pgtable.h>
16 #include <asm/irq.h>
17 #include <asm/io.h>
18 #include <asm/cacheflush.h>
19
20 #include "irq.h"
21 #include "kernel.h"
22
23 /* Sample sun4m IRQ layout:
24 *
25 * 0x22 - Power
26 * 0x24 - ESP SCSI
27 * 0x26 - Lance ethernet
28 * 0x2b - Floppy
29 * 0x2c - Zilog uart
30 * 0x32 - SBUS level 0
31 * 0x33 - Parallel port, SBUS level 1
32 * 0x35 - SBUS level 2
33 * 0x37 - SBUS level 3
34 * 0x39 - Audio, Graphics card, SBUS level 4
35 * 0x3b - SBUS level 5
36 * 0x3d - SBUS level 6
37 *
38 * Each interrupt source has a mask bit in the interrupt registers.
39 * When the mask bit is set, this blocks interrupt deliver. So you
40 * clear the bit to enable the interrupt.
41 *
42 * Interrupts numbered less than 0x10 are software triggered interrupts
43 * and unused by Linux.
44 *
45 * Interrupt level assignment on sun4m:
46 *
47 * level source
48 * ------------------------------------------------------------
49 * 1 softint-1
50 * 2 softint-2, VME/SBUS level 1
51 * 3 softint-3, VME/SBUS level 2
52 * 4 softint-4, onboard SCSI
53 * 5 softint-5, VME/SBUS level 3
54 * 6 softint-6, onboard ETHERNET
55 * 7 softint-7, VME/SBUS level 4
56 * 8 softint-8, onboard VIDEO
57 * 9 softint-9, VME/SBUS level 5, Module Interrupt
58 * 10 softint-10, system counter/timer
59 * 11 softint-11, VME/SBUS level 6, Floppy
60 * 12 softint-12, Keyboard/Mouse, Serial
61 * 13 softint-13, VME/SBUS level 7, ISDN Audio
62 * 14 softint-14, per-processor counter/timer
63 * 15 softint-15, Asynchronous Errors (broadcast)
64 *
65 * Each interrupt source is masked distinctly in the sun4m interrupt
66 * registers. The PIL level alone is therefore ambiguous, since multiple
67 * interrupt sources map to a single PIL.
68 *
69 * This ambiguity is resolved in the 'intr' property for device nodes
70 * in the OF device tree. Each 'intr' property entry is composed of
71 * two 32-bit words. The first word is the IRQ priority value, which
72 * is what we're intersted in. The second word is the IRQ vector, which
73 * is unused.
74 *
75 * The low 4 bits of the IRQ priority indicate the PIL, and the upper
76 * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
77 * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
78 *
79 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
80 * whereas a value of 0x33 is SBUS level 2. Here are some sample
81 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
82 * Tadpole S3 GX systems.
83 *
84 * esp: 0x24 onboard ESP SCSI
85 * le: 0x26 onboard Lance ETHERNET
86 * p9100: 0x32 SBUS level 1 P9100 video
87 * bpp: 0x33 SBUS level 2 BPP parallel port device
88 * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
89 * SUNW,leo: 0x39 SBUS level 5 LEO video
90 * pcmcia: 0x3b SBUS level 6 PCMCIA controller
91 * uctrl: 0x3b SBUS level 6 UCTRL device
92 * modem: 0x3d SBUS level 7 MODEM
93 * zs: 0x2c onboard keyboard/mouse/serial
94 * floppy: 0x2b onboard Floppy
95 * power: 0x22 onboard power device (XXX unknown mask bit XXX)
96 */
97
98
99 /* Code in entry.S needs to get at these register mappings. */
100 struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
101 struct sun4m_irq_global __iomem *sun4m_irq_global;
102
103 /* Dave Redman (djhr@tadpole.co.uk)
104 * The sun4m interrupt registers.
105 */
106 #define SUN4M_INT_ENABLE 0x80000000
107 #define SUN4M_INT_E14 0x00000080
108 #define SUN4M_INT_E10 0x00080000
109
110 #define SUN4M_HARD_INT(x) (0x000000001 << (x))
111 #define SUN4M_SOFT_INT(x) (0x000010000 << (x))
112
113 #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
114 #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
115 #define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
116 #define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
117 #define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
118 #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
119 #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
120 #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
121 #define SUN4M_INT_REALTIME 0x00080000 /* system timer */
122 #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
123 #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
124 #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
125 #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
126 #define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
127 #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
128 #define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
129
130 #define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
131 SUN4M_INT_M2S_WRITE_ERR | \
132 SUN4M_INT_ECC_ERR | \
133 SUN4M_INT_VME_ERR)
134
135 #define SUN4M_INT_SBUS(x) (1 << (x+7))
136 #define SUN4M_INT_VME(x) (1 << (x))
137
138 /* Interrupt levels used by OBP */
139 #define OBP_INT_LEVEL_SOFT 0x10
140 #define OBP_INT_LEVEL_ONBOARD 0x20
141 #define OBP_INT_LEVEL_SBUS 0x30
142 #define OBP_INT_LEVEL_VME 0x40
143
144 #define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
145 #define SUM4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14)
146
147 static unsigned long irq_mask[0x50] = {
148 /* 0x00 - SMP */
149 0, SUN4M_SOFT_INT(1),
150 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
151 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
152 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
153 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
154 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
155 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
156 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
157 /* 0x10 - soft */
158 0, SUN4M_SOFT_INT(1),
159 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
160 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
161 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
162 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
163 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
164 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
165 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
166 /* 0x20 - onboard */
167 0, 0, 0, 0,
168 SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
169 SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
170 SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
171 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
172 SUN4M_INT_AUDIO, 0, SUN4M_INT_MODULE_ERR,
173 /* 0x30 - sbus */
174 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
175 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
176 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
177 0, SUN4M_INT_SBUS(6), 0, 0,
178 /* 0x40 - vme */
179 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
180 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
181 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
182 0, SUN4M_INT_VME(6), 0, 0
183 };
184
185 static unsigned long sun4m_get_irqmask(unsigned int irq)
186 {
187 unsigned long mask;
188
189 if (irq < 0x50)
190 mask = irq_mask[irq];
191 else
192 mask = 0;
193
194 if (!mask)
195 printk(KERN_ERR "sun4m_get_irqmask: IRQ%d has no valid mask!\n",
196 irq);
197
198 return mask;
199 }
200
201 static void sun4m_disable_irq(unsigned int irq_nr)
202 {
203 unsigned long mask, flags;
204 int cpu = smp_processor_id();
205
206 mask = sun4m_get_irqmask(irq_nr);
207 local_irq_save(flags);
208 if (irq_nr > 15)
209 sbus_writel(mask, &sun4m_irq_global->mask_set);
210 else
211 sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
212 local_irq_restore(flags);
213 }
214
215 static void sun4m_enable_irq(unsigned int irq_nr)
216 {
217 unsigned long mask, flags;
218 int cpu = smp_processor_id();
219
220 /* Dreadful floppy hack. When we use 0x2b instead of
221 * 0x0b the system blows (it starts to whistle!).
222 * So we continue to use 0x0b. Fixme ASAP. --P3
223 */
224 if (irq_nr != 0x0b) {
225 mask = sun4m_get_irqmask(irq_nr);
226 local_irq_save(flags);
227 if (irq_nr > 15)
228 sbus_writel(mask, &sun4m_irq_global->mask_clear);
229 else
230 sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
231 local_irq_restore(flags);
232 } else {
233 local_irq_save(flags);
234 sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
235 local_irq_restore(flags);
236 }
237 }
238
239 static unsigned long cpu_pil_to_imask[16] = {
240 /*0*/ 0x00000000,
241 /*1*/ 0x00000000,
242 /*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
243 /*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
244 /*4*/ SUN4M_INT_SCSI,
245 /*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
246 /*6*/ SUN4M_INT_ETHERNET,
247 /*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
248 /*8*/ SUN4M_INT_VIDEO,
249 /*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
250 /*10*/ SUN4M_INT_REALTIME,
251 /*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
252 /*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
253 /*13*/ SUN4M_INT_SBUS(6) | SUN4M_INT_VME(6) | SUN4M_INT_AUDIO,
254 /*14*/ SUN4M_INT_E14,
255 /*15*/ SUN4M_INT_ERROR,
256 };
257
258 /* We assume the caller has disabled local interrupts when these are called,
259 * or else very bizarre behavior will result.
260 */
261 static void sun4m_disable_pil_irq(unsigned int pil)
262 {
263 sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
264 }
265
266 static void sun4m_enable_pil_irq(unsigned int pil)
267 {
268 sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
269 }
270
271 #ifdef CONFIG_SMP
272 static void sun4m_send_ipi(int cpu, int level)
273 {
274 unsigned long mask = sun4m_get_irqmask(level);
275
276 sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
277 }
278
279 static void sun4m_clear_ipi(int cpu, int level)
280 {
281 unsigned long mask = sun4m_get_irqmask(level);
282
283 sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
284 }
285
286 static void sun4m_set_udt(int cpu)
287 {
288 sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
289 }
290 #endif
291
292 struct sun4m_timer_percpu {
293 u32 l14_limit;
294 u32 l14_count;
295 u32 l14_limit_noclear;
296 u32 user_timer_start_stop;
297 };
298
299 static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
300
301 struct sun4m_timer_global {
302 u32 l10_limit;
303 u32 l10_count;
304 u32 l10_limit_noclear;
305 u32 reserved;
306 u32 timer_config;
307 };
308
309 static struct sun4m_timer_global __iomem *timers_global;
310
311
312 unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
313
314 static void sun4m_clear_clock_irq(void)
315 {
316 sbus_readl(&timers_global->l10_limit);
317 }
318
319 void sun4m_nmi(struct pt_regs *regs)
320 {
321 unsigned long afsr, afar, si;
322
323 printk(KERN_ERR "Aieee: sun4m NMI received!\n");
324 /* XXX HyperSparc hack XXX */
325 __asm__ __volatile__("mov 0x500, %%g1\n\t"
326 "lda [%%g1] 0x4, %0\n\t"
327 "mov 0x600, %%g1\n\t"
328 "lda [%%g1] 0x4, %1\n\t" :
329 "=r" (afsr), "=r" (afar));
330 printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
331 si = sbus_readl(&sun4m_irq_global->pending);
332 printk(KERN_ERR "si=%08lx\n", si);
333 if (si & SUN4M_INT_MODULE_ERR)
334 printk(KERN_ERR "Module async error\n");
335 if (si & SUN4M_INT_M2S_WRITE_ERR)
336 printk(KERN_ERR "MBus/SBus async error\n");
337 if (si & SUN4M_INT_ECC_ERR)
338 printk(KERN_ERR "ECC memory error\n");
339 if (si & SUN4M_INT_VME_ERR)
340 printk(KERN_ERR "VME async error\n");
341 printk(KERN_ERR "you lose buddy boy...\n");
342 show_regs(regs);
343 prom_halt();
344 }
345
346 /* Exported for sun4m_smp.c */
347 void sun4m_clear_profile_irq(int cpu)
348 {
349 sbus_readl(&timers_percpu[cpu]->l14_limit);
350 }
351
352 static void sun4m_load_profile_irq(int cpu, unsigned int limit)
353 {
354 sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
355 }
356
357 static void __init sun4m_init_timers(irq_handler_t counter_fn)
358 {
359 struct device_node *dp = of_find_node_by_name(NULL, "counter");
360 int i, err, len, num_cpu_timers;
361 const u32 *addr;
362
363 if (!dp) {
364 printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
365 return;
366 }
367
368 addr = of_get_property(dp, "address", &len);
369 of_node_put(dp);
370 if (!addr) {
371 printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
372 return;
373 }
374
375 num_cpu_timers = (len / sizeof(u32)) - 1;
376 for (i = 0; i < num_cpu_timers; i++) {
377 timers_percpu[i] = (void __iomem *)
378 (unsigned long) addr[i];
379 }
380 timers_global = (void __iomem *)
381 (unsigned long) addr[num_cpu_timers];
382
383 sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
384
385 master_l10_counter = &timers_global->l10_count;
386
387 err = request_irq(SUN4M_TIMER_IRQ, counter_fn,
388 (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
389 if (err) {
390 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
391 err);
392 return;
393 }
394
395 for (i = 0; i < num_cpu_timers; i++)
396 sbus_writel(0, &timers_percpu[i]->l14_limit);
397 if (num_cpu_timers == 4)
398 sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
399
400 #ifdef CONFIG_SMP
401 {
402 unsigned long flags;
403 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
404
405 /* For SMP we use the level 14 ticker, however the bootup code
406 * has copied the firmware's level 14 vector into the boot cpu's
407 * trap table, we must fix this now or we get squashed.
408 */
409 local_irq_save(flags);
410 trap_table->inst_one = lvl14_save[0];
411 trap_table->inst_two = lvl14_save[1];
412 trap_table->inst_three = lvl14_save[2];
413 trap_table->inst_four = lvl14_save[3];
414 local_flush_cache_all();
415 local_irq_restore(flags);
416 }
417 #endif
418 }
419
420 void __init sun4m_init_IRQ(void)
421 {
422 struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
423 int len, i, mid, num_cpu_iregs;
424 const u32 *addr;
425
426 if (!dp) {
427 printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
428 return;
429 }
430
431 addr = of_get_property(dp, "address", &len);
432 of_node_put(dp);
433 if (!addr) {
434 printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
435 return;
436 }
437
438 num_cpu_iregs = (len / sizeof(u32)) - 1;
439 for (i = 0; i < num_cpu_iregs; i++) {
440 sun4m_irq_percpu[i] = (void __iomem *)
441 (unsigned long) addr[i];
442 }
443 sun4m_irq_global = (void __iomem *)
444 (unsigned long) addr[num_cpu_iregs];
445
446 local_irq_disable();
447
448 sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
449 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
450 sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
451
452 if (num_cpu_iregs == 4)
453 sbus_writel(0, &sun4m_irq_global->interrupt_target);
454
455 BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
456 BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
457 BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
458 BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
459 BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
460 BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
461
462 sparc_irq_config.init_timers = sun4m_init_timers;
463
464 #ifdef CONFIG_SMP
465 BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
466 BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
467 BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
468 #endif
469
470 /* Cannot enable interrupts until OBP ticker is disabled. */
471 }
Linux kernel - Deliverables
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