1 /* linux/arch/sparc/kernel/time.c
3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
6 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
7 * Added support for the intersil on the sun4/4200
9 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
10 * Support for MicroSPARC-IIep, PCI CPU.
12 * This file handles the Sparc specific time handling details.
14 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
15 * "A Kernel Model for Precision Timekeeping" by Dave Mills
17 #include <linux/errno.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/param.h>
22 #include <linux/string.h>
24 #include <linux/interrupt.h>
25 #include <linux/time.h>
26 #include <linux/rtc.h>
27 #include <linux/rtc/m48t59.h>
28 #include <linux/timex.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/init.h>
32 #include <linux/pci.h>
33 #include <linux/ioport.h>
34 #include <linux/profile.h>
36 #include <linux/of_device.h>
37 #include <linux/platform_device.h>
39 #include <asm/oplib.h>
40 #include <asm/timex.h>
41 #include <asm/timer.h>
44 #include <asm/idprom.h>
45 #include <asm/machines.h>
48 #include <asm/irq_regs.h>
49 #include <asm/setup.h>
53 static __cacheline_aligned_in_smp
DEFINE_SEQLOCK(timer_cs_lock
);
54 static __volatile__ u64 timer_cs_internal_counter
= 0;
55 static char timer_cs_enabled
= 0;
57 static struct clock_event_device timer_ce
;
58 static char timer_ce_enabled
= 0;
61 DEFINE_PER_CPU(struct clock_event_device
, sparc32_clockevent
);
64 DEFINE_SPINLOCK(rtc_lock
);
65 EXPORT_SYMBOL(rtc_lock
);
67 static int set_rtc_mmss(unsigned long);
69 unsigned long profile_pc(struct pt_regs
*regs
)
71 extern char __copy_user_begin
[], __copy_user_end
[];
72 extern char __atomic_begin
[], __atomic_end
[];
73 extern char __bzero_begin
[], __bzero_end
[];
75 unsigned long pc
= regs
->pc
;
77 if (in_lock_functions(pc
) ||
78 (pc
>= (unsigned long) __copy_user_begin
&&
79 pc
< (unsigned long) __copy_user_end
) ||
80 (pc
>= (unsigned long) __atomic_begin
&&
81 pc
< (unsigned long) __atomic_end
) ||
82 (pc
>= (unsigned long) __bzero_begin
&&
83 pc
< (unsigned long) __bzero_end
))
84 pc
= regs
->u_regs
[UREG_RETPC
];
88 EXPORT_SYMBOL(profile_pc
);
90 __volatile__
unsigned int *master_l10_counter
;
92 int update_persistent_clock(struct timespec now
)
94 return set_rtc_mmss(now
.tv_sec
);
97 irqreturn_t notrace
timer_interrupt(int dummy
, void *dev_id
)
99 if (timer_cs_enabled
) {
100 write_seqlock(&timer_cs_lock
);
101 timer_cs_internal_counter
++;
103 write_sequnlock(&timer_cs_lock
);
108 if (timer_ce_enabled
)
109 timer_ce
.event_handler(&timer_ce
);
114 static void timer_ce_set_mode(enum clock_event_mode mode
,
115 struct clock_event_device
*evt
)
118 case CLOCK_EVT_MODE_PERIODIC
:
119 case CLOCK_EVT_MODE_RESUME
:
120 timer_ce_enabled
= 1;
122 case CLOCK_EVT_MODE_SHUTDOWN
:
123 timer_ce_enabled
= 0;
131 static __init
void setup_timer_ce(void)
133 struct clock_event_device
*ce
= &timer_ce
;
135 BUG_ON(smp_processor_id() != boot_cpu_id
);
137 ce
->name
= "timer_ce";
139 ce
->features
= CLOCK_EVT_FEAT_PERIODIC
;
140 ce
->set_mode
= timer_ce_set_mode
;
141 ce
->cpumask
= cpu_possible_mask
;
143 ce
->mult
= div_sc(sparc_config
.clock_rate
, NSEC_PER_SEC
,
145 clockevents_register_device(ce
);
148 static unsigned int sbus_cycles_offset(void)
150 unsigned int val
, offset
;
152 val
= *master_l10_counter
;
153 offset
= (val
>> TIMER_VALUE_SHIFT
) & TIMER_VALUE_MASK
;
156 if (val
& TIMER_LIMIT_BIT
)
157 offset
+= sparc_config
.cs_period
;
162 static cycle_t
timer_cs_read(struct clocksource
*cs
)
164 unsigned int seq
, offset
;
168 seq
= read_seqbegin(&timer_cs_lock
);
170 cycles
= timer_cs_internal_counter
;
171 offset
= sparc_config
.get_cycles_offset();
172 } while (read_seqretry(&timer_cs_lock
, seq
));
174 /* Count absolute cycles */
175 cycles
*= sparc_config
.cs_period
;
181 static struct clocksource timer_cs
= {
184 .read
= timer_cs_read
,
185 .mask
= CLOCKSOURCE_MASK(64),
187 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
190 static __init
int setup_timer_cs(void)
192 timer_cs_enabled
= 1;
193 timer_cs
.mult
= clocksource_hz2mult(sparc_config
.clock_rate
,
196 return clocksource_register(&timer_cs
);
200 static void percpu_ce_setup(enum clock_event_mode mode
,
201 struct clock_event_device
*evt
)
203 int cpu
= __first_cpu(evt
->cpumask
);
206 case CLOCK_EVT_MODE_PERIODIC
:
207 load_profile_irq(cpu
, SBUS_CLOCK_RATE
/ HZ
);
209 case CLOCK_EVT_MODE_ONESHOT
:
210 case CLOCK_EVT_MODE_SHUTDOWN
:
211 case CLOCK_EVT_MODE_UNUSED
:
212 load_profile_irq(cpu
, 0);
219 static int percpu_ce_set_next_event(unsigned long delta
,
220 struct clock_event_device
*evt
)
222 int cpu
= __first_cpu(evt
->cpumask
);
223 unsigned int next
= (unsigned int)delta
;
225 load_profile_irq(cpu
, next
);
229 void register_percpu_ce(int cpu
)
231 struct clock_event_device
*ce
= &per_cpu(sparc32_clockevent
, cpu
);
232 unsigned int features
= CLOCK_EVT_FEAT_PERIODIC
;
234 if (sparc_config
.features
& FEAT_L14_ONESHOT
)
235 features
|= CLOCK_EVT_FEAT_ONESHOT
;
237 ce
->name
= "percpu_ce";
239 ce
->features
= features
;
240 ce
->set_mode
= percpu_ce_setup
;
241 ce
->set_next_event
= percpu_ce_set_next_event
;
242 ce
->cpumask
= cpumask_of(cpu
);
244 ce
->mult
= div_sc(sparc_config
.clock_rate
, NSEC_PER_SEC
,
246 ce
->max_delta_ns
= clockevent_delta2ns(sparc_config
.clock_rate
, ce
);
247 ce
->min_delta_ns
= clockevent_delta2ns(100, ce
);
249 clockevents_register_device(ce
);
253 static unsigned char mostek_read_byte(struct device
*dev
, u32 ofs
)
255 struct platform_device
*pdev
= to_platform_device(dev
);
256 struct m48t59_plat_data
*pdata
= pdev
->dev
.platform_data
;
258 return readb(pdata
->ioaddr
+ ofs
);
261 static void mostek_write_byte(struct device
*dev
, u32 ofs
, u8 val
)
263 struct platform_device
*pdev
= to_platform_device(dev
);
264 struct m48t59_plat_data
*pdata
= pdev
->dev
.platform_data
;
266 writeb(val
, pdata
->ioaddr
+ ofs
);
269 static struct m48t59_plat_data m48t59_data
= {
270 .read_byte
= mostek_read_byte
,
271 .write_byte
= mostek_write_byte
,
274 /* resource is set at runtime */
275 static struct platform_device m48t59_rtc
= {
276 .name
= "rtc-m48t59",
280 .platform_data
= &m48t59_data
,
284 static int __devinit
clock_probe(struct platform_device
*op
)
286 struct device_node
*dp
= op
->dev
.of_node
;
287 const char *model
= of_get_property(dp
, "model", NULL
);
292 /* Only the primary RTC has an address property */
293 if (!of_find_property(dp
, "address", NULL
))
296 m48t59_rtc
.resource
= &op
->resource
[0];
297 if (!strcmp(model
, "mk48t02")) {
298 /* Map the clock register io area read-only */
299 m48t59_data
.ioaddr
= of_ioremap(&op
->resource
[0], 0,
301 m48t59_data
.type
= M48T59RTC_TYPE_M48T02
;
302 } else if (!strcmp(model
, "mk48t08")) {
303 m48t59_data
.ioaddr
= of_ioremap(&op
->resource
[0], 0,
305 m48t59_data
.type
= M48T59RTC_TYPE_M48T08
;
309 if (platform_device_register(&m48t59_rtc
) < 0)
310 printk(KERN_ERR
"Registering RTC device failed\n");
315 static struct of_device_id clock_match
[] = {
322 static struct platform_driver clock_driver
= {
323 .probe
= clock_probe
,
326 .owner
= THIS_MODULE
,
327 .of_match_table
= clock_match
,
332 /* Probe for the mostek real time clock chip. */
333 static int __init
clock_init(void)
335 return platform_driver_register(&clock_driver
);
337 /* Must be after subsys_initcall() so that busses are probed. Must
338 * be before device_initcall() because things like the RTC driver
339 * need to see the clock registers.
341 fs_initcall(clock_init
);
343 static void __init
sparc32_late_time_init(void)
345 if (sparc_config
.features
& FEAT_L10_CLOCKEVENT
)
347 if (sparc_config
.features
& FEAT_L10_CLOCKSOURCE
)
350 register_percpu_ce(smp_processor_id());
354 static void __init
sbus_time_init(void)
356 sparc_config
.get_cycles_offset
= sbus_cycles_offset
;
357 sparc_config
.init_timers();
360 void __init
time_init(void)
364 sparc_config
.features
= 0;
365 late_time_init
= sparc32_late_time_init
;
374 static int set_rtc_mmss(unsigned long secs
)
376 struct rtc_device
*rtc
= rtc_class_open("rtc0");
380 err
= rtc_set_mmss(rtc
, secs
);
381 rtc_class_close(rtc
);