arch/sparc/kernel/trampoline_32.S

   1 /*
   2  * trampoline.S: SMP cpu boot-up trampoline code.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/init.h>
   9 #include <asm/head.h>
  10 #include <asm/psr.h>
  11 #include <asm/page.h>
  12 #include <asm/asi.h>
  13 #include <asm/ptrace.h>
  14 #include <asm/vaddrs.h>
  15 #include <asm/contregs.h>
  16 #include <asm/thread_info.h>
  17
  18         .globl sun4m_cpu_startup
  19         .globl sun4d_cpu_startup
  20
  21         __CPUINIT
  22         .align 4
  23
  24 /* When we start up a cpu for the first time it enters this routine.
  25  * This initializes the chip from whatever state the prom left it
  26  * in and sets PIL in %psr to 15, no irqs.
  27  */
  28
  29 sun4m_cpu_startup:
  30 cpu1_startup:
  31         sethi   %hi(trapbase_cpu1), %g3
  32         b       1f
  33          or     %g3, %lo(trapbase_cpu1), %g3
  34
  35 cpu2_startup:
  36         sethi   %hi(trapbase_cpu2), %g3
  37         b       1f
  38          or     %g3, %lo(trapbase_cpu2), %g3
  39
  40 cpu3_startup:
  41         sethi   %hi(trapbase_cpu3), %g3
  42         b       1f
  43          or     %g3, %lo(trapbase_cpu3), %g3
  44
  45 1:
  46         /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
  47         set     (PSR_PIL | PSR_S | PSR_PS), %g1
  48         wr      %g1, 0x0, %psr          ! traps off though
  49         WRITE_PAUSE
  50
  51         /* Our %wim is one behind CWP */
  52         mov     2, %g1
  53         wr      %g1, 0x0, %wim
  54         WRITE_PAUSE
  55
  56         /* This identifies "this cpu". */
  57         wr      %g3, 0x0, %tbr
  58         WRITE_PAUSE
  59
  60         /* Give ourselves a stack and curptr. */
  61         set     current_set, %g5
  62         srl     %g3, 10, %g4
  63         and     %g4, 0xc, %g4
  64         ld      [%g5 + %g4], %g6
  65
  66         sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
  67         or      %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
  68         add     %g6, %sp, %sp
  69
  70         /* Turn on traps (PSR_ET). */
  71         rd      %psr, %g1
  72         wr      %g1, PSR_ET, %psr       ! traps on
  73         WRITE_PAUSE
  74
  75         /* Init our caches, etc. */
  76         set     poke_srmmu, %g5
  77         ld      [%g5], %g5
  78         call    %g5
  79          nop
  80
  81         /* Start this processor. */
  82         call    smp_callin
  83          nop
  84
  85         b,a     smp_panic
  86
  87         .text
  88         .align  4
  89
  90 smp_panic:
  91         call    cpu_panic
  92          nop
  93
  94 /* CPUID in bootbus can be found at PA 0xff0140000 */
  95 #define SUN4D_BOOTBUS_CPUID     0xf0140000
  96
  97         __CPUINIT
  98         .align  4
  99
 100 sun4d_cpu_startup:
 101         /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
 102         set     (PSR_PIL | PSR_S | PSR_PS), %g1
 103         wr      %g1, 0x0, %psr          ! traps off though
 104         WRITE_PAUSE
 105
 106         /* Our %wim is one behind CWP */
 107         mov     2, %g1
 108         wr      %g1, 0x0, %wim
 109         WRITE_PAUSE
 110
 111         /* Set tbr - we use just one trap table. */
 112         set     trapbase, %g1
 113         wr      %g1, 0x0, %tbr
 114         WRITE_PAUSE
 115
 116         /* Get our CPU id out of bootbus */
 117         set     SUN4D_BOOTBUS_CPUID, %g3
 118         lduba   [%g3] ASI_M_CTL, %g3
 119         and     %g3, 0xf8, %g3
 120         srl     %g3, 3, %g1
 121         sta     %g1, [%g0] ASI_M_VIKING_TMP1
 122
 123         /* Give ourselves a stack and curptr. */
 124         set     current_set, %g5
 125         srl     %g3, 1, %g4
 126         ld      [%g5 + %g4], %g6
 127
 128         sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
 129         or      %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
 130         add     %g6, %sp, %sp
 131
 132         /* Turn on traps (PSR_ET). */
 133         rd      %psr, %g1
 134         wr      %g1, PSR_ET, %psr       ! traps on
 135         WRITE_PAUSE
 136
 137         /* Init our caches, etc. */
 138         set     poke_srmmu, %g5
 139         ld      [%g5], %g5
 140         call    %g5
 141          nop
 142
 143         /* Start this processor. */
 144         call    smp_callin
 145          nop
 146
 147         b,a     smp_panic
 148
 149         __CPUINIT
 150         .align  4
 151         .global leon_smp_cpu_startup, smp_penguin_ctable
 152
 153 leon_smp_cpu_startup:
 154
 155         set smp_penguin_ctable,%g1
 156         ld [%g1+4],%g1
 157         srl %g1,4,%g1
 158         set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
 159         sta %g1, [%g5] ASI_LEON_MMUREGS
 160
 161         /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
 162         set     (PSR_PIL | PSR_S | PSR_PS), %g1
 163         wr      %g1, 0x0, %psr          ! traps off though
 164         WRITE_PAUSE
 165
 166         /* Our %wim is one behind CWP */
 167         mov     2, %g1
 168         wr      %g1, 0x0, %wim
 169         WRITE_PAUSE
 170
 171         /* Set tbr - we use just one trap table. */
 172         set     trapbase, %g1
 173         wr      %g1, 0x0, %tbr
 174         WRITE_PAUSE
 175
 176         /* Get our CPU id */
 177         rd     %asr17,%g3
 178
 179         /* Give ourselves a stack and curptr. */
 180         set     current_set, %g5
 181         srl     %g3, 28, %g4
 182         sll     %g4, 2, %g4
 183         ld      [%g5 + %g4], %g6
 184
 185         sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
 186         or      %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
 187         add     %g6, %sp, %sp
 188
 189         /* Turn on traps (PSR_ET). */
 190         rd      %psr, %g1
 191         wr      %g1, PSR_ET, %psr       ! traps on
 192         WRITE_PAUSE
 193
 194         /* Init our caches, etc. */
 195         set     poke_srmmu, %g5
 196         ld      [%g5], %g5
 197         call    %g5
 198          nop
 199
 200         /* Start this processor. */
 201         call    smp_callin
 202          nop
 203
 204         b,a     smp_panic