arch/sparc/kernel/trampoline_64.S

   1 /*
   2  * trampoline.S: Jump start slave processors on sparc64.
   3  *
   4  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #include <linux/init.h>
   8
   9 #include <asm/head.h>
  10 #include <asm/asi.h>
  11 #include <asm/lsu.h>
  12 #include <asm/dcr.h>
  13 #include <asm/dcu.h>
  14 #include <asm/pstate.h>
  15 #include <asm/page.h>
  16 #include <asm/pgtable.h>
  17 #include <asm/spitfire.h>
  18 #include <asm/processor.h>
  19 #include <asm/thread_info.h>
  20 #include <asm/mmu.h>
  21 #include <asm/hypervisor.h>
  22 #include <asm/cpudata.h>
  23
  24         .data
  25         .align  8
  26 call_method:
  27         .asciz  "call-method"
  28         .align  8
  29 itlb_load:
  30         .asciz  "SUNW,itlb-load"
  31         .align  8
  32 dtlb_load:
  33         .asciz  "SUNW,dtlb-load"
  34
  35 #define TRAMP_STACK_SIZE        1024
  36         .align  16
  37 tramp_stack:
  38         .skip   TRAMP_STACK_SIZE
  39
  40         .align          8
  41         .globl          sparc64_cpu_startup, sparc64_cpu_startup_end
  42 sparc64_cpu_startup:
  43         BRANCH_IF_SUN4V(g1, niagara_startup)
  44         BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
  45         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
  46
  47         ba,pt   %xcc, spitfire_startup
  48          nop
  49
  50 cheetah_plus_startup:
  51         /* Preserve OBP chosen DCU and DCR register settings.  */
  52         ba,pt   %xcc, cheetah_generic_startup
  53          nop
  54
  55 cheetah_startup:
  56         mov     DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
  57         wr      %g1, %asr18
  58
  59         sethi   %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
  60         or      %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
  61         sllx    %g5, 32, %g5
  62         or      %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
  63         stxa    %g5, [%g0] ASI_DCU_CONTROL_REG
  64         membar  #Sync
  65         /* fallthru */
  66
  67 cheetah_generic_startup:
  68         mov     TSB_EXTENSION_P, %g3
  69         stxa    %g0, [%g3] ASI_DMMU
  70         stxa    %g0, [%g3] ASI_IMMU
  71         membar  #Sync
  72
  73         mov     TSB_EXTENSION_S, %g3
  74         stxa    %g0, [%g3] ASI_DMMU
  75         membar  #Sync
  76
  77         mov     TSB_EXTENSION_N, %g3
  78         stxa    %g0, [%g3] ASI_DMMU
  79         stxa    %g0, [%g3] ASI_IMMU
  80         membar  #Sync
  81         /* fallthru */
  82
  83 niagara_startup:
  84         /* Disable STICK_INT interrupts. */
  85         sethi           %hi(0x80000000), %g5
  86         sllx            %g5, 32, %g5
  87         wr              %g5, %asr25
  88
  89         ba,pt           %xcc, startup_continue
  90          nop
  91
  92 spitfire_startup:
  93         mov             (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
  94         stxa            %g1, [%g0] ASI_LSU_CONTROL
  95         membar          #Sync
  96
  97 startup_continue:
  98         mov             %o0, %l0
  99         BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
 100
 101         sethi           %hi(0x80000000), %g2
 102         sllx            %g2, 32, %g2
 103         wr              %g2, 0, %tick_cmpr
 104
 105         /* Call OBP by hand to lock KERNBASE into i/d tlbs.
 106          * We lock 'num_kernel_image_mappings' consequetive entries.
 107          */
 108         sethi           %hi(prom_entry_lock), %g2
 109 1:      ldstub          [%g2 + %lo(prom_entry_lock)], %g1
 110         brnz,pn         %g1, 1b
 111          nop
 112
 113         sethi           %hi(p1275buf), %g2
 114         or              %g2, %lo(p1275buf), %g2
 115         ldx             [%g2 + 0x10], %l2
 116         add             %l2, -(192 + 128), %sp
 117         flushw
 118
 119         /* Setup the loop variables:
 120          * %l3: VADDR base
 121          * %l4: TTE base
 122          * %l5: Loop iterator, iterates from 0 to 'num_kernel_image_mappings'
 123          * %l6: Number of TTE entries to map
 124          * %l7: Highest TTE entry number, we count down
 125          */
 126         sethi           %hi(KERNBASE), %l3
 127         sethi           %hi(kern_locked_tte_data), %l4
 128         ldx             [%l4 + %lo(kern_locked_tte_data)], %l4
 129         clr             %l5
 130         sethi           %hi(num_kernel_image_mappings), %l6
 131         lduw            [%l6 + %lo(num_kernel_image_mappings)], %l6
 132         add             %l6, 1, %l6
 133
 134         mov             15, %l7
 135         BRANCH_IF_ANY_CHEETAH(g1,g5,2f)
 136
 137         mov             63, %l7
 138 2:
 139
 140 3:
 141         /* Lock into I-MMU */
 142         sethi           %hi(call_method), %g2
 143         or              %g2, %lo(call_method), %g2
 144         stx             %g2, [%sp + 2047 + 128 + 0x00]
 145         mov             5, %g2
 146         stx             %g2, [%sp + 2047 + 128 + 0x08]
 147         mov             1, %g2
 148         stx             %g2, [%sp + 2047 + 128 + 0x10]
 149         sethi           %hi(itlb_load), %g2
 150         or              %g2, %lo(itlb_load), %g2
 151         stx             %g2, [%sp + 2047 + 128 + 0x18]
 152         sethi           %hi(prom_mmu_ihandle_cache), %g2
 153         lduw            [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
 154         stx             %g2, [%sp + 2047 + 128 + 0x20]
 155
 156         /* Each TTE maps 4MB, convert index to offset.  */
 157         sllx            %l5, 22, %g1
 158
 159         add             %l3, %g1, %g2
 160         stx             %g2, [%sp + 2047 + 128 + 0x28]  ! VADDR
 161         add             %l4, %g1, %g2
 162         stx             %g2, [%sp + 2047 + 128 + 0x30]  ! TTE
 163
 164         /* TTE index is highest minus loop index.  */
 165         sub             %l7, %l5, %g2
 166         stx             %g2, [%sp + 2047 + 128 + 0x38]
 167
 168         sethi           %hi(p1275buf), %g2
 169         or              %g2, %lo(p1275buf), %g2
 170         ldx             [%g2 + 0x08], %o1
 171         call            %o1
 172          add            %sp, (2047 + 128), %o0
 173
 174         /* Lock into D-MMU */
 175         sethi           %hi(call_method), %g2
 176         or              %g2, %lo(call_method), %g2
 177         stx             %g2, [%sp + 2047 + 128 + 0x00]
 178         mov             5, %g2
 179         stx             %g2, [%sp + 2047 + 128 + 0x08]
 180         mov             1, %g2
 181         stx             %g2, [%sp + 2047 + 128 + 0x10]
 182         sethi           %hi(dtlb_load), %g2
 183         or              %g2, %lo(dtlb_load), %g2
 184         stx             %g2, [%sp + 2047 + 128 + 0x18]
 185         sethi           %hi(prom_mmu_ihandle_cache), %g2
 186         lduw            [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
 187         stx             %g2, [%sp + 2047 + 128 + 0x20]
 188
 189         /* Each TTE maps 4MB, convert index to offset.  */
 190         sllx            %l5, 22, %g1
 191
 192         add             %l3, %g1, %g2
 193         stx             %g2, [%sp + 2047 + 128 + 0x28]  ! VADDR
 194         add             %l4, %g1, %g2
 195         stx             %g2, [%sp + 2047 + 128 + 0x30]  ! TTE
 196
 197         /* TTE index is highest minus loop index.  */
 198         sub             %l7, %l5, %g2
 199         stx             %g2, [%sp + 2047 + 128 + 0x38]
 200
 201         sethi           %hi(p1275buf), %g2
 202         or              %g2, %lo(p1275buf), %g2
 203         ldx             [%g2 + 0x08], %o1
 204         call            %o1
 205          add            %sp, (2047 + 128), %o0
 206
 207         add             %l5, 1, %l5
 208         cmp             %l5, %l6
 209         bne,pt          %xcc, 3b
 210          nop
 211
 212         sethi           %hi(prom_entry_lock), %g2
 213         stb             %g0, [%g2 + %lo(prom_entry_lock)]
 214
 215         ba,pt           %xcc, after_lock_tlb
 216          nop
 217
 218 niagara_lock_tlb:
 219         sethi           %hi(KERNBASE), %l3
 220         sethi           %hi(kern_locked_tte_data), %l4
 221         ldx             [%l4 + %lo(kern_locked_tte_data)], %l4
 222         clr             %l5
 223         sethi           %hi(num_kernel_image_mappings), %l6
 224         lduw            [%l6 + %lo(num_kernel_image_mappings)], %l6
 225         add             %l6, 1, %l6
 226
 227 1:
 228         mov             HV_FAST_MMU_MAP_PERM_ADDR, %o5
 229         sllx            %l5, 22, %g2
 230         add             %l3, %g2, %o0
 231         clr             %o1
 232         add             %l4, %g2, %o2
 233         mov             HV_MMU_IMMU, %o3
 234         ta              HV_FAST_TRAP
 235
 236         mov             HV_FAST_MMU_MAP_PERM_ADDR, %o5
 237         sllx            %l5, 22, %g2
 238         add             %l3, %g2, %o0
 239         clr             %o1
 240         add             %l4, %g2, %o2
 241         mov             HV_MMU_DMMU, %o3
 242         ta              HV_FAST_TRAP
 243
 244         add             %l5, 1, %l5
 245         cmp             %l5, %l6
 246         bne,pt          %xcc, 1b
 247          nop
 248
 249 after_lock_tlb:
 250         wrpr            %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
 251         wr              %g0, 0, %fprs
 252
 253         wr              %g0, ASI_P, %asi
 254
 255         mov             PRIMARY_CONTEXT, %g7
 256
 257 661:    stxa            %g0, [%g7] ASI_DMMU
 258         .section        .sun4v_1insn_patch, "ax"
 259         .word           661b
 260         stxa            %g0, [%g7] ASI_MMU
 261         .previous
 262
 263         membar          #Sync
 264         mov             SECONDARY_CONTEXT, %g7
 265
 266 661:    stxa            %g0, [%g7] ASI_DMMU
 267         .section        .sun4v_1insn_patch, "ax"
 268         .word           661b
 269         stxa            %g0, [%g7] ASI_MMU
 270         .previous
 271
 272         membar          #Sync
 273
 274         /* Everything we do here, until we properly take over the
 275          * trap table, must be done with extreme care.  We cannot
 276          * make any references to %g6 (current thread pointer),
 277          * %g4 (current task pointer), or %g5 (base of current cpu's
 278          * per-cpu area) until we properly take over the trap table
 279          * from the firmware and hypervisor.
 280          *
 281          * Get onto temporary stack which is in the locked kernel image.
 282          */
 283         sethi           %hi(tramp_stack), %g1
 284         or              %g1, %lo(tramp_stack), %g1
 285         add             %g1, TRAMP_STACK_SIZE, %g1
 286         sub             %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
 287         mov             0, %fp
 288
 289         /* Put garbage in these registers to trap any access to them.  */
 290         set             0xdeadbeef, %g4
 291         set             0xdeadbeef, %g5
 292         set             0xdeadbeef, %g6
 293
 294         call            init_irqwork_curcpu
 295          nop
 296
 297         sethi           %hi(tlb_type), %g3
 298         lduw            [%g3 + %lo(tlb_type)], %g2
 299         cmp             %g2, 3
 300         bne,pt          %icc, 1f
 301          nop
 302
 303         call            hard_smp_processor_id
 304          nop
 305
 306         call            sun4v_register_mondo_queues
 307          nop
 308
 309 1:      call            init_cur_cpu_trap
 310          ldx            [%l0], %o0
 311
 312         /* Start using proper page size encodings in ctx register.  */
 313         sethi           %hi(sparc64_kern_pri_context), %g3
 314         ldx             [%g3 + %lo(sparc64_kern_pri_context)], %g2
 315         mov             PRIMARY_CONTEXT, %g1
 316
 317 661:    stxa            %g2, [%g1] ASI_DMMU
 318         .section        .sun4v_1insn_patch, "ax"
 319         .word           661b
 320         stxa            %g2, [%g1] ASI_MMU
 321         .previous
 322
 323         membar          #Sync
 324
 325         wrpr            %g0, 0, %wstate
 326
 327         sethi           %hi(prom_entry_lock), %g2
 328 1:      ldstub          [%g2 + %lo(prom_entry_lock)], %g1
 329         brnz,pn         %g1, 1b
 330          nop
 331
 332         /* As a hack, put &init_thread_union into %g6.
 333          * prom_world() loads from here to restore the %asi
 334          * register.
 335          */
 336         sethi           %hi(init_thread_union), %g6
 337         or              %g6, %lo(init_thread_union), %g6
 338
 339         sethi           %hi(is_sun4v), %o0
 340         lduw            [%o0 + %lo(is_sun4v)], %o0
 341         brz,pt          %o0, 2f
 342          nop
 343
 344         TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
 345         add             %g2, TRAP_PER_CPU_FAULT_INFO, %g2
 346         stxa            %g2, [%g0] ASI_SCRATCHPAD
 347
 348         /* Compute physical address:
 349          *
 350          * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
 351          */
 352         sethi           %hi(KERNBASE), %g3
 353         sub             %g2, %g3, %g2
 354         sethi           %hi(kern_base), %g3
 355         ldx             [%g3 + %lo(kern_base)], %g3
 356         add             %g2, %g3, %o1
 357         sethi           %hi(sparc64_ttable_tl0), %o0
 358
 359         set             prom_set_trap_table_name, %g2
 360         stx             %g2, [%sp + 2047 + 128 + 0x00]
 361         mov             2, %g2
 362         stx             %g2, [%sp + 2047 + 128 + 0x08]
 363         mov             0, %g2
 364         stx             %g2, [%sp + 2047 + 128 + 0x10]
 365         stx             %o0, [%sp + 2047 + 128 + 0x18]
 366         stx             %o1, [%sp + 2047 + 128 + 0x20]
 367         sethi           %hi(p1275buf), %g2
 368         or              %g2, %lo(p1275buf), %g2
 369         ldx             [%g2 + 0x08], %o1
 370         call            %o1
 371          add            %sp, (2047 + 128), %o0
 372
 373         ba,pt           %xcc, 3f
 374          nop
 375
 376 2:      sethi           %hi(sparc64_ttable_tl0), %o0
 377         set             prom_set_trap_table_name, %g2
 378         stx             %g2, [%sp + 2047 + 128 + 0x00]
 379         mov             1, %g2
 380         stx             %g2, [%sp + 2047 + 128 + 0x08]
 381         mov             0, %g2
 382         stx             %g2, [%sp + 2047 + 128 + 0x10]
 383         stx             %o0, [%sp + 2047 + 128 + 0x18]
 384         sethi           %hi(p1275buf), %g2
 385         or              %g2, %lo(p1275buf), %g2
 386         ldx             [%g2 + 0x08], %o1
 387         call            %o1
 388          add            %sp, (2047 + 128), %o0
 389
 390 3:      sethi           %hi(prom_entry_lock), %g2
 391         stb             %g0, [%g2 + %lo(prom_entry_lock)]
 392
 393         ldx             [%l0], %g6
 394         ldx             [%g6 + TI_TASK], %g4
 395
 396         mov             1, %g5
 397         sllx            %g5, THREAD_SHIFT, %g5
 398         sub             %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
 399         add             %g6, %g5, %sp
 400         mov             0, %fp
 401
 402         rdpr            %pstate, %o1
 403         or              %o1, PSTATE_IE, %o1
 404         wrpr            %o1, 0, %pstate
 405
 406         call            smp_callin
 407          nop
 408
 409         call            cpu_panic
 410          nop
 411 1:      b,a,pt          %xcc, 1b
 412
 413         .align          8
 414 sparc64_cpu_startup_end: