2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/ioport.h>
26 #include <linux/percpu.h>
27 #include <linux/memblock.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor
[4] __read_mostly
;
57 static unsigned long page_cache4v_flag
;
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
85 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
87 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
89 static unsigned long cpu_pgsz_mask
;
91 #define MAX_BANKS 1024
93 static struct linux_prom64_registers pavail
[MAX_BANKS
];
94 static int pavail_ents
;
96 u64 numa_latency
[MAX_NUMNODES
][MAX_NUMNODES
];
98 static int cmp_p64(const void *a
, const void *b
)
100 const struct linux_prom64_registers
*x
= a
, *y
= b
;
102 if (x
->phys_addr
> y
->phys_addr
)
104 if (x
->phys_addr
< y
->phys_addr
)
109 static void __init
read_obp_memory(const char *property
,
110 struct linux_prom64_registers
*regs
,
113 phandle node
= prom_finddevice("/memory");
114 int prop_size
= prom_getproplen(node
, property
);
117 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
118 if (ents
> MAX_BANKS
) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property
, MAX_BANKS
);
125 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
127 prom_printf("Couldn't get %s property from /memory.\n",
132 /* Sanitize what we got from the firmware, by page aligning
135 for (i
= 0; i
< ents
; i
++) {
136 unsigned long base
, size
;
138 base
= regs
[i
].phys_addr
;
139 size
= regs
[i
].reg_size
;
142 if (base
& ~PAGE_MASK
) {
143 unsigned long new_base
= PAGE_ALIGN(base
);
145 size
-= new_base
- base
;
146 if ((long) size
< 0L)
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
155 memmove(®s
[i
], ®s
[i
+ 1],
156 (ents
- i
- 1) * sizeof(regs
[0]));
161 regs
[i
].phys_addr
= base
;
162 regs
[i
].reg_size
= size
;
167 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly
;
173 unsigned long kern_size __read_mostly
;
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64
;
177 extern unsigned int sparc_ramdisk_image
;
178 extern unsigned int sparc_ramdisk_size
;
180 struct page
*mem_map_zero __read_mostly
;
181 EXPORT_SYMBOL(mem_map_zero
);
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
185 unsigned long sparc64_kern_pri_context __read_mostly
;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
187 unsigned long sparc64_kern_sec_context __read_mostly
;
189 int num_kernel_image_mappings
;
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
198 inline void flush_dcache_page_impl(struct page
*page
)
200 BUG_ON(tlb_type
== hypervisor
);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes
);
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page
),
207 ((tlb_type
== spitfire
) &&
208 page_mapping(page
) != NULL
));
210 if (page_mapping(page
) != NULL
&&
211 tlb_type
== spitfire
)
212 __flush_icache_page(__pa(page_address(page
)));
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 32UL
218 #define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221 #define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
226 unsigned long mask
= this_cpu
;
227 unsigned long non_cpu_bits
;
229 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
230 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
232 __asm__
__volatile__("1:\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
241 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
245 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
247 unsigned long mask
= (1UL << PG_dcache_dirty
);
249 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
263 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
264 "i" (PG_dcache_cpu_mask
),
265 "i" (PG_dcache_cpu_shift
)
269 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
271 unsigned long tsb_addr
= (unsigned long) ent
;
273 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
274 tsb_addr
= __pa(tsb_addr
);
276 __tsb_insert(tsb_addr
, tag
, pte
);
279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
281 static void flush_dcache(unsigned long pfn
)
285 page
= pfn_to_page(pfn
);
287 unsigned long pg_flags
;
289 pg_flags
= page
->flags
;
290 if (pg_flags
& (1UL << PG_dcache_dirty
)) {
291 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
293 int this_cpu
= get_cpu();
295 /* This is just to optimize away some function calls
299 flush_dcache_page_impl(page
);
301 smp_flush_dcache_page_impl(page
, cpu
);
303 clear_dcache_dirty_cpu(page
, cpu
);
310 /* mm->context.lock must be held */
311 static void __update_mmu_tsb_insert(struct mm_struct
*mm
, unsigned long tsb_index
,
312 unsigned long tsb_hash_shift
, unsigned long address
,
315 struct tsb
*tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
321 tsb
+= ((address
>> tsb_hash_shift
) &
322 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
323 tag
= (address
>> 22UL);
324 tsb_insert(tsb
, tag
, tte
);
327 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
328 static inline bool is_hugetlb_pte(pte_t pte
)
330 if ((tlb_type
== hypervisor
&&
331 (pte_val(pte
) & _PAGE_SZALL_4V
) == _PAGE_SZHUGE_4V
) ||
332 (tlb_type
!= hypervisor
&&
333 (pte_val(pte
) & _PAGE_SZALL_4U
) == _PAGE_SZHUGE_4U
))
339 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t
*ptep
)
341 struct mm_struct
*mm
;
345 if (tlb_type
!= hypervisor
) {
346 unsigned long pfn
= pte_pfn(pte
);
354 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
355 if (!pte_accessible(mm
, pte
))
358 spin_lock_irqsave(&mm
->context
.lock
, flags
);
360 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
361 if (mm
->context
.huge_pte_count
&& is_hugetlb_pte(pte
))
362 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
363 address
, pte_val(pte
));
366 __update_mmu_tsb_insert(mm
, MM_TSB_BASE
, PAGE_SHIFT
,
367 address
, pte_val(pte
));
369 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
372 void flush_dcache_page(struct page
*page
)
374 struct address_space
*mapping
;
377 if (tlb_type
== hypervisor
)
380 /* Do not bother with the expensive D-cache flush if it
381 * is merely the zero page. The 'bigcore' testcase in GDB
382 * causes this case to run millions of times.
384 if (page
== ZERO_PAGE(0))
387 this_cpu
= get_cpu();
389 mapping
= page_mapping(page
);
390 if (mapping
&& !mapping_mapped(mapping
)) {
391 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
393 int dirty_cpu
= dcache_dirty_cpu(page
);
395 if (dirty_cpu
== this_cpu
)
397 smp_flush_dcache_page_impl(page
, dirty_cpu
);
399 set_dcache_dirty(page
, this_cpu
);
401 /* We could delay the flush for the !page_mapping
402 * case too. But that case is for exec env/arg
403 * pages and those are %99 certainly going to get
404 * faulted into the tlb (and thus flushed) anyways.
406 flush_dcache_page_impl(page
);
412 EXPORT_SYMBOL(flush_dcache_page
);
414 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
416 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
417 if (tlb_type
== spitfire
) {
420 /* This code only runs on Spitfire cpus so this is
421 * why we can assume _PAGE_PADDR_4U.
423 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
424 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
426 if (kaddr
>= PAGE_OFFSET
)
427 paddr
= kaddr
& mask
;
429 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
430 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
431 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
432 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
434 paddr
= pte_val(*ptep
) & mask
;
436 __flush_icache_page(paddr
);
440 EXPORT_SYMBOL(flush_icache_range
);
442 void mmu_info(struct seq_file
*m
)
444 static const char *pgsz_strings
[] = {
445 "8K", "64K", "512K", "4MB", "32MB",
446 "256MB", "2GB", "16GB",
450 if (tlb_type
== cheetah
)
451 seq_printf(m
, "MMU Type\t: Cheetah\n");
452 else if (tlb_type
== cheetah_plus
)
453 seq_printf(m
, "MMU Type\t: Cheetah+\n");
454 else if (tlb_type
== spitfire
)
455 seq_printf(m
, "MMU Type\t: Spitfire\n");
456 else if (tlb_type
== hypervisor
)
457 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
459 seq_printf(m
, "MMU Type\t: ???\n");
461 seq_printf(m
, "MMU PGSZs\t: ");
463 for (i
= 0; i
< ARRAY_SIZE(pgsz_strings
); i
++) {
464 if (cpu_pgsz_mask
& (1UL << i
)) {
465 seq_printf(m
, "%s%s",
466 printed
? "," : "", pgsz_strings
[i
]);
472 #ifdef CONFIG_DEBUG_DCFLUSH
473 seq_printf(m
, "DCPageFlushes\t: %d\n",
474 atomic_read(&dcpage_flushes
));
476 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
477 atomic_read(&dcpage_flushes_xcall
));
478 #endif /* CONFIG_SMP */
479 #endif /* CONFIG_DEBUG_DCFLUSH */
482 struct linux_prom_translation prom_trans
[512] __read_mostly
;
483 unsigned int prom_trans_ents __read_mostly
;
485 unsigned long kern_locked_tte_data
;
487 /* The obp translations are saved based on 8k pagesize, since obp can
488 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
489 * HI_OBP_ADDRESS range are handled in ktlb.S.
491 static inline int in_obp_range(unsigned long vaddr
)
493 return (vaddr
>= LOW_OBP_ADDRESS
&&
494 vaddr
< HI_OBP_ADDRESS
);
497 static int cmp_ptrans(const void *a
, const void *b
)
499 const struct linux_prom_translation
*x
= a
, *y
= b
;
501 if (x
->virt
> y
->virt
)
503 if (x
->virt
< y
->virt
)
508 /* Read OBP translations property into 'prom_trans[]'. */
509 static void __init
read_obp_translations(void)
511 int n
, node
, ents
, first
, last
, i
;
513 node
= prom_finddevice("/virtual-memory");
514 n
= prom_getproplen(node
, "translations");
515 if (unlikely(n
== 0 || n
== -1)) {
516 prom_printf("prom_mappings: Couldn't get size.\n");
519 if (unlikely(n
> sizeof(prom_trans
))) {
520 prom_printf("prom_mappings: Size %d is too big.\n", n
);
524 if ((n
= prom_getproperty(node
, "translations",
525 (char *)&prom_trans
[0],
526 sizeof(prom_trans
))) == -1) {
527 prom_printf("prom_mappings: Couldn't get property.\n");
531 n
= n
/ sizeof(struct linux_prom_translation
);
535 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
538 /* Now kick out all the non-OBP entries. */
539 for (i
= 0; i
< ents
; i
++) {
540 if (in_obp_range(prom_trans
[i
].virt
))
544 for (; i
< ents
; i
++) {
545 if (!in_obp_range(prom_trans
[i
].virt
))
550 for (i
= 0; i
< (last
- first
); i
++) {
551 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
552 struct linux_prom_translation
*dest
= &prom_trans
[i
];
556 for (; i
< ents
; i
++) {
557 struct linux_prom_translation
*dest
= &prom_trans
[i
];
558 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
561 prom_trans_ents
= last
- first
;
563 if (tlb_type
== spitfire
) {
564 /* Clear diag TTE bits. */
565 for (i
= 0; i
< prom_trans_ents
; i
++)
566 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
569 /* Force execute bit on. */
570 for (i
= 0; i
< prom_trans_ents
; i
++)
571 prom_trans
[i
].data
|= (tlb_type
== hypervisor
?
572 _PAGE_EXEC_4V
: _PAGE_EXEC_4U
);
575 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
579 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
582 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
583 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
588 static unsigned long kern_large_tte(unsigned long paddr
);
590 static void __init
remap_kernel(void)
592 unsigned long phys_page
, tte_vaddr
, tte_data
;
593 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
595 tte_vaddr
= (unsigned long) KERNBASE
;
596 phys_page
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
597 tte_data
= kern_large_tte(phys_page
);
599 kern_locked_tte_data
= tte_data
;
601 /* Now lock us into the TLBs via Hypervisor or OBP. */
602 if (tlb_type
== hypervisor
) {
603 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
604 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
605 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
606 tte_vaddr
+= 0x400000;
607 tte_data
+= 0x400000;
610 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
611 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
612 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
613 tte_vaddr
+= 0x400000;
614 tte_data
+= 0x400000;
616 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
618 if (tlb_type
== cheetah_plus
) {
619 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
620 CTX_CHEETAH_PLUS_NUC
);
621 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
622 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
627 static void __init
inherit_prom_mappings(void)
629 /* Now fixup OBP's idea about where we really are mapped. */
630 printk("Remapping the kernel... ");
635 void prom_world(int enter
)
640 __asm__
__volatile__("flushw");
643 void __flush_dcache_range(unsigned long start
, unsigned long end
)
647 if (tlb_type
== spitfire
) {
650 for (va
= start
; va
< end
; va
+= 32) {
651 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
655 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
658 for (va
= start
; va
< end
; va
+= 32)
659 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
663 "i" (ASI_DCACHE_INVALIDATE
));
666 EXPORT_SYMBOL(__flush_dcache_range
);
668 /* get_new_mmu_context() uses "cache + 1". */
669 DEFINE_SPINLOCK(ctx_alloc_lock
);
670 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
671 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
672 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
673 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
675 /* Caller does TLB context flushing on local CPU if necessary.
676 * The caller also ensures that CTX_VALID(mm->context) is false.
678 * We must be careful about boundary cases so that we never
679 * let the user have CTX 0 (nucleus) or we ever use a CTX
680 * version of zero (and thus NO_CONTEXT would not be caught
681 * by version mis-match tests in mmu_context.h).
683 * Always invoked with interrupts disabled.
685 void get_new_mmu_context(struct mm_struct
*mm
)
687 unsigned long ctx
, new_ctx
;
688 unsigned long orig_pgsz_bits
;
691 spin_lock(&ctx_alloc_lock
);
692 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
693 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
694 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
696 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
697 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
698 if (new_ctx
>= ctx
) {
700 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
703 new_ctx
= CTX_FIRST_VERSION
;
705 /* Don't call memset, for 16 entries that's just
708 mmu_context_bmap
[0] = 3;
709 mmu_context_bmap
[1] = 0;
710 mmu_context_bmap
[2] = 0;
711 mmu_context_bmap
[3] = 0;
712 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
713 mmu_context_bmap
[i
+ 0] = 0;
714 mmu_context_bmap
[i
+ 1] = 0;
715 mmu_context_bmap
[i
+ 2] = 0;
716 mmu_context_bmap
[i
+ 3] = 0;
722 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
723 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
725 tlb_context_cache
= new_ctx
;
726 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
727 spin_unlock(&ctx_alloc_lock
);
729 if (unlikely(new_version
))
730 smp_new_mmu_context_version();
733 static int numa_enabled
= 1;
734 static int numa_debug
;
736 static int __init
early_numa(char *p
)
741 if (strstr(p
, "off"))
744 if (strstr(p
, "debug"))
749 early_param("numa", early_numa
);
751 #define numadbg(f, a...) \
752 do { if (numa_debug) \
753 printk(KERN_INFO f, ## a); \
756 static void __init
find_ramdisk(unsigned long phys_base
)
758 #ifdef CONFIG_BLK_DEV_INITRD
759 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
760 unsigned long ramdisk_image
;
762 /* Older versions of the bootloader only supported a
763 * 32-bit physical address for the ramdisk image
764 * location, stored at sparc_ramdisk_image. Newer
765 * SILO versions set sparc_ramdisk_image to zero and
766 * provide a full 64-bit physical address at
767 * sparc_ramdisk_image64.
769 ramdisk_image
= sparc_ramdisk_image
;
771 ramdisk_image
= sparc_ramdisk_image64
;
773 /* Another bootloader quirk. The bootloader normalizes
774 * the physical address to KERNBASE, so we have to
775 * factor that back out and add in the lowest valid
776 * physical page address to get the true physical address.
778 ramdisk_image
-= KERNBASE
;
779 ramdisk_image
+= phys_base
;
781 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
782 ramdisk_image
, sparc_ramdisk_size
);
784 initrd_start
= ramdisk_image
;
785 initrd_end
= ramdisk_image
+ sparc_ramdisk_size
;
787 memblock_reserve(initrd_start
, sparc_ramdisk_size
);
789 initrd_start
+= PAGE_OFFSET
;
790 initrd_end
+= PAGE_OFFSET
;
795 struct node_mem_mask
{
799 static struct node_mem_mask node_masks
[MAX_NUMNODES
];
800 static int num_node_masks
;
802 #ifdef CONFIG_NEED_MULTIPLE_NODES
804 int numa_cpu_lookup_table
[NR_CPUS
];
805 cpumask_t numa_cpumask_lookup_table
[MAX_NUMNODES
];
807 struct mdesc_mblock
{
810 u64 offset
; /* RA-to-PA */
812 static struct mdesc_mblock
*mblocks
;
813 static int num_mblocks
;
815 static unsigned long ra_to_pa(unsigned long addr
)
819 for (i
= 0; i
< num_mblocks
; i
++) {
820 struct mdesc_mblock
*m
= &mblocks
[i
];
822 if (addr
>= m
->base
&&
823 addr
< (m
->base
+ m
->size
)) {
831 static int find_node(unsigned long addr
)
835 addr
= ra_to_pa(addr
);
836 for (i
= 0; i
< num_node_masks
; i
++) {
837 struct node_mem_mask
*p
= &node_masks
[i
];
839 if ((addr
& p
->mask
) == p
->val
)
842 /* The following condition has been observed on LDOM guests.*/
843 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
844 " rule. Some physical memory will be owned by node 0.");
848 static u64
memblock_nid_range(u64 start
, u64 end
, int *nid
)
850 *nid
= find_node(start
);
852 while (start
< end
) {
853 int n
= find_node(start
);
867 /* This must be invoked after performing all of the necessary
868 * memblock_set_node() calls for 'nid'. We need to be able to get
869 * correct data from get_pfn_range_for_nid().
871 static void __init
allocate_node_data(int nid
)
873 struct pglist_data
*p
;
874 unsigned long start_pfn
, end_pfn
;
875 #ifdef CONFIG_NEED_MULTIPLE_NODES
878 paddr
= memblock_alloc_try_nid(sizeof(struct pglist_data
), SMP_CACHE_BYTES
, nid
);
880 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid
);
883 NODE_DATA(nid
) = __va(paddr
);
884 memset(NODE_DATA(nid
), 0, sizeof(struct pglist_data
));
886 NODE_DATA(nid
)->node_id
= nid
;
891 get_pfn_range_for_nid(nid
, &start_pfn
, &end_pfn
);
892 p
->node_start_pfn
= start_pfn
;
893 p
->node_spanned_pages
= end_pfn
- start_pfn
;
896 static void init_node_masks_nonnuma(void)
898 #ifdef CONFIG_NEED_MULTIPLE_NODES
902 numadbg("Initializing tables for non-numa.\n");
904 node_masks
[0].mask
= node_masks
[0].val
= 0;
907 #ifdef CONFIG_NEED_MULTIPLE_NODES
908 for (i
= 0; i
< NR_CPUS
; i
++)
909 numa_cpu_lookup_table
[i
] = 0;
911 cpumask_setall(&numa_cpumask_lookup_table
[0]);
915 #ifdef CONFIG_NEED_MULTIPLE_NODES
916 struct pglist_data
*node_data
[MAX_NUMNODES
];
918 EXPORT_SYMBOL(numa_cpu_lookup_table
);
919 EXPORT_SYMBOL(numa_cpumask_lookup_table
);
920 EXPORT_SYMBOL(node_data
);
922 struct mdesc_mlgroup
{
928 static struct mdesc_mlgroup
*mlgroups
;
929 static int num_mlgroups
;
931 static int scan_pio_for_cfg_handle(struct mdesc_handle
*md
, u64 pio
,
936 mdesc_for_each_arc(arc
, md
, pio
, MDESC_ARC_TYPE_FWD
) {
937 u64 target
= mdesc_arc_target(md
, arc
);
940 val
= mdesc_get_property(md
, target
,
942 if (val
&& *val
== cfg_handle
)
948 static int scan_arcs_for_cfg_handle(struct mdesc_handle
*md
, u64 grp
,
951 u64 arc
, candidate
, best_latency
= ~(u64
)0;
953 candidate
= MDESC_NODE_NULL
;
954 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
955 u64 target
= mdesc_arc_target(md
, arc
);
956 const char *name
= mdesc_node_name(md
, target
);
959 if (strcmp(name
, "pio-latency-group"))
962 val
= mdesc_get_property(md
, target
, "latency", NULL
);
966 if (*val
< best_latency
) {
972 if (candidate
== MDESC_NODE_NULL
)
975 return scan_pio_for_cfg_handle(md
, candidate
, cfg_handle
);
978 int of_node_to_nid(struct device_node
*dp
)
980 const struct linux_prom64_registers
*regs
;
981 struct mdesc_handle
*md
;
986 /* This is the right thing to do on currently supported
987 * SUN4U NUMA platforms as well, as the PCI controller does
988 * not sit behind any particular memory controller.
993 regs
= of_get_property(dp
, "reg", NULL
);
997 cfg_handle
= (regs
->phys_addr
>> 32UL) & 0x0fffffff;
1003 mdesc_for_each_node_by_name(md
, grp
, "group") {
1004 if (!scan_arcs_for_cfg_handle(md
, grp
, cfg_handle
)) {
1016 static void __init
add_node_ranges(void)
1018 struct memblock_region
*reg
;
1020 for_each_memblock(memory
, reg
) {
1021 unsigned long size
= reg
->size
;
1022 unsigned long start
, end
;
1026 while (start
< end
) {
1027 unsigned long this_end
;
1030 this_end
= memblock_nid_range(start
, end
, &nid
);
1032 numadbg("Setting memblock NUMA node nid[%d] "
1033 "start[%lx] end[%lx]\n",
1034 nid
, start
, this_end
);
1036 memblock_set_node(start
, this_end
- start
,
1037 &memblock
.memory
, nid
);
1043 static int __init
grab_mlgroups(struct mdesc_handle
*md
)
1045 unsigned long paddr
;
1049 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group")
1054 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mlgroup
),
1059 mlgroups
= __va(paddr
);
1060 num_mlgroups
= count
;
1063 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group") {
1064 struct mdesc_mlgroup
*m
= &mlgroups
[count
++];
1069 val
= mdesc_get_property(md
, node
, "latency", NULL
);
1071 val
= mdesc_get_property(md
, node
, "address-match", NULL
);
1073 val
= mdesc_get_property(md
, node
, "address-mask", NULL
);
1076 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1077 "match[%llx] mask[%llx]\n",
1078 count
- 1, m
->node
, m
->latency
, m
->match
, m
->mask
);
1084 static int __init
grab_mblocks(struct mdesc_handle
*md
)
1086 unsigned long paddr
;
1090 mdesc_for_each_node_by_name(md
, node
, "mblock")
1095 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mblock
),
1100 mblocks
= __va(paddr
);
1101 num_mblocks
= count
;
1104 mdesc_for_each_node_by_name(md
, node
, "mblock") {
1105 struct mdesc_mblock
*m
= &mblocks
[count
++];
1108 val
= mdesc_get_property(md
, node
, "base", NULL
);
1110 val
= mdesc_get_property(md
, node
, "size", NULL
);
1112 val
= mdesc_get_property(md
, node
,
1113 "address-congruence-offset", NULL
);
1115 /* The address-congruence-offset property is optional.
1116 * Explicity zero it be identifty this.
1123 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1124 count
- 1, m
->base
, m
->size
, m
->offset
);
1130 static void __init
numa_parse_mdesc_group_cpus(struct mdesc_handle
*md
,
1131 u64 grp
, cpumask_t
*mask
)
1135 cpumask_clear(mask
);
1137 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_BACK
) {
1138 u64 target
= mdesc_arc_target(md
, arc
);
1139 const char *name
= mdesc_node_name(md
, target
);
1142 if (strcmp(name
, "cpu"))
1144 id
= mdesc_get_property(md
, target
, "id", NULL
);
1145 if (*id
< nr_cpu_ids
)
1146 cpumask_set_cpu(*id
, mask
);
1150 static struct mdesc_mlgroup
* __init
find_mlgroup(u64 node
)
1154 for (i
= 0; i
< num_mlgroups
; i
++) {
1155 struct mdesc_mlgroup
*m
= &mlgroups
[i
];
1156 if (m
->node
== node
)
1162 int __node_distance(int from
, int to
)
1164 if ((from
>= MAX_NUMNODES
) || (to
>= MAX_NUMNODES
)) {
1165 pr_warn("Returning default NUMA distance value for %d->%d\n",
1167 return (from
== to
) ? LOCAL_DISTANCE
: REMOTE_DISTANCE
;
1169 return numa_latency
[from
][to
];
1172 static int find_best_numa_node_for_mlgroup(struct mdesc_mlgroup
*grp
)
1176 for (i
= 0; i
< MAX_NUMNODES
; i
++) {
1177 struct node_mem_mask
*n
= &node_masks
[i
];
1179 if ((grp
->mask
== n
->mask
) && (grp
->match
== n
->val
))
1185 static void find_numa_latencies_for_group(struct mdesc_handle
*md
, u64 grp
,
1190 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1192 u64 target
= mdesc_arc_target(md
, arc
);
1193 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1197 tnode
= find_best_numa_node_for_mlgroup(m
);
1198 if (tnode
== MAX_NUMNODES
)
1200 numa_latency
[index
][tnode
] = m
->latency
;
1204 static int __init
numa_attach_mlgroup(struct mdesc_handle
*md
, u64 grp
,
1207 struct mdesc_mlgroup
*candidate
= NULL
;
1208 u64 arc
, best_latency
= ~(u64
)0;
1209 struct node_mem_mask
*n
;
1211 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1212 u64 target
= mdesc_arc_target(md
, arc
);
1213 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1216 if (m
->latency
< best_latency
) {
1218 best_latency
= m
->latency
;
1224 if (num_node_masks
!= index
) {
1225 printk(KERN_ERR
"Inconsistent NUMA state, "
1226 "index[%d] != num_node_masks[%d]\n",
1227 index
, num_node_masks
);
1231 n
= &node_masks
[num_node_masks
++];
1233 n
->mask
= candidate
->mask
;
1234 n
->val
= candidate
->match
;
1236 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1237 index
, n
->mask
, n
->val
, candidate
->latency
);
1242 static int __init
numa_parse_mdesc_group(struct mdesc_handle
*md
, u64 grp
,
1248 numa_parse_mdesc_group_cpus(md
, grp
, &mask
);
1250 for_each_cpu(cpu
, &mask
)
1251 numa_cpu_lookup_table
[cpu
] = index
;
1252 cpumask_copy(&numa_cpumask_lookup_table
[index
], &mask
);
1255 printk(KERN_INFO
"NUMA GROUP[%d]: cpus [ ", index
);
1256 for_each_cpu(cpu
, &mask
)
1261 return numa_attach_mlgroup(md
, grp
, index
);
1264 static int __init
numa_parse_mdesc(void)
1266 struct mdesc_handle
*md
= mdesc_grab();
1267 int i
, j
, err
, count
;
1270 node
= mdesc_node_by_name(md
, MDESC_NODE_NULL
, "latency-groups");
1271 if (node
== MDESC_NODE_NULL
) {
1276 err
= grab_mblocks(md
);
1280 err
= grab_mlgroups(md
);
1285 mdesc_for_each_node_by_name(md
, node
, "group") {
1286 err
= numa_parse_mdesc_group(md
, node
, count
);
1293 mdesc_for_each_node_by_name(md
, node
, "group") {
1294 find_numa_latencies_for_group(md
, node
, count
);
1298 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1299 for (i
= 0; i
< MAX_NUMNODES
; i
++) {
1300 u64 self_latency
= numa_latency
[i
][i
];
1302 for (j
= 0; j
< MAX_NUMNODES
; j
++) {
1303 numa_latency
[i
][j
] =
1304 (numa_latency
[i
][j
] * LOCAL_DISTANCE
) /
1311 for (i
= 0; i
< num_node_masks
; i
++) {
1312 allocate_node_data(i
);
1322 static int __init
numa_parse_jbus(void)
1324 unsigned long cpu
, index
;
1326 /* NUMA node id is encoded in bits 36 and higher, and there is
1327 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1330 for_each_present_cpu(cpu
) {
1331 numa_cpu_lookup_table
[cpu
] = index
;
1332 cpumask_copy(&numa_cpumask_lookup_table
[index
], cpumask_of(cpu
));
1333 node_masks
[index
].mask
= ~((1UL << 36UL) - 1UL);
1334 node_masks
[index
].val
= cpu
<< 36UL;
1338 num_node_masks
= index
;
1342 for (index
= 0; index
< num_node_masks
; index
++) {
1343 allocate_node_data(index
);
1344 node_set_online(index
);
1350 static int __init
numa_parse_sun4u(void)
1352 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1355 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
1356 if ((ver
>> 32UL) == __JALAPENO_ID
||
1357 (ver
>> 32UL) == __SERRANO_ID
)
1358 return numa_parse_jbus();
1363 static int __init
bootmem_init_numa(void)
1368 numadbg("bootmem_init_numa()\n");
1370 /* Some sane defaults for numa latency values */
1371 for (i
= 0; i
< MAX_NUMNODES
; i
++) {
1372 for (j
= 0; j
< MAX_NUMNODES
; j
++)
1373 numa_latency
[i
][j
] = (i
== j
) ?
1374 LOCAL_DISTANCE
: REMOTE_DISTANCE
;
1378 if (tlb_type
== hypervisor
)
1379 err
= numa_parse_mdesc();
1381 err
= numa_parse_sun4u();
1388 static int bootmem_init_numa(void)
1395 static void __init
bootmem_init_nonnuma(void)
1397 unsigned long top_of_ram
= memblock_end_of_DRAM();
1398 unsigned long total_ram
= memblock_phys_mem_size();
1400 numadbg("bootmem_init_nonnuma()\n");
1402 printk(KERN_INFO
"Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1403 top_of_ram
, total_ram
);
1404 printk(KERN_INFO
"Memory hole size: %ldMB\n",
1405 (top_of_ram
- total_ram
) >> 20);
1407 init_node_masks_nonnuma();
1408 memblock_set_node(0, (phys_addr_t
)ULLONG_MAX
, &memblock
.memory
, 0);
1409 allocate_node_data(0);
1413 static unsigned long __init
bootmem_init(unsigned long phys_base
)
1415 unsigned long end_pfn
;
1417 end_pfn
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
1418 max_pfn
= max_low_pfn
= end_pfn
;
1419 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
1421 if (bootmem_init_numa() < 0)
1422 bootmem_init_nonnuma();
1424 /* Dump memblock with node info. */
1425 memblock_dump_all();
1427 /* XXX cpu notifier XXX */
1429 sparse_memory_present_with_active_regions(MAX_NUMNODES
);
1435 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
1436 static int pall_ents __initdata
;
1438 static unsigned long max_phys_bits
= 40;
1440 bool kern_addr_valid(unsigned long addr
)
1447 if ((long)addr
< 0L) {
1448 unsigned long pa
= __pa(addr
);
1450 if ((addr
>> max_phys_bits
) != 0UL)
1453 return pfn_valid(pa
>> PAGE_SHIFT
);
1456 if (addr
>= (unsigned long) KERNBASE
&&
1457 addr
< (unsigned long)&_end
)
1460 pgd
= pgd_offset_k(addr
);
1464 pud
= pud_offset(pgd
, addr
);
1468 if (pud_large(*pud
))
1469 return pfn_valid(pud_pfn(*pud
));
1471 pmd
= pmd_offset(pud
, addr
);
1475 if (pmd_large(*pmd
))
1476 return pfn_valid(pmd_pfn(*pmd
));
1478 pte
= pte_offset_kernel(pmd
, addr
);
1482 return pfn_valid(pte_pfn(*pte
));
1484 EXPORT_SYMBOL(kern_addr_valid
);
1486 static unsigned long __ref
kernel_map_hugepud(unsigned long vstart
,
1490 const unsigned long mask16gb
= (1UL << 34) - 1UL;
1491 u64 pte_val
= vstart
;
1493 /* Each PUD is 8GB */
1494 if ((vstart
& mask16gb
) ||
1495 (vend
- vstart
<= mask16gb
)) {
1496 pte_val
^= kern_linear_pte_xor
[2];
1497 pud_val(*pud
) = pte_val
| _PAGE_PUD_HUGE
;
1499 return vstart
+ PUD_SIZE
;
1502 pte_val
^= kern_linear_pte_xor
[3];
1503 pte_val
|= _PAGE_PUD_HUGE
;
1505 vend
= vstart
+ mask16gb
+ 1UL;
1506 while (vstart
< vend
) {
1507 pud_val(*pud
) = pte_val
;
1509 pte_val
+= PUD_SIZE
;
1516 static bool kernel_can_map_hugepud(unsigned long vstart
, unsigned long vend
,
1519 if (guard
&& !(vstart
& ~PUD_MASK
) && (vend
- vstart
) >= PUD_SIZE
)
1525 static unsigned long __ref
kernel_map_hugepmd(unsigned long vstart
,
1529 const unsigned long mask256mb
= (1UL << 28) - 1UL;
1530 const unsigned long mask2gb
= (1UL << 31) - 1UL;
1531 u64 pte_val
= vstart
;
1533 /* Each PMD is 8MB */
1534 if ((vstart
& mask256mb
) ||
1535 (vend
- vstart
<= mask256mb
)) {
1536 pte_val
^= kern_linear_pte_xor
[0];
1537 pmd_val(*pmd
) = pte_val
| _PAGE_PMD_HUGE
;
1539 return vstart
+ PMD_SIZE
;
1542 if ((vstart
& mask2gb
) ||
1543 (vend
- vstart
<= mask2gb
)) {
1544 pte_val
^= kern_linear_pte_xor
[1];
1545 pte_val
|= _PAGE_PMD_HUGE
;
1546 vend
= vstart
+ mask256mb
+ 1UL;
1548 pte_val
^= kern_linear_pte_xor
[2];
1549 pte_val
|= _PAGE_PMD_HUGE
;
1550 vend
= vstart
+ mask2gb
+ 1UL;
1553 while (vstart
< vend
) {
1554 pmd_val(*pmd
) = pte_val
;
1556 pte_val
+= PMD_SIZE
;
1564 static bool kernel_can_map_hugepmd(unsigned long vstart
, unsigned long vend
,
1567 if (guard
&& !(vstart
& ~PMD_MASK
) && (vend
- vstart
) >= PMD_SIZE
)
1573 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
1574 unsigned long pend
, pgprot_t prot
,
1577 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
1578 unsigned long vend
= PAGE_OFFSET
+ pend
;
1579 unsigned long alloc_bytes
= 0UL;
1581 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
1582 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1587 while (vstart
< vend
) {
1588 unsigned long this_end
, paddr
= __pa(vstart
);
1589 pgd_t
*pgd
= pgd_offset_k(vstart
);
1594 if (pgd_none(*pgd
)) {
1597 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1598 alloc_bytes
+= PAGE_SIZE
;
1599 pgd_populate(&init_mm
, pgd
, new);
1601 pud
= pud_offset(pgd
, vstart
);
1602 if (pud_none(*pud
)) {
1605 if (kernel_can_map_hugepud(vstart
, vend
, use_huge
)) {
1606 vstart
= kernel_map_hugepud(vstart
, vend
, pud
);
1609 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1610 alloc_bytes
+= PAGE_SIZE
;
1611 pud_populate(&init_mm
, pud
, new);
1614 pmd
= pmd_offset(pud
, vstart
);
1615 if (pmd_none(*pmd
)) {
1618 if (kernel_can_map_hugepmd(vstart
, vend
, use_huge
)) {
1619 vstart
= kernel_map_hugepmd(vstart
, vend
, pmd
);
1622 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1623 alloc_bytes
+= PAGE_SIZE
;
1624 pmd_populate_kernel(&init_mm
, pmd
, new);
1627 pte
= pte_offset_kernel(pmd
, vstart
);
1628 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1629 if (this_end
> vend
)
1632 while (vstart
< this_end
) {
1633 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1635 vstart
+= PAGE_SIZE
;
1644 static void __init
flush_all_kernel_tsbs(void)
1648 for (i
= 0; i
< KERNEL_TSB_NENTRIES
; i
++) {
1649 struct tsb
*ent
= &swapper_tsb
[i
];
1651 ent
->tag
= (1UL << TSB_TAG_INVALID_BIT
);
1653 #ifndef CONFIG_DEBUG_PAGEALLOC
1654 for (i
= 0; i
< KERNEL_TSB4M_NENTRIES
; i
++) {
1655 struct tsb
*ent
= &swapper_4m_tsb
[i
];
1657 ent
->tag
= (1UL << TSB_TAG_INVALID_BIT
);
1662 extern unsigned int kvmap_linear_patch
[1];
1664 static void __init
kernel_physical_mapping_init(void)
1666 unsigned long i
, mem_alloced
= 0UL;
1667 bool use_huge
= true;
1669 #ifdef CONFIG_DEBUG_PAGEALLOC
1672 for (i
= 0; i
< pall_ents
; i
++) {
1673 unsigned long phys_start
, phys_end
;
1675 phys_start
= pall
[i
].phys_addr
;
1676 phys_end
= phys_start
+ pall
[i
].reg_size
;
1678 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1679 PAGE_KERNEL
, use_huge
);
1682 printk("Allocated %ld bytes for kernel page tables.\n",
1685 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1686 flushi(&kvmap_linear_patch
[0]);
1688 flush_all_kernel_tsbs();
1693 #ifdef CONFIG_DEBUG_PAGEALLOC
1694 void __kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1696 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1697 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1699 kernel_map_range(phys_start
, phys_end
,
1700 (enable
? PAGE_KERNEL
: __pgprot(0)), false);
1702 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1703 PAGE_OFFSET
+ phys_end
);
1705 /* we should perform an IPI and flush all tlbs,
1706 * but that can deadlock->flush only current cpu.
1708 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1709 PAGE_OFFSET
+ phys_end
);
1713 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1717 for (i
= 0; i
< pavail_ents
; i
++) {
1718 if (pavail
[i
].reg_size
>= size
)
1719 return pavail
[i
].phys_addr
;
1725 unsigned long PAGE_OFFSET
;
1726 EXPORT_SYMBOL(PAGE_OFFSET
);
1728 unsigned long VMALLOC_END
= 0x0000010000000000UL
;
1729 EXPORT_SYMBOL(VMALLOC_END
);
1731 unsigned long sparc64_va_hole_top
= 0xfffff80000000000UL
;
1732 unsigned long sparc64_va_hole_bottom
= 0x0000080000000000UL
;
1734 static void __init
setup_page_offset(void)
1736 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1737 /* Cheetah/Panther support a full 64-bit virtual
1738 * address, so we can use all that our page tables
1741 sparc64_va_hole_top
= 0xfff0000000000000UL
;
1742 sparc64_va_hole_bottom
= 0x0010000000000000UL
;
1745 } else if (tlb_type
== hypervisor
) {
1746 switch (sun4v_chip_type
) {
1747 case SUN4V_CHIP_NIAGARA1
:
1748 case SUN4V_CHIP_NIAGARA2
:
1749 /* T1 and T2 support 48-bit virtual addresses. */
1750 sparc64_va_hole_top
= 0xffff800000000000UL
;
1751 sparc64_va_hole_bottom
= 0x0000800000000000UL
;
1755 case SUN4V_CHIP_NIAGARA3
:
1756 /* T3 supports 48-bit virtual addresses. */
1757 sparc64_va_hole_top
= 0xffff800000000000UL
;
1758 sparc64_va_hole_bottom
= 0x0000800000000000UL
;
1762 case SUN4V_CHIP_NIAGARA4
:
1763 case SUN4V_CHIP_NIAGARA5
:
1764 case SUN4V_CHIP_SPARC64X
:
1765 case SUN4V_CHIP_SPARC_M6
:
1766 /* T4 and later support 52-bit virtual addresses. */
1767 sparc64_va_hole_top
= 0xfff8000000000000UL
;
1768 sparc64_va_hole_bottom
= 0x0008000000000000UL
;
1771 case SUN4V_CHIP_SPARC_M7
:
1772 case SUN4V_CHIP_SPARC_SN
:
1774 /* M7 and later support 52-bit virtual addresses. */
1775 sparc64_va_hole_top
= 0xfff8000000000000UL
;
1776 sparc64_va_hole_bottom
= 0x0008000000000000UL
;
1782 if (max_phys_bits
> MAX_PHYS_ADDRESS_BITS
) {
1783 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1788 PAGE_OFFSET
= sparc64_va_hole_top
;
1789 VMALLOC_END
= ((sparc64_va_hole_bottom
>> 1) +
1790 (sparc64_va_hole_bottom
>> 2));
1792 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1793 PAGE_OFFSET
, max_phys_bits
);
1794 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1795 VMALLOC_START
, VMALLOC_END
);
1796 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1797 VMEMMAP_BASE
, VMEMMAP_BASE
<< 1);
1800 static void __init
tsb_phys_patch(void)
1802 struct tsb_ldquad_phys_patch_entry
*pquad
;
1803 struct tsb_phys_patch_entry
*p
;
1805 pquad
= &__tsb_ldquad_phys_patch
;
1806 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1807 unsigned long addr
= pquad
->addr
;
1809 if (tlb_type
== hypervisor
)
1810 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1812 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1814 __asm__
__volatile__("flush %0"
1821 p
= &__tsb_phys_patch
;
1822 while (p
< &__tsb_phys_patch_end
) {
1823 unsigned long addr
= p
->addr
;
1825 *(unsigned int *) addr
= p
->insn
;
1827 __asm__
__volatile__("flush %0"
1835 /* Don't mark as init, we give this to the Hypervisor. */
1836 #ifndef CONFIG_DEBUG_PAGEALLOC
1837 #define NUM_KTSB_DESCR 2
1839 #define NUM_KTSB_DESCR 1
1841 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1843 /* The swapper TSBs are loaded with a base sequence of:
1845 * sethi %uhi(SYMBOL), REG1
1846 * sethi %hi(SYMBOL), REG2
1847 * or REG1, %ulo(SYMBOL), REG1
1848 * or REG2, %lo(SYMBOL), REG2
1849 * sllx REG1, 32, REG1
1850 * or REG1, REG2, REG1
1852 * When we use physical addressing for the TSB accesses, we patch the
1853 * first four instructions in the above sequence.
1856 static void patch_one_ktsb_phys(unsigned int *start
, unsigned int *end
, unsigned long pa
)
1858 unsigned long high_bits
, low_bits
;
1860 high_bits
= (pa
>> 32) & 0xffffffff;
1861 low_bits
= (pa
>> 0) & 0xffffffff;
1863 while (start
< end
) {
1864 unsigned int *ia
= (unsigned int *)(unsigned long)*start
;
1866 ia
[0] = (ia
[0] & ~0x3fffff) | (high_bits
>> 10);
1867 __asm__
__volatile__("flush %0" : : "r" (ia
));
1869 ia
[1] = (ia
[1] & ~0x3fffff) | (low_bits
>> 10);
1870 __asm__
__volatile__("flush %0" : : "r" (ia
+ 1));
1872 ia
[2] = (ia
[2] & ~0x1fff) | (high_bits
& 0x3ff);
1873 __asm__
__volatile__("flush %0" : : "r" (ia
+ 2));
1875 ia
[3] = (ia
[3] & ~0x1fff) | (low_bits
& 0x3ff);
1876 __asm__
__volatile__("flush %0" : : "r" (ia
+ 3));
1882 static void ktsb_phys_patch(void)
1884 extern unsigned int __swapper_tsb_phys_patch
;
1885 extern unsigned int __swapper_tsb_phys_patch_end
;
1886 unsigned long ktsb_pa
;
1888 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1889 patch_one_ktsb_phys(&__swapper_tsb_phys_patch
,
1890 &__swapper_tsb_phys_patch_end
, ktsb_pa
);
1891 #ifndef CONFIG_DEBUG_PAGEALLOC
1893 extern unsigned int __swapper_4m_tsb_phys_patch
;
1894 extern unsigned int __swapper_4m_tsb_phys_patch_end
;
1895 ktsb_pa
= (kern_base
+
1896 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1897 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch
,
1898 &__swapper_4m_tsb_phys_patch_end
, ktsb_pa
);
1903 static void __init
sun4v_ktsb_init(void)
1905 unsigned long ktsb_pa
;
1907 /* First KTSB for PAGE_SIZE mappings. */
1908 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1910 switch (PAGE_SIZE
) {
1913 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1914 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1918 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1919 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1923 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1924 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1927 case 4 * 1024 * 1024:
1928 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1929 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1933 ktsb_descr
[0].assoc
= 1;
1934 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1935 ktsb_descr
[0].ctx_idx
= 0;
1936 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1937 ktsb_descr
[0].resv
= 0;
1939 #ifndef CONFIG_DEBUG_PAGEALLOC
1940 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1941 ktsb_pa
= (kern_base
+
1942 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1944 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1945 ktsb_descr
[1].pgsz_mask
= ((HV_PGSZ_MASK_4MB
|
1946 HV_PGSZ_MASK_256MB
|
1948 HV_PGSZ_MASK_16GB
) &
1950 ktsb_descr
[1].assoc
= 1;
1951 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1952 ktsb_descr
[1].ctx_idx
= 0;
1953 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1954 ktsb_descr
[1].resv
= 0;
1958 void sun4v_ktsb_register(void)
1960 unsigned long pa
, ret
;
1962 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1964 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
1966 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1967 "errors with %lx\n", pa
, ret
);
1972 static void __init
sun4u_linear_pte_xor_finalize(void)
1974 #ifndef CONFIG_DEBUG_PAGEALLOC
1975 /* This is where we would add Panther support for
1976 * 32MB and 256MB pages.
1981 static void __init
sun4v_linear_pte_xor_finalize(void)
1983 unsigned long pagecv_flag
;
1985 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1986 * enables MCD error. Do not set bit 9 on M7 processor.
1988 switch (sun4v_chip_type
) {
1989 case SUN4V_CHIP_SPARC_M7
:
1990 case SUN4V_CHIP_SPARC_SN
:
1994 pagecv_flag
= _PAGE_CV_4V
;
1997 #ifndef CONFIG_DEBUG_PAGEALLOC
1998 if (cpu_pgsz_mask
& HV_PGSZ_MASK_256MB
) {
1999 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
2001 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| pagecv_flag
|
2002 _PAGE_P_4V
| _PAGE_W_4V
);
2004 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
2007 if (cpu_pgsz_mask
& HV_PGSZ_MASK_2GB
) {
2008 kern_linear_pte_xor
[2] = (_PAGE_VALID
| _PAGE_SZ2GB_4V
) ^
2010 kern_linear_pte_xor
[2] |= (_PAGE_CP_4V
| pagecv_flag
|
2011 _PAGE_P_4V
| _PAGE_W_4V
);
2013 kern_linear_pte_xor
[2] = kern_linear_pte_xor
[1];
2016 if (cpu_pgsz_mask
& HV_PGSZ_MASK_16GB
) {
2017 kern_linear_pte_xor
[3] = (_PAGE_VALID
| _PAGE_SZ16GB_4V
) ^
2019 kern_linear_pte_xor
[3] |= (_PAGE_CP_4V
| pagecv_flag
|
2020 _PAGE_P_4V
| _PAGE_W_4V
);
2022 kern_linear_pte_xor
[3] = kern_linear_pte_xor
[2];
2027 /* paging_init() sets up the page tables */
2029 static unsigned long last_valid_pfn
;
2031 static void sun4u_pgprot_init(void);
2032 static void sun4v_pgprot_init(void);
2034 static phys_addr_t __init
available_memory(void)
2036 phys_addr_t available
= 0ULL;
2037 phys_addr_t pa_start
, pa_end
;
2040 for_each_free_mem_range(i
, NUMA_NO_NODE
, MEMBLOCK_NONE
, &pa_start
,
2042 available
= available
+ (pa_end
- pa_start
);
2047 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2048 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2049 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2050 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2051 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2052 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2054 /* We need to exclude reserved regions. This exclusion will include
2055 * vmlinux and initrd. To be more precise the initrd size could be used to
2056 * compute a new lower limit because it is freed later during initialization.
2058 static void __init
reduce_memory(phys_addr_t limit_ram
)
2060 phys_addr_t avail_ram
= available_memory();
2061 phys_addr_t pa_start
, pa_end
;
2064 if (limit_ram
>= avail_ram
)
2067 for_each_free_mem_range(i
, NUMA_NO_NODE
, MEMBLOCK_NONE
, &pa_start
,
2069 phys_addr_t region_size
= pa_end
- pa_start
;
2070 phys_addr_t clip_start
= pa_start
;
2072 avail_ram
= avail_ram
- region_size
;
2073 /* Are we consuming too much? */
2074 if (avail_ram
< limit_ram
) {
2075 phys_addr_t give_back
= limit_ram
- avail_ram
;
2077 region_size
= region_size
- give_back
;
2078 clip_start
= clip_start
+ give_back
;
2081 memblock_remove(clip_start
, region_size
);
2083 if (avail_ram
<= limit_ram
)
2089 void __init
paging_init(void)
2091 unsigned long end_pfn
, shift
, phys_base
;
2092 unsigned long real_end
, i
;
2095 setup_page_offset();
2097 /* These build time checkes make sure that the dcache_dirty_cpu()
2098 * page->flags usage will work.
2100 * When a page gets marked as dcache-dirty, we store the
2101 * cpu number starting at bit 32 in the page->flags. Also,
2102 * functions like clear_dcache_dirty_cpu use the cpu mask
2103 * in 13-bit signed-immediate instruction fields.
2107 * Page flags must not reach into upper 32 bits that are used
2108 * for the cpu number
2110 BUILD_BUG_ON(NR_PAGEFLAGS
> 32);
2113 * The bit fields placed in the high range must not reach below
2114 * the 32 bit boundary. Otherwise we cannot place the cpu field
2115 * at the 32 bit boundary.
2117 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
2118 ilog2(roundup_pow_of_two(NR_CPUS
)) > 32);
2120 BUILD_BUG_ON(NR_CPUS
> 4096);
2122 kern_base
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
2123 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
2125 /* Invalidate both kernel TSBs. */
2126 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
2127 #ifndef CONFIG_DEBUG_PAGEALLOC
2128 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
2131 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2132 * bit on M7 processor. This is a conflicting usage of the same
2133 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2134 * Detection error on all pages and this will lead to problems
2135 * later. Kernel does not run with MCD enabled and hence rest
2136 * of the required steps to fully configure memory corruption
2137 * detection are not taken. We need to ensure TTE.mcde is not
2138 * set on M7 processor. Compute the value of cacheability
2139 * flag for use later taking this into consideration.
2141 switch (sun4v_chip_type
) {
2142 case SUN4V_CHIP_SPARC_M7
:
2143 case SUN4V_CHIP_SPARC_SN
:
2144 page_cache4v_flag
= _PAGE_CP_4V
;
2147 page_cache4v_flag
= _PAGE_CACHE_4V
;
2151 if (tlb_type
== hypervisor
)
2152 sun4v_pgprot_init();
2154 sun4u_pgprot_init();
2156 if (tlb_type
== cheetah_plus
||
2157 tlb_type
== hypervisor
) {
2162 if (tlb_type
== hypervisor
)
2163 sun4v_patch_tlb_handlers();
2165 /* Find available physical memory...
2167 * Read it twice in order to work around a bug in openfirmware.
2168 * The call to grab this table itself can cause openfirmware to
2169 * allocate memory, which in turn can take away some space from
2170 * the list of available memory. Reading it twice makes sure
2171 * we really do get the final value.
2173 read_obp_translations();
2174 read_obp_memory("reg", &pall
[0], &pall_ents
);
2175 read_obp_memory("available", &pavail
[0], &pavail_ents
);
2176 read_obp_memory("available", &pavail
[0], &pavail_ents
);
2178 phys_base
= 0xffffffffffffffffUL
;
2179 for (i
= 0; i
< pavail_ents
; i
++) {
2180 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
2181 memblock_add(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
2184 memblock_reserve(kern_base
, kern_size
);
2186 find_ramdisk(phys_base
);
2188 if (cmdline_memory_size
)
2189 reduce_memory(cmdline_memory_size
);
2191 memblock_allow_resize();
2192 memblock_dump_all();
2194 set_bit(0, mmu_context_bmap
);
2196 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
2198 real_end
= (unsigned long)_end
;
2199 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << ILOG2_4MB
);
2200 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2201 num_kernel_image_mappings
);
2203 /* Set kernel pgd to upper alias so physical page computations
2206 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
2208 memset(swapper_pg_dir
, 0, sizeof(swapper_pg_dir
));
2210 inherit_prom_mappings();
2212 /* Ok, we can use our TLB miss and window trap handlers safely. */
2217 prom_build_devicetree();
2218 of_populate_present_mask();
2220 of_fill_in_cpu_data();
2223 if (tlb_type
== hypervisor
) {
2225 mdesc_populate_present_mask(cpu_all_mask
);
2227 mdesc_fill_in_cpu_data(cpu_all_mask
);
2229 mdesc_get_page_sizes(cpu_all_mask
, &cpu_pgsz_mask
);
2231 sun4v_linear_pte_xor_finalize();
2234 sun4v_ktsb_register();
2236 unsigned long impl
, ver
;
2238 cpu_pgsz_mask
= (HV_PGSZ_MASK_8K
| HV_PGSZ_MASK_64K
|
2239 HV_PGSZ_MASK_512K
| HV_PGSZ_MASK_4MB
);
2241 __asm__
__volatile__("rdpr %%ver, %0" : "=r" (ver
));
2242 impl
= ((ver
>> 32) & 0xffff);
2243 if (impl
== PANTHER_IMPL
)
2244 cpu_pgsz_mask
|= (HV_PGSZ_MASK_32MB
|
2245 HV_PGSZ_MASK_256MB
);
2247 sun4u_linear_pte_xor_finalize();
2250 /* Flush the TLBs and the 4M TSB so that the updated linear
2251 * pte XOR settings are realized for all mappings.
2254 #ifndef CONFIG_DEBUG_PAGEALLOC
2255 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
2259 /* Setup bootmem... */
2260 last_valid_pfn
= end_pfn
= bootmem_init(phys_base
);
2262 /* Once the OF device tree and MDESC have been setup, we know
2263 * the list of possible cpus. Therefore we can allocate the
2266 for_each_possible_cpu(i
) {
2267 node
= cpu_to_node(i
);
2269 softirq_stack
[i
] = __alloc_bootmem_node(NODE_DATA(node
),
2272 hardirq_stack
[i
] = __alloc_bootmem_node(NODE_DATA(node
),
2277 kernel_physical_mapping_init();
2280 unsigned long max_zone_pfns
[MAX_NR_ZONES
];
2282 memset(max_zone_pfns
, 0, sizeof(max_zone_pfns
));
2284 max_zone_pfns
[ZONE_NORMAL
] = end_pfn
;
2286 free_area_init_nodes(max_zone_pfns
);
2289 printk("Booting Linux...\n");
2292 int page_in_phys_avail(unsigned long paddr
)
2298 for (i
= 0; i
< pavail_ents
; i
++) {
2299 unsigned long start
, end
;
2301 start
= pavail
[i
].phys_addr
;
2302 end
= start
+ pavail
[i
].reg_size
;
2304 if (paddr
>= start
&& paddr
< end
)
2307 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
2309 #ifdef CONFIG_BLK_DEV_INITRD
2310 if (paddr
>= __pa(initrd_start
) &&
2311 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
2318 static void __init
register_page_bootmem_info(void)
2320 #ifdef CONFIG_NEED_MULTIPLE_NODES
2323 for_each_online_node(i
)
2324 if (NODE_DATA(i
)->node_spanned_pages
)
2325 register_page_bootmem_info_node(NODE_DATA(i
));
2328 void __init
mem_init(void)
2330 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
2332 register_page_bootmem_info();
2336 * Set up the zero page, mark it reserved, so that page count
2337 * is not manipulated when freeing the page from user ptes.
2339 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
2340 if (mem_map_zero
== NULL
) {
2341 prom_printf("paging_init: Cannot alloc zero page.\n");
2344 mark_page_reserved(mem_map_zero
);
2346 mem_init_print_info(NULL
);
2348 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
2349 cheetah_ecache_flush_init();
2352 void free_initmem(void)
2354 unsigned long addr
, initend
;
2357 /* If the physical memory maps were trimmed by kernel command
2358 * line options, don't even try freeing this initmem stuff up.
2359 * The kernel image could have been in the trimmed out region
2360 * and if so the freeing below will free invalid page structs.
2362 if (cmdline_memory_size
)
2366 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2368 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
2369 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
2370 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
2374 ((unsigned long) __va(kern_base
)) -
2375 ((unsigned long) KERNBASE
));
2376 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
2379 free_reserved_page(virt_to_page(page
));
2383 #ifdef CONFIG_BLK_DEV_INITRD
2384 void free_initrd_mem(unsigned long start
, unsigned long end
)
2386 free_reserved_area((void *)start
, (void *)end
, POISON_FREE_INITMEM
,
2391 pgprot_t PAGE_KERNEL __read_mostly
;
2392 EXPORT_SYMBOL(PAGE_KERNEL
);
2394 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
2395 pgprot_t PAGE_COPY __read_mostly
;
2397 pgprot_t PAGE_SHARED __read_mostly
;
2398 EXPORT_SYMBOL(PAGE_SHARED
);
2400 unsigned long pg_iobits __read_mostly
;
2402 unsigned long _PAGE_IE __read_mostly
;
2403 EXPORT_SYMBOL(_PAGE_IE
);
2405 unsigned long _PAGE_E __read_mostly
;
2406 EXPORT_SYMBOL(_PAGE_E
);
2408 unsigned long _PAGE_CACHE __read_mostly
;
2409 EXPORT_SYMBOL(_PAGE_CACHE
);
2411 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2412 int __meminit
vmemmap_populate(unsigned long vstart
, unsigned long vend
,
2415 unsigned long pte_base
;
2417 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2418 _PAGE_CP_4U
| _PAGE_CV_4U
|
2419 _PAGE_P_4U
| _PAGE_W_4U
);
2420 if (tlb_type
== hypervisor
)
2421 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2422 page_cache4v_flag
| _PAGE_P_4V
| _PAGE_W_4V
);
2424 pte_base
|= _PAGE_PMD_HUGE
;
2426 vstart
= vstart
& PMD_MASK
;
2427 vend
= ALIGN(vend
, PMD_SIZE
);
2428 for (; vstart
< vend
; vstart
+= PMD_SIZE
) {
2429 pgd_t
*pgd
= pgd_offset_k(vstart
);
2434 if (pgd_none(*pgd
)) {
2435 pud_t
*new = vmemmap_alloc_block(PAGE_SIZE
, node
);
2439 pgd_populate(&init_mm
, pgd
, new);
2442 pud
= pud_offset(pgd
, vstart
);
2443 if (pud_none(*pud
)) {
2444 pmd_t
*new = vmemmap_alloc_block(PAGE_SIZE
, node
);
2448 pud_populate(&init_mm
, pud
, new);
2451 pmd
= pmd_offset(pud
, vstart
);
2453 pte
= pmd_val(*pmd
);
2454 if (!(pte
& _PAGE_VALID
)) {
2455 void *block
= vmemmap_alloc_block(PMD_SIZE
, node
);
2460 pmd_val(*pmd
) = pte_base
| __pa(block
);
2467 void vmemmap_free(unsigned long start
, unsigned long end
)
2470 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2472 static void prot_init_common(unsigned long page_none
,
2473 unsigned long page_shared
,
2474 unsigned long page_copy
,
2475 unsigned long page_readonly
,
2476 unsigned long page_exec_bit
)
2478 PAGE_COPY
= __pgprot(page_copy
);
2479 PAGE_SHARED
= __pgprot(page_shared
);
2481 protection_map
[0x0] = __pgprot(page_none
);
2482 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
2483 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
2484 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
2485 protection_map
[0x4] = __pgprot(page_readonly
);
2486 protection_map
[0x5] = __pgprot(page_readonly
);
2487 protection_map
[0x6] = __pgprot(page_copy
);
2488 protection_map
[0x7] = __pgprot(page_copy
);
2489 protection_map
[0x8] = __pgprot(page_none
);
2490 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
2491 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
2492 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
2493 protection_map
[0xc] = __pgprot(page_readonly
);
2494 protection_map
[0xd] = __pgprot(page_readonly
);
2495 protection_map
[0xe] = __pgprot(page_shared
);
2496 protection_map
[0xf] = __pgprot(page_shared
);
2499 static void __init
sun4u_pgprot_init(void)
2501 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2502 unsigned long page_exec_bit
;
2505 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2506 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2507 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2509 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2510 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2511 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2512 _PAGE_EXEC_4U
| _PAGE_L_4U
);
2514 _PAGE_IE
= _PAGE_IE_4U
;
2515 _PAGE_E
= _PAGE_E_4U
;
2516 _PAGE_CACHE
= _PAGE_CACHE_4U
;
2518 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
2519 __ACCESS_BITS_4U
| _PAGE_E_4U
);
2521 #ifdef CONFIG_DEBUG_PAGEALLOC
2522 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2524 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
2527 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
2528 _PAGE_P_4U
| _PAGE_W_4U
);
2530 for (i
= 1; i
< 4; i
++)
2531 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2533 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
2534 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
2535 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
2538 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
2539 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2540 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
2541 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2542 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2543 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2544 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2546 page_exec_bit
= _PAGE_EXEC_4U
;
2548 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2552 static void __init
sun4v_pgprot_init(void)
2554 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2555 unsigned long page_exec_bit
;
2558 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
2559 page_cache4v_flag
| _PAGE_P_4V
|
2560 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
2562 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
2564 _PAGE_IE
= _PAGE_IE_4V
;
2565 _PAGE_E
= _PAGE_E_4V
;
2566 _PAGE_CACHE
= page_cache4v_flag
;
2568 #ifdef CONFIG_DEBUG_PAGEALLOC
2569 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2571 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
2574 kern_linear_pte_xor
[0] |= (page_cache4v_flag
| _PAGE_P_4V
|
2577 for (i
= 1; i
< 4; i
++)
2578 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2580 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
2581 __ACCESS_BITS_4V
| _PAGE_E_4V
);
2583 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
2584 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
2585 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
2586 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
2588 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| page_cache4v_flag
;
2589 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| page_cache4v_flag
|
2590 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
2591 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| page_cache4v_flag
|
2592 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2593 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| page_cache4v_flag
|
2594 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2596 page_exec_bit
= _PAGE_EXEC_4V
;
2598 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2602 unsigned long pte_sz_bits(unsigned long sz
)
2604 if (tlb_type
== hypervisor
) {
2608 return _PAGE_SZ8K_4V
;
2610 return _PAGE_SZ64K_4V
;
2612 return _PAGE_SZ512K_4V
;
2613 case 4 * 1024 * 1024:
2614 return _PAGE_SZ4MB_4V
;
2620 return _PAGE_SZ8K_4U
;
2622 return _PAGE_SZ64K_4U
;
2624 return _PAGE_SZ512K_4U
;
2625 case 4 * 1024 * 1024:
2626 return _PAGE_SZ4MB_4U
;
2631 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
2635 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
2636 pte_val(pte
) |= (((unsigned long)space
) << 32);
2637 pte_val(pte
) |= pte_sz_bits(page_size
);
2642 static unsigned long kern_large_tte(unsigned long paddr
)
2646 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2647 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
2648 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
2649 if (tlb_type
== hypervisor
)
2650 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2651 page_cache4v_flag
| _PAGE_P_4V
|
2652 _PAGE_EXEC_4V
| _PAGE_W_4V
);
2657 /* If not locked, zap it. */
2658 void __flush_tlb_all(void)
2660 unsigned long pstate
;
2663 __asm__
__volatile__("flushw\n\t"
2664 "rdpr %%pstate, %0\n\t"
2665 "wrpr %0, %1, %%pstate"
2668 if (tlb_type
== hypervisor
) {
2669 sun4v_mmu_demap_all();
2670 } else if (tlb_type
== spitfire
) {
2671 for (i
= 0; i
< 64; i
++) {
2672 /* Spitfire Errata #32 workaround */
2673 /* NOTE: Always runs on spitfire, so no
2674 * cheetah+ page size encodings.
2676 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2680 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2682 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
2683 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2686 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
2687 spitfire_put_dtlb_data(i
, 0x0UL
);
2690 /* Spitfire Errata #32 workaround */
2691 /* NOTE: Always runs on spitfire, so no
2692 * cheetah+ page size encodings.
2694 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2698 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2700 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
2701 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2704 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
2705 spitfire_put_itlb_data(i
, 0x0UL
);
2708 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
2709 cheetah_flush_dtlb_all();
2710 cheetah_flush_itlb_all();
2712 __asm__
__volatile__("wrpr %0, 0, %%pstate"
2716 pte_t
*pte_alloc_one_kernel(struct mm_struct
*mm
,
2717 unsigned long address
)
2719 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
|
2720 __GFP_REPEAT
| __GFP_ZERO
);
2724 pte
= (pte_t
*) page_address(page
);
2729 pgtable_t
pte_alloc_one(struct mm_struct
*mm
,
2730 unsigned long address
)
2732 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
|
2733 __GFP_REPEAT
| __GFP_ZERO
);
2736 if (!pgtable_page_ctor(page
)) {
2737 free_hot_cold_page(page
, 0);
2740 return (pte_t
*) page_address(page
);
2743 void pte_free_kernel(struct mm_struct
*mm
, pte_t
*pte
)
2745 free_page((unsigned long)pte
);
2748 static void __pte_free(pgtable_t pte
)
2750 struct page
*page
= virt_to_page(pte
);
2752 pgtable_page_dtor(page
);
2756 void pte_free(struct mm_struct
*mm
, pgtable_t pte
)
2761 void pgtable_free(void *table
, bool is_page
)
2766 kmem_cache_free(pgtable_cache
, table
);
2769 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2770 void update_mmu_cache_pmd(struct vm_area_struct
*vma
, unsigned long addr
,
2773 unsigned long pte
, flags
;
2774 struct mm_struct
*mm
;
2777 if (!pmd_large(entry
) || !pmd_young(entry
))
2780 pte
= pmd_val(entry
);
2782 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2783 if (!(pte
& _PAGE_VALID
))
2786 /* We are fabricating 8MB pages using 4MB real hw pages. */
2787 pte
|= (addr
& (1UL << REAL_HPAGE_SHIFT
));
2791 spin_lock_irqsave(&mm
->context
.lock
, flags
);
2793 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
)
2794 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
2797 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
2799 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2801 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2802 static void context_reload(void *__data
)
2804 struct mm_struct
*mm
= __data
;
2806 if (mm
== current
->mm
)
2807 load_secondary_context(mm
);
2810 void hugetlb_setup(struct pt_regs
*regs
)
2812 struct mm_struct
*mm
= current
->mm
;
2813 struct tsb_config
*tp
;
2815 if (faulthandler_disabled() || !mm
) {
2816 const struct exception_table_entry
*entry
;
2818 entry
= search_exception_tables(regs
->tpc
);
2820 regs
->tpc
= entry
->fixup
;
2821 regs
->tnpc
= regs
->tpc
+ 4;
2824 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2825 die_if_kernel("HugeTSB in atomic", regs
);
2828 tp
= &mm
->context
.tsb_block
[MM_TSB_HUGE
];
2829 if (likely(tp
->tsb
== NULL
))
2830 tsb_grow(mm
, MM_TSB_HUGE
, 0);
2832 tsb_context_switch(mm
);
2835 /* On UltraSPARC-III+ and later, configure the second half of
2836 * the Data-TLB for huge pages.
2838 if (tlb_type
== cheetah_plus
) {
2841 spin_lock(&ctx_alloc_lock
);
2842 ctx
= mm
->context
.sparc64_ctx_val
;
2843 ctx
&= ~CTX_PGSZ_MASK
;
2844 ctx
|= CTX_PGSZ_BASE
<< CTX_PGSZ0_SHIFT
;
2845 ctx
|= CTX_PGSZ_HUGE
<< CTX_PGSZ1_SHIFT
;
2847 if (ctx
!= mm
->context
.sparc64_ctx_val
) {
2848 /* When changing the page size fields, we
2849 * must perform a context flush so that no
2850 * stale entries match. This flush must
2851 * occur with the original context register
2854 do_flush_tlb_mm(mm
);
2856 /* Reload the context register of all processors
2857 * also executing in this address space.
2859 mm
->context
.sparc64_ctx_val
= ctx
;
2860 on_each_cpu(context_reload
, mm
, 0);
2862 spin_unlock(&ctx_alloc_lock
);
2867 static struct resource code_resource
= {
2868 .name
= "Kernel code",
2869 .flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
2872 static struct resource data_resource
= {
2873 .name
= "Kernel data",
2874 .flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
2877 static struct resource bss_resource
= {
2878 .name
= "Kernel bss",
2879 .flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
2882 static inline resource_size_t
compute_kern_paddr(void *addr
)
2884 return (resource_size_t
) (addr
- KERNBASE
+ kern_base
);
2887 static void __init
kernel_lds_init(void)
2889 code_resource
.start
= compute_kern_paddr(_text
);
2890 code_resource
.end
= compute_kern_paddr(_etext
- 1);
2891 data_resource
.start
= compute_kern_paddr(_etext
);
2892 data_resource
.end
= compute_kern_paddr(_edata
- 1);
2893 bss_resource
.start
= compute_kern_paddr(__bss_start
);
2894 bss_resource
.end
= compute_kern_paddr(_end
- 1);
2897 static int __init
report_memory(void)
2900 struct resource
*res
;
2904 for (i
= 0; i
< pavail_ents
; i
++) {
2905 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
2908 pr_warn("Failed to allocate source.\n");
2912 res
->name
= "System RAM";
2913 res
->start
= pavail
[i
].phys_addr
;
2914 res
->end
= pavail
[i
].phys_addr
+ pavail
[i
].reg_size
- 1;
2915 res
->flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
;
2917 if (insert_resource(&iomem_resource
, res
) < 0) {
2918 pr_warn("Resource insertion failed.\n");
2922 insert_resource(res
, &code_resource
);
2923 insert_resource(res
, &data_resource
);
2924 insert_resource(res
, &bss_resource
);
2929 arch_initcall(report_memory
);
2932 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2934 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2937 void flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
2939 if (start
< HI_OBP_ADDRESS
&& end
> LOW_OBP_ADDRESS
) {
2940 if (start
< LOW_OBP_ADDRESS
) {
2941 flush_tsb_kernel_range(start
, LOW_OBP_ADDRESS
);
2942 do_flush_tlb_kernel_range(start
, LOW_OBP_ADDRESS
);
2944 if (end
> HI_OBP_ADDRESS
) {
2945 flush_tsb_kernel_range(HI_OBP_ADDRESS
, end
);
2946 do_flush_tlb_kernel_range(HI_OBP_ADDRESS
, end
);
2949 flush_tsb_kernel_range(start
, end
);
2950 do_flush_tlb_kernel_range(start
, end
);