2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/ioport.h>
26 #include <linux/percpu.h>
27 #include <linux/memblock.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor
[4] __read_mostly
;
58 /* A bitmap, two bits for every 256MB of physical memory. These two
59 * bits determine what page size we use for kernel linear
60 * translations. They form an index into kern_linear_pte_xor[]. The
61 * value in the indexed slot is XOR'd with the TLB miss virtual
62 * address to form the resulting TTE. The mapping is:
69 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
70 * support 2GB pages, and hopefully future cpus will support the 16GB
71 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
72 * if these larger page sizes are not supported by the cpu.
74 * It would be nice to determine this from the machine description
75 * 'cpu' properties, but we need to have this table setup before the
76 * MDESC is initialized.
79 #ifndef CONFIG_DEBUG_PAGEALLOC
80 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
81 * Space is allocated for this right after the trap table in
82 * arch/sparc64/kernel/head.S
84 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
86 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
88 static unsigned long cpu_pgsz_mask
;
90 #define MAX_BANKS 1024
92 static struct linux_prom64_registers pavail
[MAX_BANKS
];
93 static int pavail_ents
;
95 static int cmp_p64(const void *a
, const void *b
)
97 const struct linux_prom64_registers
*x
= a
, *y
= b
;
99 if (x
->phys_addr
> y
->phys_addr
)
101 if (x
->phys_addr
< y
->phys_addr
)
106 static void __init
read_obp_memory(const char *property
,
107 struct linux_prom64_registers
*regs
,
110 phandle node
= prom_finddevice("/memory");
111 int prop_size
= prom_getproplen(node
, property
);
114 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
115 if (ents
> MAX_BANKS
) {
116 prom_printf("The machine has more %s property entries than "
117 "this kernel can support (%d).\n",
118 property
, MAX_BANKS
);
122 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
124 prom_printf("Couldn't get %s property from /memory.\n",
129 /* Sanitize what we got from the firmware, by page aligning
132 for (i
= 0; i
< ents
; i
++) {
133 unsigned long base
, size
;
135 base
= regs
[i
].phys_addr
;
136 size
= regs
[i
].reg_size
;
139 if (base
& ~PAGE_MASK
) {
140 unsigned long new_base
= PAGE_ALIGN(base
);
142 size
-= new_base
- base
;
143 if ((long) size
< 0L)
148 /* If it is empty, simply get rid of it.
149 * This simplifies the logic of the other
150 * functions that process these arrays.
152 memmove(®s
[i
], ®s
[i
+ 1],
153 (ents
- i
- 1) * sizeof(regs
[0]));
158 regs
[i
].phys_addr
= base
;
159 regs
[i
].reg_size
= size
;
164 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
168 /* Kernel physical address base and size in bytes. */
169 unsigned long kern_base __read_mostly
;
170 unsigned long kern_size __read_mostly
;
172 /* Initial ramdisk setup */
173 extern unsigned long sparc_ramdisk_image64
;
174 extern unsigned int sparc_ramdisk_image
;
175 extern unsigned int sparc_ramdisk_size
;
177 struct page
*mem_map_zero __read_mostly
;
178 EXPORT_SYMBOL(mem_map_zero
);
180 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
182 unsigned long sparc64_kern_pri_context __read_mostly
;
183 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
184 unsigned long sparc64_kern_sec_context __read_mostly
;
186 int num_kernel_image_mappings
;
188 #ifdef CONFIG_DEBUG_DCFLUSH
189 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
191 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
195 inline void flush_dcache_page_impl(struct page
*page
)
197 BUG_ON(tlb_type
== hypervisor
);
198 #ifdef CONFIG_DEBUG_DCFLUSH
199 atomic_inc(&dcpage_flushes
);
202 #ifdef DCACHE_ALIASING_POSSIBLE
203 __flush_dcache_page(page_address(page
),
204 ((tlb_type
== spitfire
) &&
205 page_mapping(page
) != NULL
));
207 if (page_mapping(page
) != NULL
&&
208 tlb_type
== spitfire
)
209 __flush_icache_page(__pa(page_address(page
)));
213 #define PG_dcache_dirty PG_arch_1
214 #define PG_dcache_cpu_shift 32UL
215 #define PG_dcache_cpu_mask \
216 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
218 #define dcache_dirty_cpu(page) \
219 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
221 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
223 unsigned long mask
= this_cpu
;
224 unsigned long non_cpu_bits
;
226 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
227 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
229 __asm__
__volatile__("1:\n\t"
231 "and %%g7, %1, %%g1\n\t"
232 "or %%g1, %0, %%g1\n\t"
233 "casx [%2], %%g7, %%g1\n\t"
235 "bne,pn %%xcc, 1b\n\t"
238 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
242 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
244 unsigned long mask
= (1UL << PG_dcache_dirty
);
246 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
249 "srlx %%g7, %4, %%g1\n\t"
250 "and %%g1, %3, %%g1\n\t"
252 "bne,pn %%icc, 2f\n\t"
253 " andn %%g7, %1, %%g1\n\t"
254 "casx [%2], %%g7, %%g1\n\t"
256 "bne,pn %%xcc, 1b\n\t"
260 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
261 "i" (PG_dcache_cpu_mask
),
262 "i" (PG_dcache_cpu_shift
)
266 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
268 unsigned long tsb_addr
= (unsigned long) ent
;
270 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
271 tsb_addr
= __pa(tsb_addr
);
273 __tsb_insert(tsb_addr
, tag
, pte
);
276 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
278 static void flush_dcache(unsigned long pfn
)
282 page
= pfn_to_page(pfn
);
284 unsigned long pg_flags
;
286 pg_flags
= page
->flags
;
287 if (pg_flags
& (1UL << PG_dcache_dirty
)) {
288 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
290 int this_cpu
= get_cpu();
292 /* This is just to optimize away some function calls
296 flush_dcache_page_impl(page
);
298 smp_flush_dcache_page_impl(page
, cpu
);
300 clear_dcache_dirty_cpu(page
, cpu
);
307 /* mm->context.lock must be held */
308 static void __update_mmu_tsb_insert(struct mm_struct
*mm
, unsigned long tsb_index
,
309 unsigned long tsb_hash_shift
, unsigned long address
,
312 struct tsb
*tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
318 tsb
+= ((address
>> tsb_hash_shift
) &
319 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
320 tag
= (address
>> 22UL);
321 tsb_insert(tsb
, tag
, tte
);
324 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
325 static inline bool is_hugetlb_pte(pte_t pte
)
327 if ((tlb_type
== hypervisor
&&
328 (pte_val(pte
) & _PAGE_SZALL_4V
) == _PAGE_SZHUGE_4V
) ||
329 (tlb_type
!= hypervisor
&&
330 (pte_val(pte
) & _PAGE_SZALL_4U
) == _PAGE_SZHUGE_4U
))
336 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t
*ptep
)
338 struct mm_struct
*mm
;
342 if (tlb_type
!= hypervisor
) {
343 unsigned long pfn
= pte_pfn(pte
);
351 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
352 if (!pte_accessible(mm
, pte
))
355 spin_lock_irqsave(&mm
->context
.lock
, flags
);
357 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
358 if (mm
->context
.huge_pte_count
&& is_hugetlb_pte(pte
))
359 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
360 address
, pte_val(pte
));
363 __update_mmu_tsb_insert(mm
, MM_TSB_BASE
, PAGE_SHIFT
,
364 address
, pte_val(pte
));
366 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
369 void flush_dcache_page(struct page
*page
)
371 struct address_space
*mapping
;
374 if (tlb_type
== hypervisor
)
377 /* Do not bother with the expensive D-cache flush if it
378 * is merely the zero page. The 'bigcore' testcase in GDB
379 * causes this case to run millions of times.
381 if (page
== ZERO_PAGE(0))
384 this_cpu
= get_cpu();
386 mapping
= page_mapping(page
);
387 if (mapping
&& !mapping_mapped(mapping
)) {
388 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
390 int dirty_cpu
= dcache_dirty_cpu(page
);
392 if (dirty_cpu
== this_cpu
)
394 smp_flush_dcache_page_impl(page
, dirty_cpu
);
396 set_dcache_dirty(page
, this_cpu
);
398 /* We could delay the flush for the !page_mapping
399 * case too. But that case is for exec env/arg
400 * pages and those are %99 certainly going to get
401 * faulted into the tlb (and thus flushed) anyways.
403 flush_dcache_page_impl(page
);
409 EXPORT_SYMBOL(flush_dcache_page
);
411 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
413 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
414 if (tlb_type
== spitfire
) {
417 /* This code only runs on Spitfire cpus so this is
418 * why we can assume _PAGE_PADDR_4U.
420 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
421 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
423 if (kaddr
>= PAGE_OFFSET
)
424 paddr
= kaddr
& mask
;
426 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
427 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
428 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
429 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
431 paddr
= pte_val(*ptep
) & mask
;
433 __flush_icache_page(paddr
);
437 EXPORT_SYMBOL(flush_icache_range
);
439 void mmu_info(struct seq_file
*m
)
441 static const char *pgsz_strings
[] = {
442 "8K", "64K", "512K", "4MB", "32MB",
443 "256MB", "2GB", "16GB",
447 if (tlb_type
== cheetah
)
448 seq_printf(m
, "MMU Type\t: Cheetah\n");
449 else if (tlb_type
== cheetah_plus
)
450 seq_printf(m
, "MMU Type\t: Cheetah+\n");
451 else if (tlb_type
== spitfire
)
452 seq_printf(m
, "MMU Type\t: Spitfire\n");
453 else if (tlb_type
== hypervisor
)
454 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
456 seq_printf(m
, "MMU Type\t: ???\n");
458 seq_printf(m
, "MMU PGSZs\t: ");
460 for (i
= 0; i
< ARRAY_SIZE(pgsz_strings
); i
++) {
461 if (cpu_pgsz_mask
& (1UL << i
)) {
462 seq_printf(m
, "%s%s",
463 printed
? "," : "", pgsz_strings
[i
]);
469 #ifdef CONFIG_DEBUG_DCFLUSH
470 seq_printf(m
, "DCPageFlushes\t: %d\n",
471 atomic_read(&dcpage_flushes
));
473 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
474 atomic_read(&dcpage_flushes_xcall
));
475 #endif /* CONFIG_SMP */
476 #endif /* CONFIG_DEBUG_DCFLUSH */
479 struct linux_prom_translation prom_trans
[512] __read_mostly
;
480 unsigned int prom_trans_ents __read_mostly
;
482 unsigned long kern_locked_tte_data
;
484 /* The obp translations are saved based on 8k pagesize, since obp can
485 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
486 * HI_OBP_ADDRESS range are handled in ktlb.S.
488 static inline int in_obp_range(unsigned long vaddr
)
490 return (vaddr
>= LOW_OBP_ADDRESS
&&
491 vaddr
< HI_OBP_ADDRESS
);
494 static int cmp_ptrans(const void *a
, const void *b
)
496 const struct linux_prom_translation
*x
= a
, *y
= b
;
498 if (x
->virt
> y
->virt
)
500 if (x
->virt
< y
->virt
)
505 /* Read OBP translations property into 'prom_trans[]'. */
506 static void __init
read_obp_translations(void)
508 int n
, node
, ents
, first
, last
, i
;
510 node
= prom_finddevice("/virtual-memory");
511 n
= prom_getproplen(node
, "translations");
512 if (unlikely(n
== 0 || n
== -1)) {
513 prom_printf("prom_mappings: Couldn't get size.\n");
516 if (unlikely(n
> sizeof(prom_trans
))) {
517 prom_printf("prom_mappings: Size %d is too big.\n", n
);
521 if ((n
= prom_getproperty(node
, "translations",
522 (char *)&prom_trans
[0],
523 sizeof(prom_trans
))) == -1) {
524 prom_printf("prom_mappings: Couldn't get property.\n");
528 n
= n
/ sizeof(struct linux_prom_translation
);
532 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
535 /* Now kick out all the non-OBP entries. */
536 for (i
= 0; i
< ents
; i
++) {
537 if (in_obp_range(prom_trans
[i
].virt
))
541 for (; i
< ents
; i
++) {
542 if (!in_obp_range(prom_trans
[i
].virt
))
547 for (i
= 0; i
< (last
- first
); i
++) {
548 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
549 struct linux_prom_translation
*dest
= &prom_trans
[i
];
553 for (; i
< ents
; i
++) {
554 struct linux_prom_translation
*dest
= &prom_trans
[i
];
555 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
558 prom_trans_ents
= last
- first
;
560 if (tlb_type
== spitfire
) {
561 /* Clear diag TTE bits. */
562 for (i
= 0; i
< prom_trans_ents
; i
++)
563 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
566 /* Force execute bit on. */
567 for (i
= 0; i
< prom_trans_ents
; i
++)
568 prom_trans
[i
].data
|= (tlb_type
== hypervisor
?
569 _PAGE_EXEC_4V
: _PAGE_EXEC_4U
);
572 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
576 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
579 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
580 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
585 static unsigned long kern_large_tte(unsigned long paddr
);
587 static void __init
remap_kernel(void)
589 unsigned long phys_page
, tte_vaddr
, tte_data
;
590 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
592 tte_vaddr
= (unsigned long) KERNBASE
;
593 phys_page
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
594 tte_data
= kern_large_tte(phys_page
);
596 kern_locked_tte_data
= tte_data
;
598 /* Now lock us into the TLBs via Hypervisor or OBP. */
599 if (tlb_type
== hypervisor
) {
600 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
601 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
602 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
603 tte_vaddr
+= 0x400000;
604 tte_data
+= 0x400000;
607 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
608 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
609 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
610 tte_vaddr
+= 0x400000;
611 tte_data
+= 0x400000;
613 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
615 if (tlb_type
== cheetah_plus
) {
616 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
617 CTX_CHEETAH_PLUS_NUC
);
618 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
619 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
624 static void __init
inherit_prom_mappings(void)
626 /* Now fixup OBP's idea about where we really are mapped. */
627 printk("Remapping the kernel... ");
632 void prom_world(int enter
)
637 __asm__
__volatile__("flushw");
640 void __flush_dcache_range(unsigned long start
, unsigned long end
)
644 if (tlb_type
== spitfire
) {
647 for (va
= start
; va
< end
; va
+= 32) {
648 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
652 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
655 for (va
= start
; va
< end
; va
+= 32)
656 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
660 "i" (ASI_DCACHE_INVALIDATE
));
663 EXPORT_SYMBOL(__flush_dcache_range
);
665 /* get_new_mmu_context() uses "cache + 1". */
666 DEFINE_SPINLOCK(ctx_alloc_lock
);
667 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
668 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
669 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
670 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
672 /* Caller does TLB context flushing on local CPU if necessary.
673 * The caller also ensures that CTX_VALID(mm->context) is false.
675 * We must be careful about boundary cases so that we never
676 * let the user have CTX 0 (nucleus) or we ever use a CTX
677 * version of zero (and thus NO_CONTEXT would not be caught
678 * by version mis-match tests in mmu_context.h).
680 * Always invoked with interrupts disabled.
682 void get_new_mmu_context(struct mm_struct
*mm
)
684 unsigned long ctx
, new_ctx
;
685 unsigned long orig_pgsz_bits
;
688 spin_lock(&ctx_alloc_lock
);
689 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
690 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
691 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
693 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
694 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
695 if (new_ctx
>= ctx
) {
697 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
700 new_ctx
= CTX_FIRST_VERSION
;
702 /* Don't call memset, for 16 entries that's just
705 mmu_context_bmap
[0] = 3;
706 mmu_context_bmap
[1] = 0;
707 mmu_context_bmap
[2] = 0;
708 mmu_context_bmap
[3] = 0;
709 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
710 mmu_context_bmap
[i
+ 0] = 0;
711 mmu_context_bmap
[i
+ 1] = 0;
712 mmu_context_bmap
[i
+ 2] = 0;
713 mmu_context_bmap
[i
+ 3] = 0;
719 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
720 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
722 tlb_context_cache
= new_ctx
;
723 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
724 spin_unlock(&ctx_alloc_lock
);
726 if (unlikely(new_version
))
727 smp_new_mmu_context_version();
730 static int numa_enabled
= 1;
731 static int numa_debug
;
733 static int __init
early_numa(char *p
)
738 if (strstr(p
, "off"))
741 if (strstr(p
, "debug"))
746 early_param("numa", early_numa
);
748 #define numadbg(f, a...) \
749 do { if (numa_debug) \
750 printk(KERN_INFO f, ## a); \
753 static void __init
find_ramdisk(unsigned long phys_base
)
755 #ifdef CONFIG_BLK_DEV_INITRD
756 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
757 unsigned long ramdisk_image
;
759 /* Older versions of the bootloader only supported a
760 * 32-bit physical address for the ramdisk image
761 * location, stored at sparc_ramdisk_image. Newer
762 * SILO versions set sparc_ramdisk_image to zero and
763 * provide a full 64-bit physical address at
764 * sparc_ramdisk_image64.
766 ramdisk_image
= sparc_ramdisk_image
;
768 ramdisk_image
= sparc_ramdisk_image64
;
770 /* Another bootloader quirk. The bootloader normalizes
771 * the physical address to KERNBASE, so we have to
772 * factor that back out and add in the lowest valid
773 * physical page address to get the true physical address.
775 ramdisk_image
-= KERNBASE
;
776 ramdisk_image
+= phys_base
;
778 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
779 ramdisk_image
, sparc_ramdisk_size
);
781 initrd_start
= ramdisk_image
;
782 initrd_end
= ramdisk_image
+ sparc_ramdisk_size
;
784 memblock_reserve(initrd_start
, sparc_ramdisk_size
);
786 initrd_start
+= PAGE_OFFSET
;
787 initrd_end
+= PAGE_OFFSET
;
792 struct node_mem_mask
{
796 static struct node_mem_mask node_masks
[MAX_NUMNODES
];
797 static int num_node_masks
;
799 #ifdef CONFIG_NEED_MULTIPLE_NODES
801 int numa_cpu_lookup_table
[NR_CPUS
];
802 cpumask_t numa_cpumask_lookup_table
[MAX_NUMNODES
];
804 struct mdesc_mblock
{
807 u64 offset
; /* RA-to-PA */
809 static struct mdesc_mblock
*mblocks
;
810 static int num_mblocks
;
812 static unsigned long ra_to_pa(unsigned long addr
)
816 for (i
= 0; i
< num_mblocks
; i
++) {
817 struct mdesc_mblock
*m
= &mblocks
[i
];
819 if (addr
>= m
->base
&&
820 addr
< (m
->base
+ m
->size
)) {
828 static int find_node(unsigned long addr
)
832 addr
= ra_to_pa(addr
);
833 for (i
= 0; i
< num_node_masks
; i
++) {
834 struct node_mem_mask
*p
= &node_masks
[i
];
836 if ((addr
& p
->mask
) == p
->val
)
839 /* The following condition has been observed on LDOM guests.*/
840 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
841 " rule. Some physical memory will be owned by node 0.");
845 static u64
memblock_nid_range(u64 start
, u64 end
, int *nid
)
847 *nid
= find_node(start
);
849 while (start
< end
) {
850 int n
= find_node(start
);
864 /* This must be invoked after performing all of the necessary
865 * memblock_set_node() calls for 'nid'. We need to be able to get
866 * correct data from get_pfn_range_for_nid().
868 static void __init
allocate_node_data(int nid
)
870 struct pglist_data
*p
;
871 unsigned long start_pfn
, end_pfn
;
872 #ifdef CONFIG_NEED_MULTIPLE_NODES
875 paddr
= memblock_alloc_try_nid(sizeof(struct pglist_data
), SMP_CACHE_BYTES
, nid
);
877 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid
);
880 NODE_DATA(nid
) = __va(paddr
);
881 memset(NODE_DATA(nid
), 0, sizeof(struct pglist_data
));
883 NODE_DATA(nid
)->node_id
= nid
;
888 get_pfn_range_for_nid(nid
, &start_pfn
, &end_pfn
);
889 p
->node_start_pfn
= start_pfn
;
890 p
->node_spanned_pages
= end_pfn
- start_pfn
;
893 static void init_node_masks_nonnuma(void)
895 #ifdef CONFIG_NEED_MULTIPLE_NODES
899 numadbg("Initializing tables for non-numa.\n");
901 node_masks
[0].mask
= node_masks
[0].val
= 0;
904 #ifdef CONFIG_NEED_MULTIPLE_NODES
905 for (i
= 0; i
< NR_CPUS
; i
++)
906 numa_cpu_lookup_table
[i
] = 0;
908 cpumask_setall(&numa_cpumask_lookup_table
[0]);
912 #ifdef CONFIG_NEED_MULTIPLE_NODES
913 struct pglist_data
*node_data
[MAX_NUMNODES
];
915 EXPORT_SYMBOL(numa_cpu_lookup_table
);
916 EXPORT_SYMBOL(numa_cpumask_lookup_table
);
917 EXPORT_SYMBOL(node_data
);
919 struct mdesc_mlgroup
{
925 static struct mdesc_mlgroup
*mlgroups
;
926 static int num_mlgroups
;
928 static int scan_pio_for_cfg_handle(struct mdesc_handle
*md
, u64 pio
,
933 mdesc_for_each_arc(arc
, md
, pio
, MDESC_ARC_TYPE_FWD
) {
934 u64 target
= mdesc_arc_target(md
, arc
);
937 val
= mdesc_get_property(md
, target
,
939 if (val
&& *val
== cfg_handle
)
945 static int scan_arcs_for_cfg_handle(struct mdesc_handle
*md
, u64 grp
,
948 u64 arc
, candidate
, best_latency
= ~(u64
)0;
950 candidate
= MDESC_NODE_NULL
;
951 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
952 u64 target
= mdesc_arc_target(md
, arc
);
953 const char *name
= mdesc_node_name(md
, target
);
956 if (strcmp(name
, "pio-latency-group"))
959 val
= mdesc_get_property(md
, target
, "latency", NULL
);
963 if (*val
< best_latency
) {
969 if (candidate
== MDESC_NODE_NULL
)
972 return scan_pio_for_cfg_handle(md
, candidate
, cfg_handle
);
975 int of_node_to_nid(struct device_node
*dp
)
977 const struct linux_prom64_registers
*regs
;
978 struct mdesc_handle
*md
;
983 /* This is the right thing to do on currently supported
984 * SUN4U NUMA platforms as well, as the PCI controller does
985 * not sit behind any particular memory controller.
990 regs
= of_get_property(dp
, "reg", NULL
);
994 cfg_handle
= (regs
->phys_addr
>> 32UL) & 0x0fffffff;
1000 mdesc_for_each_node_by_name(md
, grp
, "group") {
1001 if (!scan_arcs_for_cfg_handle(md
, grp
, cfg_handle
)) {
1013 static void __init
add_node_ranges(void)
1015 struct memblock_region
*reg
;
1017 for_each_memblock(memory
, reg
) {
1018 unsigned long size
= reg
->size
;
1019 unsigned long start
, end
;
1023 while (start
< end
) {
1024 unsigned long this_end
;
1027 this_end
= memblock_nid_range(start
, end
, &nid
);
1029 numadbg("Setting memblock NUMA node nid[%d] "
1030 "start[%lx] end[%lx]\n",
1031 nid
, start
, this_end
);
1033 memblock_set_node(start
, this_end
- start
,
1034 &memblock
.memory
, nid
);
1040 static int __init
grab_mlgroups(struct mdesc_handle
*md
)
1042 unsigned long paddr
;
1046 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group")
1051 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mlgroup
),
1056 mlgroups
= __va(paddr
);
1057 num_mlgroups
= count
;
1060 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group") {
1061 struct mdesc_mlgroup
*m
= &mlgroups
[count
++];
1066 val
= mdesc_get_property(md
, node
, "latency", NULL
);
1068 val
= mdesc_get_property(md
, node
, "address-match", NULL
);
1070 val
= mdesc_get_property(md
, node
, "address-mask", NULL
);
1073 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1074 "match[%llx] mask[%llx]\n",
1075 count
- 1, m
->node
, m
->latency
, m
->match
, m
->mask
);
1081 static int __init
grab_mblocks(struct mdesc_handle
*md
)
1083 unsigned long paddr
;
1087 mdesc_for_each_node_by_name(md
, node
, "mblock")
1092 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mblock
),
1097 mblocks
= __va(paddr
);
1098 num_mblocks
= count
;
1101 mdesc_for_each_node_by_name(md
, node
, "mblock") {
1102 struct mdesc_mblock
*m
= &mblocks
[count
++];
1105 val
= mdesc_get_property(md
, node
, "base", NULL
);
1107 val
= mdesc_get_property(md
, node
, "size", NULL
);
1109 val
= mdesc_get_property(md
, node
,
1110 "address-congruence-offset", NULL
);
1112 /* The address-congruence-offset property is optional.
1113 * Explicity zero it be identifty this.
1120 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1121 count
- 1, m
->base
, m
->size
, m
->offset
);
1127 static void __init
numa_parse_mdesc_group_cpus(struct mdesc_handle
*md
,
1128 u64 grp
, cpumask_t
*mask
)
1132 cpumask_clear(mask
);
1134 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_BACK
) {
1135 u64 target
= mdesc_arc_target(md
, arc
);
1136 const char *name
= mdesc_node_name(md
, target
);
1139 if (strcmp(name
, "cpu"))
1141 id
= mdesc_get_property(md
, target
, "id", NULL
);
1142 if (*id
< nr_cpu_ids
)
1143 cpumask_set_cpu(*id
, mask
);
1147 static struct mdesc_mlgroup
* __init
find_mlgroup(u64 node
)
1151 for (i
= 0; i
< num_mlgroups
; i
++) {
1152 struct mdesc_mlgroup
*m
= &mlgroups
[i
];
1153 if (m
->node
== node
)
1159 static int __init
numa_attach_mlgroup(struct mdesc_handle
*md
, u64 grp
,
1162 struct mdesc_mlgroup
*candidate
= NULL
;
1163 u64 arc
, best_latency
= ~(u64
)0;
1164 struct node_mem_mask
*n
;
1166 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1167 u64 target
= mdesc_arc_target(md
, arc
);
1168 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1171 if (m
->latency
< best_latency
) {
1173 best_latency
= m
->latency
;
1179 if (num_node_masks
!= index
) {
1180 printk(KERN_ERR
"Inconsistent NUMA state, "
1181 "index[%d] != num_node_masks[%d]\n",
1182 index
, num_node_masks
);
1186 n
= &node_masks
[num_node_masks
++];
1188 n
->mask
= candidate
->mask
;
1189 n
->val
= candidate
->match
;
1191 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1192 index
, n
->mask
, n
->val
, candidate
->latency
);
1197 static int __init
numa_parse_mdesc_group(struct mdesc_handle
*md
, u64 grp
,
1203 numa_parse_mdesc_group_cpus(md
, grp
, &mask
);
1205 for_each_cpu(cpu
, &mask
)
1206 numa_cpu_lookup_table
[cpu
] = index
;
1207 cpumask_copy(&numa_cpumask_lookup_table
[index
], &mask
);
1210 printk(KERN_INFO
"NUMA GROUP[%d]: cpus [ ", index
);
1211 for_each_cpu(cpu
, &mask
)
1216 return numa_attach_mlgroup(md
, grp
, index
);
1219 static int __init
numa_parse_mdesc(void)
1221 struct mdesc_handle
*md
= mdesc_grab();
1225 node
= mdesc_node_by_name(md
, MDESC_NODE_NULL
, "latency-groups");
1226 if (node
== MDESC_NODE_NULL
) {
1231 err
= grab_mblocks(md
);
1235 err
= grab_mlgroups(md
);
1240 mdesc_for_each_node_by_name(md
, node
, "group") {
1241 err
= numa_parse_mdesc_group(md
, node
, count
);
1249 for (i
= 0; i
< num_node_masks
; i
++) {
1250 allocate_node_data(i
);
1260 static int __init
numa_parse_jbus(void)
1262 unsigned long cpu
, index
;
1264 /* NUMA node id is encoded in bits 36 and higher, and there is
1265 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1268 for_each_present_cpu(cpu
) {
1269 numa_cpu_lookup_table
[cpu
] = index
;
1270 cpumask_copy(&numa_cpumask_lookup_table
[index
], cpumask_of(cpu
));
1271 node_masks
[index
].mask
= ~((1UL << 36UL) - 1UL);
1272 node_masks
[index
].val
= cpu
<< 36UL;
1276 num_node_masks
= index
;
1280 for (index
= 0; index
< num_node_masks
; index
++) {
1281 allocate_node_data(index
);
1282 node_set_online(index
);
1288 static int __init
numa_parse_sun4u(void)
1290 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1293 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
1294 if ((ver
>> 32UL) == __JALAPENO_ID
||
1295 (ver
>> 32UL) == __SERRANO_ID
)
1296 return numa_parse_jbus();
1301 static int __init
bootmem_init_numa(void)
1305 numadbg("bootmem_init_numa()\n");
1308 if (tlb_type
== hypervisor
)
1309 err
= numa_parse_mdesc();
1311 err
= numa_parse_sun4u();
1318 static int bootmem_init_numa(void)
1325 static void __init
bootmem_init_nonnuma(void)
1327 unsigned long top_of_ram
= memblock_end_of_DRAM();
1328 unsigned long total_ram
= memblock_phys_mem_size();
1330 numadbg("bootmem_init_nonnuma()\n");
1332 printk(KERN_INFO
"Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1333 top_of_ram
, total_ram
);
1334 printk(KERN_INFO
"Memory hole size: %ldMB\n",
1335 (top_of_ram
- total_ram
) >> 20);
1337 init_node_masks_nonnuma();
1338 memblock_set_node(0, (phys_addr_t
)ULLONG_MAX
, &memblock
.memory
, 0);
1339 allocate_node_data(0);
1343 static unsigned long __init
bootmem_init(unsigned long phys_base
)
1345 unsigned long end_pfn
;
1347 end_pfn
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
1348 max_pfn
= max_low_pfn
= end_pfn
;
1349 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
1351 if (bootmem_init_numa() < 0)
1352 bootmem_init_nonnuma();
1354 /* Dump memblock with node info. */
1355 memblock_dump_all();
1357 /* XXX cpu notifier XXX */
1359 sparse_memory_present_with_active_regions(MAX_NUMNODES
);
1365 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
1366 static int pall_ents __initdata
;
1368 static unsigned long max_phys_bits
= 40;
1370 bool kern_addr_valid(unsigned long addr
)
1377 if ((long)addr
< 0L) {
1378 unsigned long pa
= __pa(addr
);
1380 if ((addr
>> max_phys_bits
) != 0UL)
1383 return pfn_valid(pa
>> PAGE_SHIFT
);
1386 if (addr
>= (unsigned long) KERNBASE
&&
1387 addr
< (unsigned long)&_end
)
1390 pgd
= pgd_offset_k(addr
);
1394 pud
= pud_offset(pgd
, addr
);
1398 if (pud_large(*pud
))
1399 return pfn_valid(pud_pfn(*pud
));
1401 pmd
= pmd_offset(pud
, addr
);
1405 if (pmd_large(*pmd
))
1406 return pfn_valid(pmd_pfn(*pmd
));
1408 pte
= pte_offset_kernel(pmd
, addr
);
1412 return pfn_valid(pte_pfn(*pte
));
1414 EXPORT_SYMBOL(kern_addr_valid
);
1416 static unsigned long __ref
kernel_map_hugepud(unsigned long vstart
,
1420 const unsigned long mask16gb
= (1UL << 34) - 1UL;
1421 u64 pte_val
= vstart
;
1423 /* Each PUD is 8GB */
1424 if ((vstart
& mask16gb
) ||
1425 (vend
- vstart
<= mask16gb
)) {
1426 pte_val
^= kern_linear_pte_xor
[2];
1427 pud_val(*pud
) = pte_val
| _PAGE_PUD_HUGE
;
1429 return vstart
+ PUD_SIZE
;
1432 pte_val
^= kern_linear_pte_xor
[3];
1433 pte_val
|= _PAGE_PUD_HUGE
;
1435 vend
= vstart
+ mask16gb
+ 1UL;
1436 while (vstart
< vend
) {
1437 pud_val(*pud
) = pte_val
;
1439 pte_val
+= PUD_SIZE
;
1446 static bool kernel_can_map_hugepud(unsigned long vstart
, unsigned long vend
,
1449 if (guard
&& !(vstart
& ~PUD_MASK
) && (vend
- vstart
) >= PUD_SIZE
)
1455 static unsigned long __ref
kernel_map_hugepmd(unsigned long vstart
,
1459 const unsigned long mask256mb
= (1UL << 28) - 1UL;
1460 const unsigned long mask2gb
= (1UL << 31) - 1UL;
1461 u64 pte_val
= vstart
;
1463 /* Each PMD is 8MB */
1464 if ((vstart
& mask256mb
) ||
1465 (vend
- vstart
<= mask256mb
)) {
1466 pte_val
^= kern_linear_pte_xor
[0];
1467 pmd_val(*pmd
) = pte_val
| _PAGE_PMD_HUGE
;
1469 return vstart
+ PMD_SIZE
;
1472 if ((vstart
& mask2gb
) ||
1473 (vend
- vstart
<= mask2gb
)) {
1474 pte_val
^= kern_linear_pte_xor
[1];
1475 pte_val
|= _PAGE_PMD_HUGE
;
1476 vend
= vstart
+ mask256mb
+ 1UL;
1478 pte_val
^= kern_linear_pte_xor
[2];
1479 pte_val
|= _PAGE_PMD_HUGE
;
1480 vend
= vstart
+ mask2gb
+ 1UL;
1483 while (vstart
< vend
) {
1484 pmd_val(*pmd
) = pte_val
;
1486 pte_val
+= PMD_SIZE
;
1494 static bool kernel_can_map_hugepmd(unsigned long vstart
, unsigned long vend
,
1497 if (guard
&& !(vstart
& ~PMD_MASK
) && (vend
- vstart
) >= PMD_SIZE
)
1503 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
1504 unsigned long pend
, pgprot_t prot
,
1507 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
1508 unsigned long vend
= PAGE_OFFSET
+ pend
;
1509 unsigned long alloc_bytes
= 0UL;
1511 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
1512 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1517 while (vstart
< vend
) {
1518 unsigned long this_end
, paddr
= __pa(vstart
);
1519 pgd_t
*pgd
= pgd_offset_k(vstart
);
1524 if (pgd_none(*pgd
)) {
1527 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1528 alloc_bytes
+= PAGE_SIZE
;
1529 pgd_populate(&init_mm
, pgd
, new);
1531 pud
= pud_offset(pgd
, vstart
);
1532 if (pud_none(*pud
)) {
1535 if (kernel_can_map_hugepud(vstart
, vend
, use_huge
)) {
1536 vstart
= kernel_map_hugepud(vstart
, vend
, pud
);
1539 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1540 alloc_bytes
+= PAGE_SIZE
;
1541 pud_populate(&init_mm
, pud
, new);
1544 pmd
= pmd_offset(pud
, vstart
);
1545 if (pmd_none(*pmd
)) {
1548 if (kernel_can_map_hugepmd(vstart
, vend
, use_huge
)) {
1549 vstart
= kernel_map_hugepmd(vstart
, vend
, pmd
);
1552 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1553 alloc_bytes
+= PAGE_SIZE
;
1554 pmd_populate_kernel(&init_mm
, pmd
, new);
1557 pte
= pte_offset_kernel(pmd
, vstart
);
1558 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1559 if (this_end
> vend
)
1562 while (vstart
< this_end
) {
1563 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1565 vstart
+= PAGE_SIZE
;
1574 static void __init
flush_all_kernel_tsbs(void)
1578 for (i
= 0; i
< KERNEL_TSB_NENTRIES
; i
++) {
1579 struct tsb
*ent
= &swapper_tsb
[i
];
1581 ent
->tag
= (1UL << TSB_TAG_INVALID_BIT
);
1583 #ifndef CONFIG_DEBUG_PAGEALLOC
1584 for (i
= 0; i
< KERNEL_TSB4M_NENTRIES
; i
++) {
1585 struct tsb
*ent
= &swapper_4m_tsb
[i
];
1587 ent
->tag
= (1UL << TSB_TAG_INVALID_BIT
);
1592 extern unsigned int kvmap_linear_patch
[1];
1594 static void __init
kernel_physical_mapping_init(void)
1596 unsigned long i
, mem_alloced
= 0UL;
1597 bool use_huge
= true;
1599 #ifdef CONFIG_DEBUG_PAGEALLOC
1602 for (i
= 0; i
< pall_ents
; i
++) {
1603 unsigned long phys_start
, phys_end
;
1605 phys_start
= pall
[i
].phys_addr
;
1606 phys_end
= phys_start
+ pall
[i
].reg_size
;
1608 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1609 PAGE_KERNEL
, use_huge
);
1612 printk("Allocated %ld bytes for kernel page tables.\n",
1615 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1616 flushi(&kvmap_linear_patch
[0]);
1618 flush_all_kernel_tsbs();
1623 #ifdef CONFIG_DEBUG_PAGEALLOC
1624 void __kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1626 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1627 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1629 kernel_map_range(phys_start
, phys_end
,
1630 (enable
? PAGE_KERNEL
: __pgprot(0)), false);
1632 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1633 PAGE_OFFSET
+ phys_end
);
1635 /* we should perform an IPI and flush all tlbs,
1636 * but that can deadlock->flush only current cpu.
1638 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1639 PAGE_OFFSET
+ phys_end
);
1643 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1647 for (i
= 0; i
< pavail_ents
; i
++) {
1648 if (pavail
[i
].reg_size
>= size
)
1649 return pavail
[i
].phys_addr
;
1655 unsigned long PAGE_OFFSET
;
1656 EXPORT_SYMBOL(PAGE_OFFSET
);
1658 unsigned long VMALLOC_END
= 0x0000010000000000UL
;
1659 EXPORT_SYMBOL(VMALLOC_END
);
1661 unsigned long sparc64_va_hole_top
= 0xfffff80000000000UL
;
1662 unsigned long sparc64_va_hole_bottom
= 0x0000080000000000UL
;
1664 static void __init
setup_page_offset(void)
1666 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1667 /* Cheetah/Panther support a full 64-bit virtual
1668 * address, so we can use all that our page tables
1671 sparc64_va_hole_top
= 0xfff0000000000000UL
;
1672 sparc64_va_hole_bottom
= 0x0010000000000000UL
;
1675 } else if (tlb_type
== hypervisor
) {
1676 switch (sun4v_chip_type
) {
1677 case SUN4V_CHIP_NIAGARA1
:
1678 case SUN4V_CHIP_NIAGARA2
:
1679 /* T1 and T2 support 48-bit virtual addresses. */
1680 sparc64_va_hole_top
= 0xffff800000000000UL
;
1681 sparc64_va_hole_bottom
= 0x0000800000000000UL
;
1685 case SUN4V_CHIP_NIAGARA3
:
1686 /* T3 supports 48-bit virtual addresses. */
1687 sparc64_va_hole_top
= 0xffff800000000000UL
;
1688 sparc64_va_hole_bottom
= 0x0000800000000000UL
;
1692 case SUN4V_CHIP_NIAGARA4
:
1693 case SUN4V_CHIP_NIAGARA5
:
1694 case SUN4V_CHIP_SPARC64X
:
1695 case SUN4V_CHIP_SPARC_M6
:
1696 /* T4 and later support 52-bit virtual addresses. */
1697 sparc64_va_hole_top
= 0xfff8000000000000UL
;
1698 sparc64_va_hole_bottom
= 0x0008000000000000UL
;
1701 case SUN4V_CHIP_SPARC_M7
:
1703 /* M7 and later support 52-bit virtual addresses. */
1704 sparc64_va_hole_top
= 0xfff8000000000000UL
;
1705 sparc64_va_hole_bottom
= 0x0008000000000000UL
;
1711 if (max_phys_bits
> MAX_PHYS_ADDRESS_BITS
) {
1712 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1717 PAGE_OFFSET
= sparc64_va_hole_top
;
1718 VMALLOC_END
= ((sparc64_va_hole_bottom
>> 1) +
1719 (sparc64_va_hole_bottom
>> 2));
1721 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1722 PAGE_OFFSET
, max_phys_bits
);
1723 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1724 VMALLOC_START
, VMALLOC_END
);
1725 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1726 VMEMMAP_BASE
, VMEMMAP_BASE
<< 1);
1729 static void __init
tsb_phys_patch(void)
1731 struct tsb_ldquad_phys_patch_entry
*pquad
;
1732 struct tsb_phys_patch_entry
*p
;
1734 pquad
= &__tsb_ldquad_phys_patch
;
1735 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1736 unsigned long addr
= pquad
->addr
;
1738 if (tlb_type
== hypervisor
)
1739 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1741 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1743 __asm__
__volatile__("flush %0"
1750 p
= &__tsb_phys_patch
;
1751 while (p
< &__tsb_phys_patch_end
) {
1752 unsigned long addr
= p
->addr
;
1754 *(unsigned int *) addr
= p
->insn
;
1756 __asm__
__volatile__("flush %0"
1764 /* Don't mark as init, we give this to the Hypervisor. */
1765 #ifndef CONFIG_DEBUG_PAGEALLOC
1766 #define NUM_KTSB_DESCR 2
1768 #define NUM_KTSB_DESCR 1
1770 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1772 /* The swapper TSBs are loaded with a base sequence of:
1774 * sethi %uhi(SYMBOL), REG1
1775 * sethi %hi(SYMBOL), REG2
1776 * or REG1, %ulo(SYMBOL), REG1
1777 * or REG2, %lo(SYMBOL), REG2
1778 * sllx REG1, 32, REG1
1779 * or REG1, REG2, REG1
1781 * When we use physical addressing for the TSB accesses, we patch the
1782 * first four instructions in the above sequence.
1785 static void patch_one_ktsb_phys(unsigned int *start
, unsigned int *end
, unsigned long pa
)
1787 unsigned long high_bits
, low_bits
;
1789 high_bits
= (pa
>> 32) & 0xffffffff;
1790 low_bits
= (pa
>> 0) & 0xffffffff;
1792 while (start
< end
) {
1793 unsigned int *ia
= (unsigned int *)(unsigned long)*start
;
1795 ia
[0] = (ia
[0] & ~0x3fffff) | (high_bits
>> 10);
1796 __asm__
__volatile__("flush %0" : : "r" (ia
));
1798 ia
[1] = (ia
[1] & ~0x3fffff) | (low_bits
>> 10);
1799 __asm__
__volatile__("flush %0" : : "r" (ia
+ 1));
1801 ia
[2] = (ia
[2] & ~0x1fff) | (high_bits
& 0x3ff);
1802 __asm__
__volatile__("flush %0" : : "r" (ia
+ 2));
1804 ia
[3] = (ia
[3] & ~0x1fff) | (low_bits
& 0x3ff);
1805 __asm__
__volatile__("flush %0" : : "r" (ia
+ 3));
1811 static void ktsb_phys_patch(void)
1813 extern unsigned int __swapper_tsb_phys_patch
;
1814 extern unsigned int __swapper_tsb_phys_patch_end
;
1815 unsigned long ktsb_pa
;
1817 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1818 patch_one_ktsb_phys(&__swapper_tsb_phys_patch
,
1819 &__swapper_tsb_phys_patch_end
, ktsb_pa
);
1820 #ifndef CONFIG_DEBUG_PAGEALLOC
1822 extern unsigned int __swapper_4m_tsb_phys_patch
;
1823 extern unsigned int __swapper_4m_tsb_phys_patch_end
;
1824 ktsb_pa
= (kern_base
+
1825 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1826 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch
,
1827 &__swapper_4m_tsb_phys_patch_end
, ktsb_pa
);
1832 static void __init
sun4v_ktsb_init(void)
1834 unsigned long ktsb_pa
;
1836 /* First KTSB for PAGE_SIZE mappings. */
1837 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1839 switch (PAGE_SIZE
) {
1842 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1843 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1847 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1848 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1852 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1853 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1856 case 4 * 1024 * 1024:
1857 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1858 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1862 ktsb_descr
[0].assoc
= 1;
1863 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1864 ktsb_descr
[0].ctx_idx
= 0;
1865 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1866 ktsb_descr
[0].resv
= 0;
1868 #ifndef CONFIG_DEBUG_PAGEALLOC
1869 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1870 ktsb_pa
= (kern_base
+
1871 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1873 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1874 ktsb_descr
[1].pgsz_mask
= ((HV_PGSZ_MASK_4MB
|
1875 HV_PGSZ_MASK_256MB
|
1877 HV_PGSZ_MASK_16GB
) &
1879 ktsb_descr
[1].assoc
= 1;
1880 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1881 ktsb_descr
[1].ctx_idx
= 0;
1882 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1883 ktsb_descr
[1].resv
= 0;
1887 void sun4v_ktsb_register(void)
1889 unsigned long pa
, ret
;
1891 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1893 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
1895 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1896 "errors with %lx\n", pa
, ret
);
1901 static void __init
sun4u_linear_pte_xor_finalize(void)
1903 #ifndef CONFIG_DEBUG_PAGEALLOC
1904 /* This is where we would add Panther support for
1905 * 32MB and 256MB pages.
1910 static void __init
sun4v_linear_pte_xor_finalize(void)
1912 #ifndef CONFIG_DEBUG_PAGEALLOC
1913 if (cpu_pgsz_mask
& HV_PGSZ_MASK_256MB
) {
1914 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
1916 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1917 _PAGE_P_4V
| _PAGE_W_4V
);
1919 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
1922 if (cpu_pgsz_mask
& HV_PGSZ_MASK_2GB
) {
1923 kern_linear_pte_xor
[2] = (_PAGE_VALID
| _PAGE_SZ2GB_4V
) ^
1925 kern_linear_pte_xor
[2] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1926 _PAGE_P_4V
| _PAGE_W_4V
);
1928 kern_linear_pte_xor
[2] = kern_linear_pte_xor
[1];
1931 if (cpu_pgsz_mask
& HV_PGSZ_MASK_16GB
) {
1932 kern_linear_pte_xor
[3] = (_PAGE_VALID
| _PAGE_SZ16GB_4V
) ^
1934 kern_linear_pte_xor
[3] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1935 _PAGE_P_4V
| _PAGE_W_4V
);
1937 kern_linear_pte_xor
[3] = kern_linear_pte_xor
[2];
1942 /* paging_init() sets up the page tables */
1944 static unsigned long last_valid_pfn
;
1946 static void sun4u_pgprot_init(void);
1947 static void sun4v_pgprot_init(void);
1949 static phys_addr_t __init
available_memory(void)
1951 phys_addr_t available
= 0ULL;
1952 phys_addr_t pa_start
, pa_end
;
1955 for_each_free_mem_range(i
, NUMA_NO_NODE
, &pa_start
, &pa_end
, NULL
)
1956 available
= available
+ (pa_end
- pa_start
);
1961 /* We need to exclude reserved regions. This exclusion will include
1962 * vmlinux and initrd. To be more precise the initrd size could be used to
1963 * compute a new lower limit because it is freed later during initialization.
1965 static void __init
reduce_memory(phys_addr_t limit_ram
)
1967 phys_addr_t avail_ram
= available_memory();
1968 phys_addr_t pa_start
, pa_end
;
1971 if (limit_ram
>= avail_ram
)
1974 for_each_free_mem_range(i
, NUMA_NO_NODE
, &pa_start
, &pa_end
, NULL
) {
1975 phys_addr_t region_size
= pa_end
- pa_start
;
1976 phys_addr_t clip_start
= pa_start
;
1978 avail_ram
= avail_ram
- region_size
;
1979 /* Are we consuming too much? */
1980 if (avail_ram
< limit_ram
) {
1981 phys_addr_t give_back
= limit_ram
- avail_ram
;
1983 region_size
= region_size
- give_back
;
1984 clip_start
= clip_start
+ give_back
;
1987 memblock_remove(clip_start
, region_size
);
1989 if (avail_ram
<= limit_ram
)
1995 void __init
paging_init(void)
1997 unsigned long end_pfn
, shift
, phys_base
;
1998 unsigned long real_end
, i
;
2001 setup_page_offset();
2003 /* These build time checkes make sure that the dcache_dirty_cpu()
2004 * page->flags usage will work.
2006 * When a page gets marked as dcache-dirty, we store the
2007 * cpu number starting at bit 32 in the page->flags. Also,
2008 * functions like clear_dcache_dirty_cpu use the cpu mask
2009 * in 13-bit signed-immediate instruction fields.
2013 * Page flags must not reach into upper 32 bits that are used
2014 * for the cpu number
2016 BUILD_BUG_ON(NR_PAGEFLAGS
> 32);
2019 * The bit fields placed in the high range must not reach below
2020 * the 32 bit boundary. Otherwise we cannot place the cpu field
2021 * at the 32 bit boundary.
2023 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
2024 ilog2(roundup_pow_of_two(NR_CPUS
)) > 32);
2026 BUILD_BUG_ON(NR_CPUS
> 4096);
2028 kern_base
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
2029 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
2031 /* Invalidate both kernel TSBs. */
2032 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
2033 #ifndef CONFIG_DEBUG_PAGEALLOC
2034 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
2037 if (tlb_type
== hypervisor
)
2038 sun4v_pgprot_init();
2040 sun4u_pgprot_init();
2042 if (tlb_type
== cheetah_plus
||
2043 tlb_type
== hypervisor
) {
2048 if (tlb_type
== hypervisor
)
2049 sun4v_patch_tlb_handlers();
2051 /* Find available physical memory...
2053 * Read it twice in order to work around a bug in openfirmware.
2054 * The call to grab this table itself can cause openfirmware to
2055 * allocate memory, which in turn can take away some space from
2056 * the list of available memory. Reading it twice makes sure
2057 * we really do get the final value.
2059 read_obp_translations();
2060 read_obp_memory("reg", &pall
[0], &pall_ents
);
2061 read_obp_memory("available", &pavail
[0], &pavail_ents
);
2062 read_obp_memory("available", &pavail
[0], &pavail_ents
);
2064 phys_base
= 0xffffffffffffffffUL
;
2065 for (i
= 0; i
< pavail_ents
; i
++) {
2066 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
2067 memblock_add(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
2070 memblock_reserve(kern_base
, kern_size
);
2072 find_ramdisk(phys_base
);
2074 if (cmdline_memory_size
)
2075 reduce_memory(cmdline_memory_size
);
2077 memblock_allow_resize();
2078 memblock_dump_all();
2080 set_bit(0, mmu_context_bmap
);
2082 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
2084 real_end
= (unsigned long)_end
;
2085 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << ILOG2_4MB
);
2086 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2087 num_kernel_image_mappings
);
2089 /* Set kernel pgd to upper alias so physical page computations
2092 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
2094 memset(swapper_pg_dir
, 0, sizeof(swapper_pg_dir
));
2096 inherit_prom_mappings();
2098 /* Ok, we can use our TLB miss and window trap handlers safely. */
2103 prom_build_devicetree();
2104 of_populate_present_mask();
2106 of_fill_in_cpu_data();
2109 if (tlb_type
== hypervisor
) {
2111 mdesc_populate_present_mask(cpu_all_mask
);
2113 mdesc_fill_in_cpu_data(cpu_all_mask
);
2115 mdesc_get_page_sizes(cpu_all_mask
, &cpu_pgsz_mask
);
2117 sun4v_linear_pte_xor_finalize();
2120 sun4v_ktsb_register();
2122 unsigned long impl
, ver
;
2124 cpu_pgsz_mask
= (HV_PGSZ_MASK_8K
| HV_PGSZ_MASK_64K
|
2125 HV_PGSZ_MASK_512K
| HV_PGSZ_MASK_4MB
);
2127 __asm__
__volatile__("rdpr %%ver, %0" : "=r" (ver
));
2128 impl
= ((ver
>> 32) & 0xffff);
2129 if (impl
== PANTHER_IMPL
)
2130 cpu_pgsz_mask
|= (HV_PGSZ_MASK_32MB
|
2131 HV_PGSZ_MASK_256MB
);
2133 sun4u_linear_pte_xor_finalize();
2136 /* Flush the TLBs and the 4M TSB so that the updated linear
2137 * pte XOR settings are realized for all mappings.
2140 #ifndef CONFIG_DEBUG_PAGEALLOC
2141 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
2145 /* Setup bootmem... */
2146 last_valid_pfn
= end_pfn
= bootmem_init(phys_base
);
2148 /* Once the OF device tree and MDESC have been setup, we know
2149 * the list of possible cpus. Therefore we can allocate the
2152 for_each_possible_cpu(i
) {
2153 node
= cpu_to_node(i
);
2155 softirq_stack
[i
] = __alloc_bootmem_node(NODE_DATA(node
),
2158 hardirq_stack
[i
] = __alloc_bootmem_node(NODE_DATA(node
),
2163 kernel_physical_mapping_init();
2166 unsigned long max_zone_pfns
[MAX_NR_ZONES
];
2168 memset(max_zone_pfns
, 0, sizeof(max_zone_pfns
));
2170 max_zone_pfns
[ZONE_NORMAL
] = end_pfn
;
2172 free_area_init_nodes(max_zone_pfns
);
2175 printk("Booting Linux...\n");
2178 int page_in_phys_avail(unsigned long paddr
)
2184 for (i
= 0; i
< pavail_ents
; i
++) {
2185 unsigned long start
, end
;
2187 start
= pavail
[i
].phys_addr
;
2188 end
= start
+ pavail
[i
].reg_size
;
2190 if (paddr
>= start
&& paddr
< end
)
2193 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
2195 #ifdef CONFIG_BLK_DEV_INITRD
2196 if (paddr
>= __pa(initrd_start
) &&
2197 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
2204 static void __init
register_page_bootmem_info(void)
2206 #ifdef CONFIG_NEED_MULTIPLE_NODES
2209 for_each_online_node(i
)
2210 if (NODE_DATA(i
)->node_spanned_pages
)
2211 register_page_bootmem_info_node(NODE_DATA(i
));
2214 void __init
mem_init(void)
2216 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
2218 register_page_bootmem_info();
2222 * Set up the zero page, mark it reserved, so that page count
2223 * is not manipulated when freeing the page from user ptes.
2225 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
2226 if (mem_map_zero
== NULL
) {
2227 prom_printf("paging_init: Cannot alloc zero page.\n");
2230 mark_page_reserved(mem_map_zero
);
2232 mem_init_print_info(NULL
);
2234 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
2235 cheetah_ecache_flush_init();
2238 void free_initmem(void)
2240 unsigned long addr
, initend
;
2243 /* If the physical memory maps were trimmed by kernel command
2244 * line options, don't even try freeing this initmem stuff up.
2245 * The kernel image could have been in the trimmed out region
2246 * and if so the freeing below will free invalid page structs.
2248 if (cmdline_memory_size
)
2252 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2254 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
2255 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
2256 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
2260 ((unsigned long) __va(kern_base
)) -
2261 ((unsigned long) KERNBASE
));
2262 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
2265 free_reserved_page(virt_to_page(page
));
2269 #ifdef CONFIG_BLK_DEV_INITRD
2270 void free_initrd_mem(unsigned long start
, unsigned long end
)
2272 free_reserved_area((void *)start
, (void *)end
, POISON_FREE_INITMEM
,
2277 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2278 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2279 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2280 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2281 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2282 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2284 pgprot_t PAGE_KERNEL __read_mostly
;
2285 EXPORT_SYMBOL(PAGE_KERNEL
);
2287 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
2288 pgprot_t PAGE_COPY __read_mostly
;
2290 pgprot_t PAGE_SHARED __read_mostly
;
2291 EXPORT_SYMBOL(PAGE_SHARED
);
2293 unsigned long pg_iobits __read_mostly
;
2295 unsigned long _PAGE_IE __read_mostly
;
2296 EXPORT_SYMBOL(_PAGE_IE
);
2298 unsigned long _PAGE_E __read_mostly
;
2299 EXPORT_SYMBOL(_PAGE_E
);
2301 unsigned long _PAGE_CACHE __read_mostly
;
2302 EXPORT_SYMBOL(_PAGE_CACHE
);
2304 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2305 int __meminit
vmemmap_populate(unsigned long vstart
, unsigned long vend
,
2308 unsigned long pte_base
;
2310 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2311 _PAGE_CP_4U
| _PAGE_CV_4U
|
2312 _PAGE_P_4U
| _PAGE_W_4U
);
2313 if (tlb_type
== hypervisor
)
2314 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2315 _PAGE_CP_4V
| _PAGE_CV_4V
|
2316 _PAGE_P_4V
| _PAGE_W_4V
);
2318 pte_base
|= _PAGE_PMD_HUGE
;
2320 vstart
= vstart
& PMD_MASK
;
2321 vend
= ALIGN(vend
, PMD_SIZE
);
2322 for (; vstart
< vend
; vstart
+= PMD_SIZE
) {
2323 pgd_t
*pgd
= pgd_offset_k(vstart
);
2328 if (pgd_none(*pgd
)) {
2329 pud_t
*new = vmemmap_alloc_block(PAGE_SIZE
, node
);
2333 pgd_populate(&init_mm
, pgd
, new);
2336 pud
= pud_offset(pgd
, vstart
);
2337 if (pud_none(*pud
)) {
2338 pmd_t
*new = vmemmap_alloc_block(PAGE_SIZE
, node
);
2342 pud_populate(&init_mm
, pud
, new);
2345 pmd
= pmd_offset(pud
, vstart
);
2347 pte
= pmd_val(*pmd
);
2348 if (!(pte
& _PAGE_VALID
)) {
2349 void *block
= vmemmap_alloc_block(PMD_SIZE
, node
);
2354 pmd_val(*pmd
) = pte_base
| __pa(block
);
2361 void vmemmap_free(unsigned long start
, unsigned long end
)
2364 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2366 static void prot_init_common(unsigned long page_none
,
2367 unsigned long page_shared
,
2368 unsigned long page_copy
,
2369 unsigned long page_readonly
,
2370 unsigned long page_exec_bit
)
2372 PAGE_COPY
= __pgprot(page_copy
);
2373 PAGE_SHARED
= __pgprot(page_shared
);
2375 protection_map
[0x0] = __pgprot(page_none
);
2376 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
2377 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
2378 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
2379 protection_map
[0x4] = __pgprot(page_readonly
);
2380 protection_map
[0x5] = __pgprot(page_readonly
);
2381 protection_map
[0x6] = __pgprot(page_copy
);
2382 protection_map
[0x7] = __pgprot(page_copy
);
2383 protection_map
[0x8] = __pgprot(page_none
);
2384 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
2385 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
2386 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
2387 protection_map
[0xc] = __pgprot(page_readonly
);
2388 protection_map
[0xd] = __pgprot(page_readonly
);
2389 protection_map
[0xe] = __pgprot(page_shared
);
2390 protection_map
[0xf] = __pgprot(page_shared
);
2393 static void __init
sun4u_pgprot_init(void)
2395 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2396 unsigned long page_exec_bit
;
2399 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2400 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2401 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2403 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2404 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2405 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2406 _PAGE_EXEC_4U
| _PAGE_L_4U
);
2408 _PAGE_IE
= _PAGE_IE_4U
;
2409 _PAGE_E
= _PAGE_E_4U
;
2410 _PAGE_CACHE
= _PAGE_CACHE_4U
;
2412 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
2413 __ACCESS_BITS_4U
| _PAGE_E_4U
);
2415 #ifdef CONFIG_DEBUG_PAGEALLOC
2416 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2418 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
2421 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
2422 _PAGE_P_4U
| _PAGE_W_4U
);
2424 for (i
= 1; i
< 4; i
++)
2425 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2427 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
2428 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
2429 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
2432 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
2433 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2434 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
2435 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2436 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2437 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2438 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2440 page_exec_bit
= _PAGE_EXEC_4U
;
2442 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2446 static void __init
sun4v_pgprot_init(void)
2448 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2449 unsigned long page_exec_bit
;
2452 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
2453 _PAGE_CACHE_4V
| _PAGE_P_4V
|
2454 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
2456 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
2458 _PAGE_IE
= _PAGE_IE_4V
;
2459 _PAGE_E
= _PAGE_E_4V
;
2460 _PAGE_CACHE
= _PAGE_CACHE_4V
;
2462 #ifdef CONFIG_DEBUG_PAGEALLOC
2463 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2465 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
2468 kern_linear_pte_xor
[0] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
2469 _PAGE_P_4V
| _PAGE_W_4V
);
2471 for (i
= 1; i
< 4; i
++)
2472 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2474 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
2475 __ACCESS_BITS_4V
| _PAGE_E_4V
);
2477 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
2478 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
2479 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
2480 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
2482 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| _PAGE_CACHE_4V
;
2483 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2484 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
2485 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2486 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2487 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2488 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2490 page_exec_bit
= _PAGE_EXEC_4V
;
2492 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2496 unsigned long pte_sz_bits(unsigned long sz
)
2498 if (tlb_type
== hypervisor
) {
2502 return _PAGE_SZ8K_4V
;
2504 return _PAGE_SZ64K_4V
;
2506 return _PAGE_SZ512K_4V
;
2507 case 4 * 1024 * 1024:
2508 return _PAGE_SZ4MB_4V
;
2514 return _PAGE_SZ8K_4U
;
2516 return _PAGE_SZ64K_4U
;
2518 return _PAGE_SZ512K_4U
;
2519 case 4 * 1024 * 1024:
2520 return _PAGE_SZ4MB_4U
;
2525 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
2529 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
2530 pte_val(pte
) |= (((unsigned long)space
) << 32);
2531 pte_val(pte
) |= pte_sz_bits(page_size
);
2536 static unsigned long kern_large_tte(unsigned long paddr
)
2540 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2541 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
2542 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
2543 if (tlb_type
== hypervisor
)
2544 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2545 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_P_4V
|
2546 _PAGE_EXEC_4V
| _PAGE_W_4V
);
2551 /* If not locked, zap it. */
2552 void __flush_tlb_all(void)
2554 unsigned long pstate
;
2557 __asm__
__volatile__("flushw\n\t"
2558 "rdpr %%pstate, %0\n\t"
2559 "wrpr %0, %1, %%pstate"
2562 if (tlb_type
== hypervisor
) {
2563 sun4v_mmu_demap_all();
2564 } else if (tlb_type
== spitfire
) {
2565 for (i
= 0; i
< 64; i
++) {
2566 /* Spitfire Errata #32 workaround */
2567 /* NOTE: Always runs on spitfire, so no
2568 * cheetah+ page size encodings.
2570 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2574 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2576 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
2577 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2580 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
2581 spitfire_put_dtlb_data(i
, 0x0UL
);
2584 /* Spitfire Errata #32 workaround */
2585 /* NOTE: Always runs on spitfire, so no
2586 * cheetah+ page size encodings.
2588 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2592 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2594 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
2595 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2598 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
2599 spitfire_put_itlb_data(i
, 0x0UL
);
2602 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
2603 cheetah_flush_dtlb_all();
2604 cheetah_flush_itlb_all();
2606 __asm__
__volatile__("wrpr %0, 0, %%pstate"
2610 pte_t
*pte_alloc_one_kernel(struct mm_struct
*mm
,
2611 unsigned long address
)
2613 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
|
2614 __GFP_REPEAT
| __GFP_ZERO
);
2618 pte
= (pte_t
*) page_address(page
);
2623 pgtable_t
pte_alloc_one(struct mm_struct
*mm
,
2624 unsigned long address
)
2626 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
|
2627 __GFP_REPEAT
| __GFP_ZERO
);
2630 if (!pgtable_page_ctor(page
)) {
2631 free_hot_cold_page(page
, 0);
2634 return (pte_t
*) page_address(page
);
2637 void pte_free_kernel(struct mm_struct
*mm
, pte_t
*pte
)
2639 free_page((unsigned long)pte
);
2642 static void __pte_free(pgtable_t pte
)
2644 struct page
*page
= virt_to_page(pte
);
2646 pgtable_page_dtor(page
);
2650 void pte_free(struct mm_struct
*mm
, pgtable_t pte
)
2655 void pgtable_free(void *table
, bool is_page
)
2660 kmem_cache_free(pgtable_cache
, table
);
2663 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2664 void update_mmu_cache_pmd(struct vm_area_struct
*vma
, unsigned long addr
,
2667 unsigned long pte
, flags
;
2668 struct mm_struct
*mm
;
2671 if (!pmd_large(entry
) || !pmd_young(entry
))
2674 pte
= pmd_val(entry
);
2676 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2677 if (!(pte
& _PAGE_VALID
))
2680 /* We are fabricating 8MB pages using 4MB real hw pages. */
2681 pte
|= (addr
& (1UL << REAL_HPAGE_SHIFT
));
2685 spin_lock_irqsave(&mm
->context
.lock
, flags
);
2687 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
)
2688 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
2691 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
2693 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2695 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2696 static void context_reload(void *__data
)
2698 struct mm_struct
*mm
= __data
;
2700 if (mm
== current
->mm
)
2701 load_secondary_context(mm
);
2704 void hugetlb_setup(struct pt_regs
*regs
)
2706 struct mm_struct
*mm
= current
->mm
;
2707 struct tsb_config
*tp
;
2709 if (in_atomic() || !mm
) {
2710 const struct exception_table_entry
*entry
;
2712 entry
= search_exception_tables(regs
->tpc
);
2714 regs
->tpc
= entry
->fixup
;
2715 regs
->tnpc
= regs
->tpc
+ 4;
2718 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2719 die_if_kernel("HugeTSB in atomic", regs
);
2722 tp
= &mm
->context
.tsb_block
[MM_TSB_HUGE
];
2723 if (likely(tp
->tsb
== NULL
))
2724 tsb_grow(mm
, MM_TSB_HUGE
, 0);
2726 tsb_context_switch(mm
);
2729 /* On UltraSPARC-III+ and later, configure the second half of
2730 * the Data-TLB for huge pages.
2732 if (tlb_type
== cheetah_plus
) {
2735 spin_lock(&ctx_alloc_lock
);
2736 ctx
= mm
->context
.sparc64_ctx_val
;
2737 ctx
&= ~CTX_PGSZ_MASK
;
2738 ctx
|= CTX_PGSZ_BASE
<< CTX_PGSZ0_SHIFT
;
2739 ctx
|= CTX_PGSZ_HUGE
<< CTX_PGSZ1_SHIFT
;
2741 if (ctx
!= mm
->context
.sparc64_ctx_val
) {
2742 /* When changing the page size fields, we
2743 * must perform a context flush so that no
2744 * stale entries match. This flush must
2745 * occur with the original context register
2748 do_flush_tlb_mm(mm
);
2750 /* Reload the context register of all processors
2751 * also executing in this address space.
2753 mm
->context
.sparc64_ctx_val
= ctx
;
2754 on_each_cpu(context_reload
, mm
, 0);
2756 spin_unlock(&ctx_alloc_lock
);
2761 static struct resource code_resource
= {
2762 .name
= "Kernel code",
2763 .flags
= IORESOURCE_BUSY
| IORESOURCE_MEM
2766 static struct resource data_resource
= {
2767 .name
= "Kernel data",
2768 .flags
= IORESOURCE_BUSY
| IORESOURCE_MEM
2771 static struct resource bss_resource
= {
2772 .name
= "Kernel bss",
2773 .flags
= IORESOURCE_BUSY
| IORESOURCE_MEM
2776 static inline resource_size_t
compute_kern_paddr(void *addr
)
2778 return (resource_size_t
) (addr
- KERNBASE
+ kern_base
);
2781 static void __init
kernel_lds_init(void)
2783 code_resource
.start
= compute_kern_paddr(_text
);
2784 code_resource
.end
= compute_kern_paddr(_etext
- 1);
2785 data_resource
.start
= compute_kern_paddr(_etext
);
2786 data_resource
.end
= compute_kern_paddr(_edata
- 1);
2787 bss_resource
.start
= compute_kern_paddr(__bss_start
);
2788 bss_resource
.end
= compute_kern_paddr(_end
- 1);
2791 static int __init
report_memory(void)
2794 struct resource
*res
;
2798 for (i
= 0; i
< pavail_ents
; i
++) {
2799 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
2802 pr_warn("Failed to allocate source.\n");
2806 res
->name
= "System RAM";
2807 res
->start
= pavail
[i
].phys_addr
;
2808 res
->end
= pavail
[i
].phys_addr
+ pavail
[i
].reg_size
- 1;
2809 res
->flags
= IORESOURCE_BUSY
| IORESOURCE_MEM
;
2811 if (insert_resource(&iomem_resource
, res
) < 0) {
2812 pr_warn("Resource insertion failed.\n");
2816 insert_resource(res
, &code_resource
);
2817 insert_resource(res
, &data_resource
);
2818 insert_resource(res
, &bss_resource
);
2823 device_initcall(report_memory
);
2826 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2828 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2831 void flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
2833 if (start
< HI_OBP_ADDRESS
&& end
> LOW_OBP_ADDRESS
) {
2834 if (start
< LOW_OBP_ADDRESS
) {
2835 flush_tsb_kernel_range(start
, LOW_OBP_ADDRESS
);
2836 do_flush_tlb_kernel_range(start
, LOW_OBP_ADDRESS
);
2838 if (end
> HI_OBP_ADDRESS
) {
2839 flush_tsb_kernel_range(HI_OBP_ADDRESS
, end
);
2840 do_flush_tlb_kernel_range(HI_OBP_ADDRESS
, end
);
2843 flush_tsb_kernel_range(start
, end
);
2844 do_flush_tlb_kernel_range(start
, end
);