2 * srmmu.c: SRMMU specific routines for memory management.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
11 #include <linux/kernel.h>
13 #include <linux/vmalloc.h>
14 #include <linux/pagemap.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/kdebug.h>
21 #include <linux/log2.h>
22 #include <linux/gfp.h>
24 #include <asm/bitext.h>
26 #include <asm/pgalloc.h>
27 #include <asm/pgtable.h>
29 #include <asm/vaddrs.h>
30 #include <asm/traps.h>
33 #include <asm/cache.h>
34 #include <asm/oplib.h>
37 #include <asm/mmu_context.h>
38 #include <asm/io-unit.h>
39 #include <asm/cacheflush.h>
40 #include <asm/tlbflush.h>
42 /* Now the cpu specific definitions. */
43 #include <asm/viking.h>
46 #include <asm/tsunami.h>
47 #include <asm/swift.h>
48 #include <asm/turbosparc.h>
51 #include <asm/btfixup.h>
53 enum mbus_module srmmu_modtype
;
54 static unsigned int hwbug_bitmask
;
58 extern struct resource sparc_iomap
;
60 extern unsigned long last_valid_pfn
;
62 extern unsigned long page_kernel
;
64 static pgd_t
*srmmu_swapper_pg_dir
;
67 #define FLUSH_BEGIN(mm)
70 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
74 BTFIXUPDEF_CALL(void, flush_page_for_dma
, unsigned long)
75 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
77 int flush_page_for_dma_global
= 1;
80 BTFIXUPDEF_CALL(void, local_flush_page_for_dma
, unsigned long)
81 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
86 ctxd_t
*srmmu_ctx_table_phys
;
87 static ctxd_t
*srmmu_context_table
;
89 int viking_mxcc_present
;
90 static DEFINE_SPINLOCK(srmmu_context_spinlock
);
92 static int is_hypersparc
;
95 * In general all page table modifications should use the V8 atomic
96 * swap instruction. This insures the mmu and the cpu are in sync
97 * with respect to ref/mod bits in the page tables.
99 static inline unsigned long srmmu_swap(unsigned long *addr
, unsigned long value
)
101 __asm__
__volatile__("swap [%2], %0" : "=&r" (value
) : "0" (value
), "r" (addr
));
105 static inline void srmmu_set_pte(pte_t
*ptep
, pte_t pteval
)
107 srmmu_swap((unsigned long *)ptep
, pte_val(pteval
));
110 /* The very generic SRMMU page table operations. */
111 static inline int srmmu_device_memory(unsigned long x
)
113 return ((x
& 0xF0000000) != 0);
116 static int srmmu_cache_pagetables
;
118 /* these will be initialized in srmmu_nocache_calcsize() */
119 static unsigned long srmmu_nocache_size
;
120 static unsigned long srmmu_nocache_end
;
122 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
123 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
125 /* The context table is a nocache user with the biggest alignment needs. */
126 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
128 void *srmmu_nocache_pool
;
129 void *srmmu_nocache_bitmap
;
130 static struct bit_map srmmu_nocache_map
;
132 static unsigned long srmmu_pte_pfn(pte_t pte
)
134 if (srmmu_device_memory(pte_val(pte
))) {
135 /* Just return something that will cause
136 * pfn_valid() to return false. This makes
137 * copy_one_pte() to just directly copy to
142 return (pte_val(pte
) & SRMMU_PTE_PMASK
) >> (PAGE_SHIFT
-4);
145 static struct page
*srmmu_pmd_page(pmd_t pmd
)
148 if (srmmu_device_memory(pmd_val(pmd
)))
150 return pfn_to_page((pmd_val(pmd
) & SRMMU_PTD_PMASK
) >> (PAGE_SHIFT
-4));
153 static inline unsigned long srmmu_pgd_page(pgd_t pgd
)
154 { return srmmu_device_memory(pgd_val(pgd
))?~0:(unsigned long)__nocache_va((pgd_val(pgd
) & SRMMU_PTD_PMASK
) << 4); }
157 static inline int srmmu_pte_none(pte_t pte
)
158 { return !(pte_val(pte
) & 0xFFFFFFF); }
160 static inline int srmmu_pte_present(pte_t pte
)
161 { return ((pte_val(pte
) & SRMMU_ET_MASK
) == SRMMU_ET_PTE
); }
163 static inline void srmmu_pte_clear(pte_t
*ptep
)
164 { srmmu_set_pte(ptep
, __pte(0)); }
166 static inline int srmmu_pmd_none(pmd_t pmd
)
167 { return !(pmd_val(pmd
) & 0xFFFFFFF); }
169 static inline int srmmu_pmd_bad(pmd_t pmd
)
170 { return (pmd_val(pmd
) & SRMMU_ET_MASK
) != SRMMU_ET_PTD
; }
172 static inline int srmmu_pmd_present(pmd_t pmd
)
173 { return ((pmd_val(pmd
) & SRMMU_ET_MASK
) == SRMMU_ET_PTD
); }
175 static inline void srmmu_pmd_clear(pmd_t
*pmdp
) {
177 for (i
= 0; i
< PTRS_PER_PTE
/SRMMU_REAL_PTRS_PER_PTE
; i
++)
178 srmmu_set_pte((pte_t
*)&pmdp
->pmdv
[i
], __pte(0));
181 static inline int srmmu_pgd_none(pgd_t pgd
)
182 { return !(pgd_val(pgd
) & 0xFFFFFFF); }
184 static inline int srmmu_pgd_bad(pgd_t pgd
)
185 { return (pgd_val(pgd
) & SRMMU_ET_MASK
) != SRMMU_ET_PTD
; }
187 static inline int srmmu_pgd_present(pgd_t pgd
)
188 { return ((pgd_val(pgd
) & SRMMU_ET_MASK
) == SRMMU_ET_PTD
); }
190 static inline void srmmu_pgd_clear(pgd_t
* pgdp
)
191 { srmmu_set_pte((pte_t
*)pgdp
, __pte(0)); }
193 static inline pte_t
srmmu_pte_wrprotect(pte_t pte
)
194 { return __pte(pte_val(pte
) & ~SRMMU_WRITE
);}
196 static inline pte_t
srmmu_pte_mkclean(pte_t pte
)
197 { return __pte(pte_val(pte
) & ~SRMMU_DIRTY
);}
199 static inline pte_t
srmmu_pte_mkold(pte_t pte
)
200 { return __pte(pte_val(pte
) & ~SRMMU_REF
);}
202 static inline pte_t
srmmu_pte_mkwrite(pte_t pte
)
203 { return __pte(pte_val(pte
) | SRMMU_WRITE
);}
205 static inline pte_t
srmmu_pte_mkdirty(pte_t pte
)
206 { return __pte(pte_val(pte
) | SRMMU_DIRTY
);}
208 static inline pte_t
srmmu_pte_mkyoung(pte_t pte
)
209 { return __pte(pte_val(pte
) | SRMMU_REF
);}
212 * Conversion functions: convert a page and protection to a page entry,
213 * and a page entry and page directory to the page they refer to.
215 static pte_t
srmmu_mk_pte(struct page
*page
, pgprot_t pgprot
)
216 { return __pte((page_to_pfn(page
) << (PAGE_SHIFT
-4)) | pgprot_val(pgprot
)); }
218 static pte_t
srmmu_mk_pte_phys(unsigned long page
, pgprot_t pgprot
)
219 { return __pte(((page
) >> 4) | pgprot_val(pgprot
)); }
221 static pte_t
srmmu_mk_pte_io(unsigned long page
, pgprot_t pgprot
, int space
)
222 { return __pte(((page
) >> 4) | (space
<< 28) | pgprot_val(pgprot
)); }
224 /* XXX should we hyper_flush_whole_icache here - Anton */
225 static inline void srmmu_ctxd_set(ctxd_t
*ctxp
, pgd_t
*pgdp
)
226 { srmmu_set_pte((pte_t
*)ctxp
, (SRMMU_ET_PTD
| (__nocache_pa((unsigned long) pgdp
) >> 4))); }
228 static inline void srmmu_pgd_set(pgd_t
* pgdp
, pmd_t
* pmdp
)
229 { srmmu_set_pte((pte_t
*)pgdp
, (SRMMU_ET_PTD
| (__nocache_pa((unsigned long) pmdp
) >> 4))); }
231 static void srmmu_pmd_set(pmd_t
*pmdp
, pte_t
*ptep
)
233 unsigned long ptp
; /* Physical address, shifted right by 4 */
236 ptp
= __nocache_pa((unsigned long) ptep
) >> 4;
237 for (i
= 0; i
< PTRS_PER_PTE
/SRMMU_REAL_PTRS_PER_PTE
; i
++) {
238 srmmu_set_pte((pte_t
*)&pmdp
->pmdv
[i
], SRMMU_ET_PTD
| ptp
);
239 ptp
+= (SRMMU_REAL_PTRS_PER_PTE
*sizeof(pte_t
) >> 4);
243 static void srmmu_pmd_populate(pmd_t
*pmdp
, struct page
*ptep
)
245 unsigned long ptp
; /* Physical address, shifted right by 4 */
248 ptp
= page_to_pfn(ptep
) << (PAGE_SHIFT
-4); /* watch for overflow */
249 for (i
= 0; i
< PTRS_PER_PTE
/SRMMU_REAL_PTRS_PER_PTE
; i
++) {
250 srmmu_set_pte((pte_t
*)&pmdp
->pmdv
[i
], SRMMU_ET_PTD
| ptp
);
251 ptp
+= (SRMMU_REAL_PTRS_PER_PTE
*sizeof(pte_t
) >> 4);
255 static inline pte_t
srmmu_pte_modify(pte_t pte
, pgprot_t newprot
)
256 { return __pte((pte_val(pte
) & SRMMU_CHG_MASK
) | pgprot_val(newprot
)); }
258 /* to find an entry in a top-level page table... */
259 static inline pgd_t
*srmmu_pgd_offset(struct mm_struct
* mm
, unsigned long address
)
260 { return mm
->pgd
+ (address
>> SRMMU_PGDIR_SHIFT
); }
262 /* Find an entry in the second-level page table.. */
263 static inline pmd_t
*srmmu_pmd_offset(pgd_t
* dir
, unsigned long address
)
265 return (pmd_t
*) srmmu_pgd_page(*dir
) +
266 ((address
>> PMD_SHIFT
) & (PTRS_PER_PMD
- 1));
269 /* Find an entry in the third-level page table.. */
270 static inline pte_t
*srmmu_pte_offset(pmd_t
* dir
, unsigned long address
)
274 pte
= __nocache_va((dir
->pmdv
[0] & SRMMU_PTD_PMASK
) << 4);
275 return (pte_t
*) pte
+
276 ((address
>> PAGE_SHIFT
) & (PTRS_PER_PTE
- 1));
279 static unsigned long srmmu_swp_type(swp_entry_t entry
)
281 return (entry
.val
>> SRMMU_SWP_TYPE_SHIFT
) & SRMMU_SWP_TYPE_MASK
;
284 static unsigned long srmmu_swp_offset(swp_entry_t entry
)
286 return (entry
.val
>> SRMMU_SWP_OFF_SHIFT
) & SRMMU_SWP_OFF_MASK
;
289 static swp_entry_t
srmmu_swp_entry(unsigned long type
, unsigned long offset
)
291 return (swp_entry_t
) {
292 (type
& SRMMU_SWP_TYPE_MASK
) << SRMMU_SWP_TYPE_SHIFT
293 | (offset
& SRMMU_SWP_OFF_MASK
) << SRMMU_SWP_OFF_SHIFT
};
297 * size: bytes to allocate in the nocache area.
298 * align: bytes, number to align at.
299 * Returns the virtual address of the allocated area.
301 static unsigned long __srmmu_get_nocache(int size
, int align
)
305 if (size
< SRMMU_NOCACHE_BITMAP_SHIFT
) {
306 printk("Size 0x%x too small for nocache request\n", size
);
307 size
= SRMMU_NOCACHE_BITMAP_SHIFT
;
309 if (size
& (SRMMU_NOCACHE_BITMAP_SHIFT
-1)) {
310 printk("Size 0x%x unaligned int nocache request\n", size
);
311 size
+= SRMMU_NOCACHE_BITMAP_SHIFT
-1;
313 BUG_ON(align
> SRMMU_NOCACHE_ALIGN_MAX
);
315 offset
= bit_map_string_get(&srmmu_nocache_map
,
316 size
>> SRMMU_NOCACHE_BITMAP_SHIFT
,
317 align
>> SRMMU_NOCACHE_BITMAP_SHIFT
);
319 printk("srmmu: out of nocache %d: %d/%d\n",
320 size
, (int) srmmu_nocache_size
,
321 srmmu_nocache_map
.used
<< SRMMU_NOCACHE_BITMAP_SHIFT
);
325 return (SRMMU_NOCACHE_VADDR
+ (offset
<< SRMMU_NOCACHE_BITMAP_SHIFT
));
328 static unsigned long srmmu_get_nocache(int size
, int align
)
332 tmp
= __srmmu_get_nocache(size
, align
);
335 memset((void *)tmp
, 0, size
);
340 static void srmmu_free_nocache(unsigned long vaddr
, int size
)
344 if (vaddr
< SRMMU_NOCACHE_VADDR
) {
345 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
346 vaddr
, (unsigned long)SRMMU_NOCACHE_VADDR
);
349 if (vaddr
+size
> srmmu_nocache_end
) {
350 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
351 vaddr
, srmmu_nocache_end
);
354 if (!is_power_of_2(size
)) {
355 printk("Size 0x%x is not a power of 2\n", size
);
358 if (size
< SRMMU_NOCACHE_BITMAP_SHIFT
) {
359 printk("Size 0x%x is too small\n", size
);
362 if (vaddr
& (size
-1)) {
363 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr
, size
);
367 offset
= (vaddr
- SRMMU_NOCACHE_VADDR
) >> SRMMU_NOCACHE_BITMAP_SHIFT
;
368 size
= size
>> SRMMU_NOCACHE_BITMAP_SHIFT
;
370 bit_map_clear(&srmmu_nocache_map
, offset
, size
);
373 static void srmmu_early_allocate_ptable_skeleton(unsigned long start
,
376 extern unsigned long probe_memory(void); /* in fault.c */
379 * Reserve nocache dynamically proportionally to the amount of
380 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
382 static void srmmu_nocache_calcsize(void)
384 unsigned long sysmemavail
= probe_memory() / 1024;
385 int srmmu_nocache_npages
;
387 srmmu_nocache_npages
=
388 sysmemavail
/ SRMMU_NOCACHE_ALCRATIO
/ 1024 * 256;
390 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
391 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
392 if (srmmu_nocache_npages
< SRMMU_MIN_NOCACHE_PAGES
)
393 srmmu_nocache_npages
= SRMMU_MIN_NOCACHE_PAGES
;
395 /* anything above 1280 blows up */
396 if (srmmu_nocache_npages
> SRMMU_MAX_NOCACHE_PAGES
)
397 srmmu_nocache_npages
= SRMMU_MAX_NOCACHE_PAGES
;
399 srmmu_nocache_size
= srmmu_nocache_npages
* PAGE_SIZE
;
400 srmmu_nocache_end
= SRMMU_NOCACHE_VADDR
+ srmmu_nocache_size
;
403 static void __init
srmmu_nocache_init(void)
405 unsigned int bitmap_bits
;
409 unsigned long paddr
, vaddr
;
410 unsigned long pteval
;
412 bitmap_bits
= srmmu_nocache_size
>> SRMMU_NOCACHE_BITMAP_SHIFT
;
414 srmmu_nocache_pool
= __alloc_bootmem(srmmu_nocache_size
,
415 SRMMU_NOCACHE_ALIGN_MAX
, 0UL);
416 memset(srmmu_nocache_pool
, 0, srmmu_nocache_size
);
418 srmmu_nocache_bitmap
= __alloc_bootmem(bitmap_bits
>> 3, SMP_CACHE_BYTES
, 0UL);
419 bit_map_init(&srmmu_nocache_map
, srmmu_nocache_bitmap
, bitmap_bits
);
421 srmmu_swapper_pg_dir
= (pgd_t
*)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE
, SRMMU_PGD_TABLE_SIZE
);
422 memset(__nocache_fix(srmmu_swapper_pg_dir
), 0, SRMMU_PGD_TABLE_SIZE
);
423 init_mm
.pgd
= srmmu_swapper_pg_dir
;
425 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR
, srmmu_nocache_end
);
427 paddr
= __pa((unsigned long)srmmu_nocache_pool
);
428 vaddr
= SRMMU_NOCACHE_VADDR
;
430 while (vaddr
< srmmu_nocache_end
) {
431 pgd
= pgd_offset_k(vaddr
);
432 pmd
= srmmu_pmd_offset(__nocache_fix(pgd
), vaddr
);
433 pte
= srmmu_pte_offset(__nocache_fix(pmd
), vaddr
);
435 pteval
= ((paddr
>> 4) | SRMMU_ET_PTE
| SRMMU_PRIV
);
437 if (srmmu_cache_pagetables
)
438 pteval
|= SRMMU_CACHE
;
440 srmmu_set_pte(__nocache_fix(pte
), __pte(pteval
));
450 static inline pgd_t
*srmmu_get_pgd_fast(void)
454 pgd
= (pgd_t
*)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE
, SRMMU_PGD_TABLE_SIZE
);
456 pgd_t
*init
= pgd_offset_k(0);
457 memset(pgd
, 0, USER_PTRS_PER_PGD
* sizeof(pgd_t
));
458 memcpy(pgd
+ USER_PTRS_PER_PGD
, init
+ USER_PTRS_PER_PGD
,
459 (PTRS_PER_PGD
- USER_PTRS_PER_PGD
) * sizeof(pgd_t
));
465 static void srmmu_free_pgd_fast(pgd_t
*pgd
)
467 srmmu_free_nocache((unsigned long)pgd
, SRMMU_PGD_TABLE_SIZE
);
470 static pmd_t
*srmmu_pmd_alloc_one(struct mm_struct
*mm
, unsigned long address
)
472 return (pmd_t
*)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
475 static void srmmu_pmd_free(pmd_t
* pmd
)
477 srmmu_free_nocache((unsigned long)pmd
, SRMMU_PMD_TABLE_SIZE
);
481 * Hardware needs alignment to 256 only, but we align to whole page size
482 * to reduce fragmentation problems due to the buddy principle.
483 * XXX Provide actual fragmentation statistics in /proc.
485 * Alignments up to the page size are the same for physical and virtual
486 * addresses of the nocache area.
489 srmmu_pte_alloc_one_kernel(struct mm_struct
*mm
, unsigned long address
)
491 return (pte_t
*)srmmu_get_nocache(PTE_SIZE
, PTE_SIZE
);
495 srmmu_pte_alloc_one(struct mm_struct
*mm
, unsigned long address
)
500 if ((pte
= (unsigned long)srmmu_pte_alloc_one_kernel(mm
, address
)) == 0)
502 page
= pfn_to_page( __nocache_pa(pte
) >> PAGE_SHIFT
);
503 pgtable_page_ctor(page
);
507 static void srmmu_free_pte_fast(pte_t
*pte
)
509 srmmu_free_nocache((unsigned long)pte
, PTE_SIZE
);
512 static void srmmu_pte_free(pgtable_t pte
)
516 pgtable_page_dtor(pte
);
517 p
= (unsigned long)page_address(pte
); /* Cached address (for test) */
520 p
= page_to_pfn(pte
) << PAGE_SHIFT
; /* Physical address */
521 p
= (unsigned long) __nocache_va(p
); /* Nocached virtual */
522 srmmu_free_nocache(p
, PTE_SIZE
);
527 static inline void alloc_context(struct mm_struct
*old_mm
, struct mm_struct
*mm
)
529 struct ctx_list
*ctxp
;
531 ctxp
= ctx_free
.next
;
532 if(ctxp
!= &ctx_free
) {
533 remove_from_ctx_list(ctxp
);
534 add_to_used_ctxlist(ctxp
);
535 mm
->context
= ctxp
->ctx_number
;
539 ctxp
= ctx_used
.next
;
540 if(ctxp
->ctx_mm
== old_mm
)
542 if(ctxp
== &ctx_used
)
543 panic("out of mmu contexts");
544 flush_cache_mm(ctxp
->ctx_mm
);
545 flush_tlb_mm(ctxp
->ctx_mm
);
546 remove_from_ctx_list(ctxp
);
547 add_to_used_ctxlist(ctxp
);
548 ctxp
->ctx_mm
->context
= NO_CONTEXT
;
550 mm
->context
= ctxp
->ctx_number
;
553 static inline void free_context(int context
)
555 struct ctx_list
*ctx_old
;
557 ctx_old
= ctx_list_pool
+ context
;
558 remove_from_ctx_list(ctx_old
);
559 add_to_free_ctxlist(ctx_old
);
563 static void srmmu_switch_mm(struct mm_struct
*old_mm
, struct mm_struct
*mm
,
564 struct task_struct
*tsk
, int cpu
)
566 if(mm
->context
== NO_CONTEXT
) {
567 spin_lock(&srmmu_context_spinlock
);
568 alloc_context(old_mm
, mm
);
569 spin_unlock(&srmmu_context_spinlock
);
570 srmmu_ctxd_set(&srmmu_context_table
[mm
->context
], mm
->pgd
);
573 if (sparc_cpu_model
== sparc_leon
)
577 hyper_flush_whole_icache();
579 srmmu_set_context(mm
->context
);
582 /* Low level IO area allocation on the SRMMU. */
583 static inline void srmmu_mapioaddr(unsigned long physaddr
,
584 unsigned long virt_addr
, int bus_type
)
591 physaddr
&= PAGE_MASK
;
592 pgdp
= pgd_offset_k(virt_addr
);
593 pmdp
= srmmu_pmd_offset(pgdp
, virt_addr
);
594 ptep
= srmmu_pte_offset(pmdp
, virt_addr
);
595 tmp
= (physaddr
>> 4) | SRMMU_ET_PTE
;
598 * I need to test whether this is consistent over all
599 * sun4m's. The bus_type represents the upper 4 bits of
600 * 36-bit physical address on the I/O space lines...
602 tmp
|= (bus_type
<< 28);
604 __flush_page_to_ram(virt_addr
);
605 srmmu_set_pte(ptep
, __pte(tmp
));
608 static void srmmu_mapiorange(unsigned int bus
, unsigned long xpa
,
609 unsigned long xva
, unsigned int len
)
613 srmmu_mapioaddr(xpa
, xva
, bus
);
620 static inline void srmmu_unmapioaddr(unsigned long virt_addr
)
626 pgdp
= pgd_offset_k(virt_addr
);
627 pmdp
= srmmu_pmd_offset(pgdp
, virt_addr
);
628 ptep
= srmmu_pte_offset(pmdp
, virt_addr
);
630 /* No need to flush uncacheable page. */
631 srmmu_pte_clear(ptep
);
634 static void srmmu_unmapiorange(unsigned long virt_addr
, unsigned int len
)
638 srmmu_unmapioaddr(virt_addr
);
639 virt_addr
+= PAGE_SIZE
;
645 * On the SRMMU we do not have the problems with limited tlb entries
646 * for mapping kernel pages, so we just take things from the free page
647 * pool. As a side effect we are putting a little too much pressure
648 * on the gfp() subsystem. This setup also makes the logic of the
649 * iommu mapping code a lot easier as we can transparently handle
650 * mappings on the kernel stack without any special code.
652 struct thread_info
*alloc_thread_info_node(struct task_struct
*tsk
, int node
)
654 struct thread_info
*ret
;
656 ret
= (struct thread_info
*)__get_free_pages(GFP_KERNEL
,
658 #ifdef CONFIG_DEBUG_STACK_USAGE
660 memset(ret
, 0, PAGE_SIZE
<< THREAD_INFO_ORDER
);
661 #endif /* DEBUG_STACK_USAGE */
666 void free_thread_info(struct thread_info
*ti
)
668 free_pages((unsigned long)ti
, THREAD_INFO_ORDER
);
672 extern void tsunami_flush_cache_all(void);
673 extern void tsunami_flush_cache_mm(struct mm_struct
*mm
);
674 extern void tsunami_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
675 extern void tsunami_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
676 extern void tsunami_flush_page_to_ram(unsigned long page
);
677 extern void tsunami_flush_page_for_dma(unsigned long page
);
678 extern void tsunami_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
679 extern void tsunami_flush_tlb_all(void);
680 extern void tsunami_flush_tlb_mm(struct mm_struct
*mm
);
681 extern void tsunami_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
682 extern void tsunami_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
683 extern void tsunami_setup_blockops(void);
686 * Workaround, until we find what's going on with Swift. When low on memory,
687 * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
688 * out it is already in page tables/ fault again on the same instruction.
689 * I really don't understand it, have checked it and contexts
690 * are right, flush_tlb_all is done as well, and it faults again...
693 * The following code is a deadwood that may be necessary when
694 * we start to make precise page flushes again. --zaitcev
696 static void swift_update_mmu_cache(struct vm_area_struct
* vma
, unsigned long address
, pte_t
*ptep
)
699 static unsigned long last
;
701 /* unsigned int n; */
703 if (address
== last
) {
704 val
= srmmu_hwprobe(address
);
705 if (val
!= 0 && pte_val(*ptep
) != val
) {
706 printk("swift_update_mmu_cache: "
707 "addr %lx put %08x probed %08x from %pf\n",
708 address
, pte_val(*ptep
), val
,
709 __builtin_return_address(0));
710 srmmu_flush_whole_tlb();
718 extern void swift_flush_cache_all(void);
719 extern void swift_flush_cache_mm(struct mm_struct
*mm
);
720 extern void swift_flush_cache_range(struct vm_area_struct
*vma
,
721 unsigned long start
, unsigned long end
);
722 extern void swift_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
723 extern void swift_flush_page_to_ram(unsigned long page
);
724 extern void swift_flush_page_for_dma(unsigned long page
);
725 extern void swift_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
726 extern void swift_flush_tlb_all(void);
727 extern void swift_flush_tlb_mm(struct mm_struct
*mm
);
728 extern void swift_flush_tlb_range(struct vm_area_struct
*vma
,
729 unsigned long start
, unsigned long end
);
730 extern void swift_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
732 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
733 void swift_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
738 if ((ctx1
= vma
->vm_mm
->context
) != -1) {
739 cctx
= srmmu_get_context();
740 /* Is context # ever different from current context? P3 */
742 printk("flush ctx %02x curr %02x\n", ctx1
, cctx
);
743 srmmu_set_context(ctx1
);
744 swift_flush_page(page
);
745 __asm__
__volatile__("sta %%g0, [%0] %1\n\t" : :
746 "r" (page
), "i" (ASI_M_FLUSH_PROBE
));
747 srmmu_set_context(cctx
);
749 /* Rm. prot. bits from virt. c. */
750 /* swift_flush_cache_all(); */
751 /* swift_flush_cache_page(vma, page); */
752 swift_flush_page(page
);
754 __asm__
__volatile__("sta %%g0, [%0] %1\n\t" : :
755 "r" (page
), "i" (ASI_M_FLUSH_PROBE
));
756 /* same as above: srmmu_flush_tlb_page() */
763 * The following are all MBUS based SRMMU modules, and therefore could
764 * be found in a multiprocessor configuration. On the whole, these
765 * chips seems to be much more touchy about DVMA and page tables
766 * with respect to cache coherency.
769 /* Cypress flushes. */
770 static void cypress_flush_cache_all(void)
772 volatile unsigned long cypress_sucks
;
773 unsigned long faddr
, tagval
;
775 flush_user_windows();
776 for(faddr
= 0; faddr
< 0x10000; faddr
+= 0x20) {
777 __asm__
__volatile__("lda [%1 + %2] %3, %0\n\t" :
779 "r" (faddr
), "r" (0x40000),
780 "i" (ASI_M_DATAC_TAG
));
782 /* If modified and valid, kick it. */
783 if((tagval
& 0x60) == 0x60)
784 cypress_sucks
= *(unsigned long *)(0xf0020000 + faddr
);
788 static void cypress_flush_cache_mm(struct mm_struct
*mm
)
790 register unsigned long a
, b
, c
, d
, e
, f
, g
;
791 unsigned long flags
, faddr
;
795 flush_user_windows();
796 local_irq_save(flags
);
797 octx
= srmmu_get_context();
798 srmmu_set_context(mm
->context
);
799 a
= 0x20; b
= 0x40; c
= 0x60;
800 d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
802 faddr
= (0x10000 - 0x100);
807 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
808 "sta %%g0, [%0 + %2] %1\n\t"
809 "sta %%g0, [%0 + %3] %1\n\t"
810 "sta %%g0, [%0 + %4] %1\n\t"
811 "sta %%g0, [%0 + %5] %1\n\t"
812 "sta %%g0, [%0 + %6] %1\n\t"
813 "sta %%g0, [%0 + %7] %1\n\t"
814 "sta %%g0, [%0 + %8] %1\n\t" : :
815 "r" (faddr
), "i" (ASI_M_FLUSH_CTX
),
816 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
817 "r" (e
), "r" (f
), "r" (g
));
819 srmmu_set_context(octx
);
820 local_irq_restore(flags
);
824 static void cypress_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
826 struct mm_struct
*mm
= vma
->vm_mm
;
827 register unsigned long a
, b
, c
, d
, e
, f
, g
;
828 unsigned long flags
, faddr
;
832 flush_user_windows();
833 local_irq_save(flags
);
834 octx
= srmmu_get_context();
835 srmmu_set_context(mm
->context
);
836 a
= 0x20; b
= 0x40; c
= 0x60;
837 d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
839 start
&= SRMMU_REAL_PMD_MASK
;
841 faddr
= (start
+ (0x10000 - 0x100));
846 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
847 "sta %%g0, [%0 + %2] %1\n\t"
848 "sta %%g0, [%0 + %3] %1\n\t"
849 "sta %%g0, [%0 + %4] %1\n\t"
850 "sta %%g0, [%0 + %5] %1\n\t"
851 "sta %%g0, [%0 + %6] %1\n\t"
852 "sta %%g0, [%0 + %7] %1\n\t"
853 "sta %%g0, [%0 + %8] %1\n\t" : :
855 "i" (ASI_M_FLUSH_SEG
),
856 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
857 "r" (e
), "r" (f
), "r" (g
));
858 } while (faddr
!= start
);
859 start
+= SRMMU_REAL_PMD_SIZE
;
861 srmmu_set_context(octx
);
862 local_irq_restore(flags
);
866 static void cypress_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
)
868 register unsigned long a
, b
, c
, d
, e
, f
, g
;
869 struct mm_struct
*mm
= vma
->vm_mm
;
870 unsigned long flags
, line
;
874 flush_user_windows();
875 local_irq_save(flags
);
876 octx
= srmmu_get_context();
877 srmmu_set_context(mm
->context
);
878 a
= 0x20; b
= 0x40; c
= 0x60;
879 d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
882 line
= (page
+ PAGE_SIZE
) - 0x100;
887 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
888 "sta %%g0, [%0 + %2] %1\n\t"
889 "sta %%g0, [%0 + %3] %1\n\t"
890 "sta %%g0, [%0 + %4] %1\n\t"
891 "sta %%g0, [%0 + %5] %1\n\t"
892 "sta %%g0, [%0 + %6] %1\n\t"
893 "sta %%g0, [%0 + %7] %1\n\t"
894 "sta %%g0, [%0 + %8] %1\n\t" : :
896 "i" (ASI_M_FLUSH_PAGE
),
897 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
898 "r" (e
), "r" (f
), "r" (g
));
899 } while(line
!= page
);
900 srmmu_set_context(octx
);
901 local_irq_restore(flags
);
905 /* Cypress is copy-back, at least that is how we configure it. */
906 static void cypress_flush_page_to_ram(unsigned long page
)
908 register unsigned long a
, b
, c
, d
, e
, f
, g
;
911 a
= 0x20; b
= 0x40; c
= 0x60; d
= 0x80; e
= 0xa0; f
= 0xc0; g
= 0xe0;
913 line
= (page
+ PAGE_SIZE
) - 0x100;
918 __asm__
__volatile__("sta %%g0, [%0] %1\n\t"
919 "sta %%g0, [%0 + %2] %1\n\t"
920 "sta %%g0, [%0 + %3] %1\n\t"
921 "sta %%g0, [%0 + %4] %1\n\t"
922 "sta %%g0, [%0 + %5] %1\n\t"
923 "sta %%g0, [%0 + %6] %1\n\t"
924 "sta %%g0, [%0 + %7] %1\n\t"
925 "sta %%g0, [%0 + %8] %1\n\t" : :
927 "i" (ASI_M_FLUSH_PAGE
),
928 "r" (a
), "r" (b
), "r" (c
), "r" (d
),
929 "r" (e
), "r" (f
), "r" (g
));
930 } while(line
!= page
);
933 /* Cypress is also IO cache coherent. */
934 static void cypress_flush_page_for_dma(unsigned long page
)
938 /* Cypress has unified L2 VIPT, from which both instructions and data
939 * are stored. It does not have an onboard icache of any sort, therefore
940 * no flush is necessary.
942 static void cypress_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
)
946 static void cypress_flush_tlb_all(void)
948 srmmu_flush_whole_tlb();
951 static void cypress_flush_tlb_mm(struct mm_struct
*mm
)
954 __asm__
__volatile__(
955 "lda [%0] %3, %%g5\n\t"
956 "sta %2, [%0] %3\n\t"
957 "sta %%g0, [%1] %4\n\t"
958 "sta %%g5, [%0] %3\n"
960 : "r" (SRMMU_CTX_REG
), "r" (0x300), "r" (mm
->context
),
961 "i" (ASI_M_MMUREGS
), "i" (ASI_M_FLUSH_PROBE
)
966 static void cypress_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
968 struct mm_struct
*mm
= vma
->vm_mm
;
972 start
&= SRMMU_PGDIR_MASK
;
973 size
= SRMMU_PGDIR_ALIGN(end
) - start
;
974 __asm__
__volatile__(
975 "lda [%0] %5, %%g5\n\t"
978 "subcc %3, %4, %3\n\t"
980 " sta %%g0, [%2 + %3] %6\n\t"
981 "sta %%g5, [%0] %5\n"
983 : "r" (SRMMU_CTX_REG
), "r" (mm
->context
), "r" (start
| 0x200),
984 "r" (size
), "r" (SRMMU_PGDIR_SIZE
), "i" (ASI_M_MMUREGS
),
985 "i" (ASI_M_FLUSH_PROBE
)
990 static void cypress_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
992 struct mm_struct
*mm
= vma
->vm_mm
;
995 __asm__
__volatile__(
996 "lda [%0] %3, %%g5\n\t"
997 "sta %1, [%0] %3\n\t"
998 "sta %%g0, [%2] %4\n\t"
999 "sta %%g5, [%0] %3\n"
1001 : "r" (SRMMU_CTX_REG
), "r" (mm
->context
), "r" (page
& PAGE_MASK
),
1002 "i" (ASI_M_MMUREGS
), "i" (ASI_M_FLUSH_PROBE
)
1008 extern void viking_flush_cache_all(void);
1009 extern void viking_flush_cache_mm(struct mm_struct
*mm
);
1010 extern void viking_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
,
1012 extern void viking_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
1013 extern void viking_flush_page_to_ram(unsigned long page
);
1014 extern void viking_flush_page_for_dma(unsigned long page
);
1015 extern void viking_flush_sig_insns(struct mm_struct
*mm
, unsigned long addr
);
1016 extern void viking_flush_page(unsigned long page
);
1017 extern void viking_mxcc_flush_page(unsigned long page
);
1018 extern void viking_flush_tlb_all(void);
1019 extern void viking_flush_tlb_mm(struct mm_struct
*mm
);
1020 extern void viking_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
1022 extern void viking_flush_tlb_page(struct vm_area_struct
*vma
,
1023 unsigned long page
);
1024 extern void sun4dsmp_flush_tlb_all(void);
1025 extern void sun4dsmp_flush_tlb_mm(struct mm_struct
*mm
);
1026 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
1028 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct
*vma
,
1029 unsigned long page
);
1032 extern void hypersparc_flush_cache_all(void);
1033 extern void hypersparc_flush_cache_mm(struct mm_struct
*mm
);
1034 extern void hypersparc_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
1035 extern void hypersparc_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
1036 extern void hypersparc_flush_page_to_ram(unsigned long page
);
1037 extern void hypersparc_flush_page_for_dma(unsigned long page
);
1038 extern void hypersparc_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
1039 extern void hypersparc_flush_tlb_all(void);
1040 extern void hypersparc_flush_tlb_mm(struct mm_struct
*mm
);
1041 extern void hypersparc_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
1042 extern void hypersparc_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
1043 extern void hypersparc_setup_blockops(void);
1046 * NOTE: All of this startup code assumes the low 16mb (approx.) of
1047 * kernel mappings are done with one single contiguous chunk of
1048 * ram. On small ram machines (classics mainly) we only get
1049 * around 8mb mapped for us.
1052 static void __init
early_pgtable_allocfail(char *type
)
1054 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type
);
1058 static void __init
srmmu_early_allocate_ptable_skeleton(unsigned long start
,
1065 while(start
< end
) {
1066 pgdp
= pgd_offset_k(start
);
1067 if(srmmu_pgd_none(*(pgd_t
*)__nocache_fix(pgdp
))) {
1068 pmdp
= (pmd_t
*) __srmmu_get_nocache(
1069 SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
1071 early_pgtable_allocfail("pmd");
1072 memset(__nocache_fix(pmdp
), 0, SRMMU_PMD_TABLE_SIZE
);
1073 srmmu_pgd_set(__nocache_fix(pgdp
), pmdp
);
1075 pmdp
= srmmu_pmd_offset(__nocache_fix(pgdp
), start
);
1076 if(srmmu_pmd_none(*(pmd_t
*)__nocache_fix(pmdp
))) {
1077 ptep
= (pte_t
*)__srmmu_get_nocache(PTE_SIZE
, PTE_SIZE
);
1079 early_pgtable_allocfail("pte");
1080 memset(__nocache_fix(ptep
), 0, PTE_SIZE
);
1081 srmmu_pmd_set(__nocache_fix(pmdp
), ptep
);
1083 if (start
> (0xffffffffUL
- PMD_SIZE
))
1085 start
= (start
+ PMD_SIZE
) & PMD_MASK
;
1089 static void __init
srmmu_allocate_ptable_skeleton(unsigned long start
,
1096 while(start
< end
) {
1097 pgdp
= pgd_offset_k(start
);
1098 if(srmmu_pgd_none(*pgdp
)) {
1099 pmdp
= (pmd_t
*)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
1101 early_pgtable_allocfail("pmd");
1102 memset(pmdp
, 0, SRMMU_PMD_TABLE_SIZE
);
1103 srmmu_pgd_set(pgdp
, pmdp
);
1105 pmdp
= srmmu_pmd_offset(pgdp
, start
);
1106 if(srmmu_pmd_none(*pmdp
)) {
1107 ptep
= (pte_t
*) __srmmu_get_nocache(PTE_SIZE
,
1110 early_pgtable_allocfail("pte");
1111 memset(ptep
, 0, PTE_SIZE
);
1112 srmmu_pmd_set(pmdp
, ptep
);
1114 if (start
> (0xffffffffUL
- PMD_SIZE
))
1116 start
= (start
+ PMD_SIZE
) & PMD_MASK
;
1121 * This is much cleaner than poking around physical address space
1122 * looking at the prom's page table directly which is what most
1123 * other OS's do. Yuck... this is much better.
1125 static void __init
srmmu_inherit_prom_mappings(unsigned long start
,
1131 int what
= 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1132 unsigned long prompte
;
1134 while(start
<= end
) {
1136 break; /* probably wrap around */
1137 if(start
== 0xfef00000)
1138 start
= KADB_DEBUGGER_BEGVM
;
1139 if(!(prompte
= srmmu_hwprobe(start
))) {
1144 /* A red snapper, see what it really is. */
1147 if(!(start
& ~(SRMMU_REAL_PMD_MASK
))) {
1148 if(srmmu_hwprobe((start
-PAGE_SIZE
) + SRMMU_REAL_PMD_SIZE
) == prompte
)
1152 if(!(start
& ~(SRMMU_PGDIR_MASK
))) {
1153 if(srmmu_hwprobe((start
-PAGE_SIZE
) + SRMMU_PGDIR_SIZE
) ==
1158 pgdp
= pgd_offset_k(start
);
1160 *(pgd_t
*)__nocache_fix(pgdp
) = __pgd(prompte
);
1161 start
+= SRMMU_PGDIR_SIZE
;
1164 if(srmmu_pgd_none(*(pgd_t
*)__nocache_fix(pgdp
))) {
1165 pmdp
= (pmd_t
*)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
1167 early_pgtable_allocfail("pmd");
1168 memset(__nocache_fix(pmdp
), 0, SRMMU_PMD_TABLE_SIZE
);
1169 srmmu_pgd_set(__nocache_fix(pgdp
), pmdp
);
1171 pmdp
= srmmu_pmd_offset(__nocache_fix(pgdp
), start
);
1172 if(srmmu_pmd_none(*(pmd_t
*)__nocache_fix(pmdp
))) {
1173 ptep
= (pte_t
*) __srmmu_get_nocache(PTE_SIZE
,
1176 early_pgtable_allocfail("pte");
1177 memset(__nocache_fix(ptep
), 0, PTE_SIZE
);
1178 srmmu_pmd_set(__nocache_fix(pmdp
), ptep
);
1182 * We bend the rule where all 16 PTPs in a pmd_t point
1183 * inside the same PTE page, and we leak a perfectly
1184 * good hardware PTE piece. Alternatives seem worse.
1186 unsigned int x
; /* Index of HW PMD in soft cluster */
1187 x
= (start
>> PMD_SHIFT
) & 15;
1188 *(unsigned long *)__nocache_fix(&pmdp
->pmdv
[x
]) = prompte
;
1189 start
+= SRMMU_REAL_PMD_SIZE
;
1192 ptep
= srmmu_pte_offset(__nocache_fix(pmdp
), start
);
1193 *(pte_t
*)__nocache_fix(ptep
) = __pte(prompte
);
1198 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1200 /* Create a third-level SRMMU 16MB page mapping. */
1201 static void __init
do_large_mapping(unsigned long vaddr
, unsigned long phys_base
)
1203 pgd_t
*pgdp
= pgd_offset_k(vaddr
);
1204 unsigned long big_pte
;
1206 big_pte
= KERNEL_PTE(phys_base
>> 4);
1207 *(pgd_t
*)__nocache_fix(pgdp
) = __pgd(big_pte
);
1210 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1211 static unsigned long __init
map_spbank(unsigned long vbase
, int sp_entry
)
1213 unsigned long pstart
= (sp_banks
[sp_entry
].base_addr
& SRMMU_PGDIR_MASK
);
1214 unsigned long vstart
= (vbase
& SRMMU_PGDIR_MASK
);
1215 unsigned long vend
= SRMMU_PGDIR_ALIGN(vbase
+ sp_banks
[sp_entry
].num_bytes
);
1216 /* Map "low" memory only */
1217 const unsigned long min_vaddr
= PAGE_OFFSET
;
1218 const unsigned long max_vaddr
= PAGE_OFFSET
+ SRMMU_MAXMEM
;
1220 if (vstart
< min_vaddr
|| vstart
>= max_vaddr
)
1223 if (vend
> max_vaddr
|| vend
< min_vaddr
)
1226 while(vstart
< vend
) {
1227 do_large_mapping(vstart
, pstart
);
1228 vstart
+= SRMMU_PGDIR_SIZE
; pstart
+= SRMMU_PGDIR_SIZE
;
1233 static inline void memprobe_error(char *msg
)
1236 prom_printf("Halting now...\n");
1240 static inline void map_kernel(void)
1244 if (phys_base
> 0) {
1245 do_large_mapping(PAGE_OFFSET
, phys_base
);
1248 for (i
= 0; sp_banks
[i
].num_bytes
!= 0; i
++) {
1249 map_spbank((unsigned long)__va(sp_banks
[i
].base_addr
), i
);
1252 BTFIXUPSET_SIMM13(user_ptrs_per_pgd
, PAGE_OFFSET
/ SRMMU_PGDIR_SIZE
);
1255 /* Paging initialization on the Sparc Reference MMU. */
1256 extern void sparc_context_init(int);
1258 void (*poke_srmmu
)(void) __cpuinitdata
= NULL
;
1260 extern unsigned long bootmem_init(unsigned long *pages_avail
);
1262 void __init
srmmu_paging_init(void)
1270 unsigned long pages_avail
;
1272 sparc_iomap
.start
= SUN4M_IOBASE_VADDR
; /* 16MB of IOSPACE on all sun4m's. */
1274 if (sparc_cpu_model
== sun4d
)
1275 num_contexts
= 65536; /* We know it is Viking */
1277 /* Find the number of contexts on the srmmu. */
1278 cpunode
= prom_getchild(prom_root_node
);
1280 while(cpunode
!= 0) {
1281 prom_getstring(cpunode
, "device_type", node_str
, sizeof(node_str
));
1282 if(!strcmp(node_str
, "cpu")) {
1283 num_contexts
= prom_getintdefault(cpunode
, "mmu-nctx", 0x8);
1286 cpunode
= prom_getsibling(cpunode
);
1291 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1296 last_valid_pfn
= bootmem_init(&pages_avail
);
1298 srmmu_nocache_calcsize();
1299 srmmu_nocache_init();
1300 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM
-PAGE_SIZE
));
1303 /* ctx table has to be physically aligned to its size */
1304 srmmu_context_table
= (ctxd_t
*)__srmmu_get_nocache(num_contexts
*sizeof(ctxd_t
), num_contexts
*sizeof(ctxd_t
));
1305 srmmu_ctx_table_phys
= (ctxd_t
*)__nocache_pa((unsigned long)srmmu_context_table
);
1307 for(i
= 0; i
< num_contexts
; i
++)
1308 srmmu_ctxd_set((ctxd_t
*)__nocache_fix(&srmmu_context_table
[i
]), srmmu_swapper_pg_dir
);
1311 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys
);
1313 /* Stop from hanging here... */
1314 local_flush_tlb_all();
1320 srmmu_allocate_ptable_skeleton(sparc_iomap
.start
, IOBASE_END
);
1321 srmmu_allocate_ptable_skeleton(DVMA_VADDR
, DVMA_END
);
1323 srmmu_allocate_ptable_skeleton(
1324 __fix_to_virt(__end_of_fixed_addresses
- 1), FIXADDR_TOP
);
1325 srmmu_allocate_ptable_skeleton(PKMAP_BASE
, PKMAP_END
);
1327 pgd
= pgd_offset_k(PKMAP_BASE
);
1328 pmd
= srmmu_pmd_offset(pgd
, PKMAP_BASE
);
1329 pte
= srmmu_pte_offset(pmd
, PKMAP_BASE
);
1330 pkmap_page_table
= pte
;
1335 sparc_context_init(num_contexts
);
1340 unsigned long zones_size
[MAX_NR_ZONES
];
1341 unsigned long zholes_size
[MAX_NR_ZONES
];
1342 unsigned long npages
;
1345 for (znum
= 0; znum
< MAX_NR_ZONES
; znum
++)
1346 zones_size
[znum
] = zholes_size
[znum
] = 0;
1348 npages
= max_low_pfn
- pfn_base
;
1350 zones_size
[ZONE_DMA
] = npages
;
1351 zholes_size
[ZONE_DMA
] = npages
- pages_avail
;
1353 npages
= highend_pfn
- max_low_pfn
;
1354 zones_size
[ZONE_HIGHMEM
] = npages
;
1355 zholes_size
[ZONE_HIGHMEM
] = npages
- calc_highpages();
1357 free_area_init_node(0, zones_size
, pfn_base
, zholes_size
);
1361 static void srmmu_mmu_info(struct seq_file
*m
)
1366 "nocache total\t: %ld\n"
1367 "nocache used\t: %d\n",
1371 srmmu_nocache_map
.used
<< SRMMU_NOCACHE_BITMAP_SHIFT
);
1374 static void srmmu_update_mmu_cache(struct vm_area_struct
* vma
, unsigned long address
, pte_t pte
)
1378 static void srmmu_destroy_context(struct mm_struct
*mm
)
1381 if(mm
->context
!= NO_CONTEXT
) {
1383 srmmu_ctxd_set(&srmmu_context_table
[mm
->context
], srmmu_swapper_pg_dir
);
1385 spin_lock(&srmmu_context_spinlock
);
1386 free_context(mm
->context
);
1387 spin_unlock(&srmmu_context_spinlock
);
1388 mm
->context
= NO_CONTEXT
;
1392 /* Init various srmmu chip types. */
1393 static void __init
srmmu_is_bad(void)
1395 prom_printf("Could not determine SRMMU chip type.\n");
1399 static void __init
init_vac_layout(void)
1406 unsigned long max_size
= 0;
1407 unsigned long min_line_size
= 0x10000000;
1410 nd
= prom_getchild(prom_root_node
);
1411 while((nd
= prom_getsibling(nd
)) != 0) {
1412 prom_getstring(nd
, "device_type", node_str
, sizeof(node_str
));
1413 if(!strcmp(node_str
, "cpu")) {
1414 vac_line_size
= prom_getint(nd
, "cache-line-size");
1415 if (vac_line_size
== -1) {
1416 prom_printf("can't determine cache-line-size, "
1420 cache_lines
= prom_getint(nd
, "cache-nlines");
1421 if (cache_lines
== -1) {
1422 prom_printf("can't determine cache-nlines, halting.\n");
1426 vac_cache_size
= cache_lines
* vac_line_size
;
1428 if(vac_cache_size
> max_size
)
1429 max_size
= vac_cache_size
;
1430 if(vac_line_size
< min_line_size
)
1431 min_line_size
= vac_line_size
;
1432 //FIXME: cpus not contiguous!!
1434 if (cpu
>= nr_cpu_ids
|| !cpu_online(cpu
))
1442 prom_printf("No CPU nodes found, halting.\n");
1446 vac_cache_size
= max_size
;
1447 vac_line_size
= min_line_size
;
1449 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1450 (int)vac_cache_size
, (int)vac_line_size
);
1453 static void __cpuinit
poke_hypersparc(void)
1455 volatile unsigned long clear
;
1456 unsigned long mreg
= srmmu_get_mmureg();
1458 hyper_flush_unconditional_combined();
1460 mreg
&= ~(HYPERSPARC_CWENABLE
);
1461 mreg
|= (HYPERSPARC_CENABLE
| HYPERSPARC_WBENABLE
);
1462 mreg
|= (HYPERSPARC_CMODE
);
1464 srmmu_set_mmureg(mreg
);
1466 #if 0 /* XXX I think this is bad news... -DaveM */
1467 hyper_clear_all_tags();
1470 put_ross_icr(HYPERSPARC_ICCR_FTD
| HYPERSPARC_ICCR_ICE
);
1471 hyper_flush_whole_icache();
1472 clear
= srmmu_get_faddr();
1473 clear
= srmmu_get_fstatus();
1476 static void __init
init_hypersparc(void)
1478 srmmu_name
= "ROSS HyperSparc";
1479 srmmu_modtype
= HyperSparc
;
1485 BTFIXUPSET_CALL(pte_clear
, srmmu_pte_clear
, BTFIXUPCALL_NORM
);
1486 BTFIXUPSET_CALL(pmd_clear
, srmmu_pmd_clear
, BTFIXUPCALL_NORM
);
1487 BTFIXUPSET_CALL(pgd_clear
, srmmu_pgd_clear
, BTFIXUPCALL_NORM
);
1488 BTFIXUPSET_CALL(flush_cache_all
, hypersparc_flush_cache_all
, BTFIXUPCALL_NORM
);
1489 BTFIXUPSET_CALL(flush_cache_mm
, hypersparc_flush_cache_mm
, BTFIXUPCALL_NORM
);
1490 BTFIXUPSET_CALL(flush_cache_range
, hypersparc_flush_cache_range
, BTFIXUPCALL_NORM
);
1491 BTFIXUPSET_CALL(flush_cache_page
, hypersparc_flush_cache_page
, BTFIXUPCALL_NORM
);
1493 BTFIXUPSET_CALL(flush_tlb_all
, hypersparc_flush_tlb_all
, BTFIXUPCALL_NORM
);
1494 BTFIXUPSET_CALL(flush_tlb_mm
, hypersparc_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1495 BTFIXUPSET_CALL(flush_tlb_range
, hypersparc_flush_tlb_range
, BTFIXUPCALL_NORM
);
1496 BTFIXUPSET_CALL(flush_tlb_page
, hypersparc_flush_tlb_page
, BTFIXUPCALL_NORM
);
1498 BTFIXUPSET_CALL(__flush_page_to_ram
, hypersparc_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1499 BTFIXUPSET_CALL(flush_sig_insns
, hypersparc_flush_sig_insns
, BTFIXUPCALL_NORM
);
1500 BTFIXUPSET_CALL(flush_page_for_dma
, hypersparc_flush_page_for_dma
, BTFIXUPCALL_NOP
);
1503 poke_srmmu
= poke_hypersparc
;
1505 hypersparc_setup_blockops();
1508 static void __cpuinit
poke_cypress(void)
1510 unsigned long mreg
= srmmu_get_mmureg();
1511 unsigned long faddr
, tagval
;
1512 volatile unsigned long cypress_sucks
;
1513 volatile unsigned long clear
;
1515 clear
= srmmu_get_faddr();
1516 clear
= srmmu_get_fstatus();
1518 if (!(mreg
& CYPRESS_CENABLE
)) {
1519 for(faddr
= 0x0; faddr
< 0x10000; faddr
+= 20) {
1520 __asm__
__volatile__("sta %%g0, [%0 + %1] %2\n\t"
1521 "sta %%g0, [%0] %2\n\t" : :
1522 "r" (faddr
), "r" (0x40000),
1523 "i" (ASI_M_DATAC_TAG
));
1526 for(faddr
= 0; faddr
< 0x10000; faddr
+= 0x20) {
1527 __asm__
__volatile__("lda [%1 + %2] %3, %0\n\t" :
1529 "r" (faddr
), "r" (0x40000),
1530 "i" (ASI_M_DATAC_TAG
));
1532 /* If modified and valid, kick it. */
1533 if((tagval
& 0x60) == 0x60)
1534 cypress_sucks
= *(unsigned long *)
1535 (0xf0020000 + faddr
);
1539 /* And one more, for our good neighbor, Mr. Broken Cypress. */
1540 clear
= srmmu_get_faddr();
1541 clear
= srmmu_get_fstatus();
1543 mreg
|= (CYPRESS_CENABLE
| CYPRESS_CMODE
);
1544 srmmu_set_mmureg(mreg
);
1547 static void __init
init_cypress_common(void)
1551 BTFIXUPSET_CALL(pte_clear
, srmmu_pte_clear
, BTFIXUPCALL_NORM
);
1552 BTFIXUPSET_CALL(pmd_clear
, srmmu_pmd_clear
, BTFIXUPCALL_NORM
);
1553 BTFIXUPSET_CALL(pgd_clear
, srmmu_pgd_clear
, BTFIXUPCALL_NORM
);
1554 BTFIXUPSET_CALL(flush_cache_all
, cypress_flush_cache_all
, BTFIXUPCALL_NORM
);
1555 BTFIXUPSET_CALL(flush_cache_mm
, cypress_flush_cache_mm
, BTFIXUPCALL_NORM
);
1556 BTFIXUPSET_CALL(flush_cache_range
, cypress_flush_cache_range
, BTFIXUPCALL_NORM
);
1557 BTFIXUPSET_CALL(flush_cache_page
, cypress_flush_cache_page
, BTFIXUPCALL_NORM
);
1559 BTFIXUPSET_CALL(flush_tlb_all
, cypress_flush_tlb_all
, BTFIXUPCALL_NORM
);
1560 BTFIXUPSET_CALL(flush_tlb_mm
, cypress_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1561 BTFIXUPSET_CALL(flush_tlb_page
, cypress_flush_tlb_page
, BTFIXUPCALL_NORM
);
1562 BTFIXUPSET_CALL(flush_tlb_range
, cypress_flush_tlb_range
, BTFIXUPCALL_NORM
);
1565 BTFIXUPSET_CALL(__flush_page_to_ram
, cypress_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1566 BTFIXUPSET_CALL(flush_sig_insns
, cypress_flush_sig_insns
, BTFIXUPCALL_NOP
);
1567 BTFIXUPSET_CALL(flush_page_for_dma
, cypress_flush_page_for_dma
, BTFIXUPCALL_NOP
);
1569 poke_srmmu
= poke_cypress
;
1572 static void __init
init_cypress_604(void)
1574 srmmu_name
= "ROSS Cypress-604(UP)";
1575 srmmu_modtype
= Cypress
;
1576 init_cypress_common();
1579 static void __init
init_cypress_605(unsigned long mrev
)
1581 srmmu_name
= "ROSS Cypress-605(MP)";
1583 srmmu_modtype
= Cypress_vE
;
1584 hwbug_bitmask
|= HWBUG_COPYBACK_BROKEN
;
1587 srmmu_modtype
= Cypress_vD
;
1588 hwbug_bitmask
|= HWBUG_ASIFLUSH_BROKEN
;
1590 srmmu_modtype
= Cypress
;
1593 init_cypress_common();
1596 static void __cpuinit
poke_swift(void)
1600 /* Clear any crap from the cache or else... */
1601 swift_flush_cache_all();
1603 /* Enable I & D caches */
1604 mreg
= srmmu_get_mmureg();
1605 mreg
|= (SWIFT_IE
| SWIFT_DE
);
1607 * The Swift branch folding logic is completely broken. At
1608 * trap time, if things are just right, if can mistakenly
1609 * think that a trap is coming from kernel mode when in fact
1610 * it is coming from user mode (it mis-executes the branch in
1611 * the trap code). So you see things like crashme completely
1612 * hosing your machine which is completely unacceptable. Turn
1613 * this shit off... nice job Fujitsu.
1615 mreg
&= ~(SWIFT_BF
);
1616 srmmu_set_mmureg(mreg
);
1619 #define SWIFT_MASKID_ADDR 0x10003018
1620 static void __init
init_swift(void)
1622 unsigned long swift_rev
;
1624 __asm__
__volatile__("lda [%1] %2, %0\n\t"
1625 "srl %0, 0x18, %0\n\t" :
1627 "r" (SWIFT_MASKID_ADDR
), "i" (ASI_M_BYPASS
));
1628 srmmu_name
= "Fujitsu Swift";
1634 srmmu_modtype
= Swift_lots_o_bugs
;
1635 hwbug_bitmask
|= (HWBUG_KERN_ACCBROKEN
| HWBUG_KERN_CBITBROKEN
);
1637 * Gee george, I wonder why Sun is so hush hush about
1638 * this hardware bug... really braindamage stuff going
1639 * on here. However I think we can find a way to avoid
1640 * all of the workaround overhead under Linux. Basically,
1641 * any page fault can cause kernel pages to become user
1642 * accessible (the mmu gets confused and clears some of
1643 * the ACC bits in kernel ptes). Aha, sounds pretty
1644 * horrible eh? But wait, after extensive testing it appears
1645 * that if you use pgd_t level large kernel pte's (like the
1646 * 4MB pages on the Pentium) the bug does not get tripped
1647 * at all. This avoids almost all of the major overhead.
1648 * Welcome to a world where your vendor tells you to,
1649 * "apply this kernel patch" instead of "sorry for the
1650 * broken hardware, send it back and we'll give you
1651 * properly functioning parts"
1656 srmmu_modtype
= Swift_bad_c
;
1657 hwbug_bitmask
|= HWBUG_KERN_CBITBROKEN
;
1659 * You see Sun allude to this hardware bug but never
1660 * admit things directly, they'll say things like,
1661 * "the Swift chip cache problems" or similar.
1665 srmmu_modtype
= Swift_ok
;
1669 BTFIXUPSET_CALL(flush_cache_all
, swift_flush_cache_all
, BTFIXUPCALL_NORM
);
1670 BTFIXUPSET_CALL(flush_cache_mm
, swift_flush_cache_mm
, BTFIXUPCALL_NORM
);
1671 BTFIXUPSET_CALL(flush_cache_page
, swift_flush_cache_page
, BTFIXUPCALL_NORM
);
1672 BTFIXUPSET_CALL(flush_cache_range
, swift_flush_cache_range
, BTFIXUPCALL_NORM
);
1675 BTFIXUPSET_CALL(flush_tlb_all
, swift_flush_tlb_all
, BTFIXUPCALL_NORM
);
1676 BTFIXUPSET_CALL(flush_tlb_mm
, swift_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1677 BTFIXUPSET_CALL(flush_tlb_page
, swift_flush_tlb_page
, BTFIXUPCALL_NORM
);
1678 BTFIXUPSET_CALL(flush_tlb_range
, swift_flush_tlb_range
, BTFIXUPCALL_NORM
);
1680 BTFIXUPSET_CALL(__flush_page_to_ram
, swift_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1681 BTFIXUPSET_CALL(flush_sig_insns
, swift_flush_sig_insns
, BTFIXUPCALL_NORM
);
1682 BTFIXUPSET_CALL(flush_page_for_dma
, swift_flush_page_for_dma
, BTFIXUPCALL_NORM
);
1684 BTFIXUPSET_CALL(update_mmu_cache
, swift_update_mmu_cache
, BTFIXUPCALL_NORM
);
1686 flush_page_for_dma_global
= 0;
1689 * Are you now convinced that the Swift is one of the
1690 * biggest VLSI abortions of all time? Bravo Fujitsu!
1691 * Fujitsu, the !#?!%$'d up processor people. I bet if
1692 * you examined the microcode of the Swift you'd find
1693 * XXX's all over the place.
1695 poke_srmmu
= poke_swift
;
1698 static void turbosparc_flush_cache_all(void)
1700 flush_user_windows();
1701 turbosparc_idflash_clear();
1704 static void turbosparc_flush_cache_mm(struct mm_struct
*mm
)
1707 flush_user_windows();
1708 turbosparc_idflash_clear();
1712 static void turbosparc_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
1714 FLUSH_BEGIN(vma
->vm_mm
)
1715 flush_user_windows();
1716 turbosparc_idflash_clear();
1720 static void turbosparc_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
)
1722 FLUSH_BEGIN(vma
->vm_mm
)
1723 flush_user_windows();
1724 if (vma
->vm_flags
& VM_EXEC
)
1725 turbosparc_flush_icache();
1726 turbosparc_flush_dcache();
1730 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1731 static void turbosparc_flush_page_to_ram(unsigned long page
)
1733 #ifdef TURBOSPARC_WRITEBACK
1734 volatile unsigned long clear
;
1736 if (srmmu_hwprobe(page
))
1737 turbosparc_flush_page_cache(page
);
1738 clear
= srmmu_get_fstatus();
1742 static void turbosparc_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
)
1746 static void turbosparc_flush_page_for_dma(unsigned long page
)
1748 turbosparc_flush_dcache();
1751 static void turbosparc_flush_tlb_all(void)
1753 srmmu_flush_whole_tlb();
1756 static void turbosparc_flush_tlb_mm(struct mm_struct
*mm
)
1759 srmmu_flush_whole_tlb();
1763 static void turbosparc_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
1765 FLUSH_BEGIN(vma
->vm_mm
)
1766 srmmu_flush_whole_tlb();
1770 static void turbosparc_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
1772 FLUSH_BEGIN(vma
->vm_mm
)
1773 srmmu_flush_whole_tlb();
1778 static void __cpuinit
poke_turbosparc(void)
1780 unsigned long mreg
= srmmu_get_mmureg();
1781 unsigned long ccreg
;
1783 /* Clear any crap from the cache or else... */
1784 turbosparc_flush_cache_all();
1785 mreg
&= ~(TURBOSPARC_ICENABLE
| TURBOSPARC_DCENABLE
); /* Temporarily disable I & D caches */
1786 mreg
&= ~(TURBOSPARC_PCENABLE
); /* Don't check parity */
1787 srmmu_set_mmureg(mreg
);
1789 ccreg
= turbosparc_get_ccreg();
1791 #ifdef TURBOSPARC_WRITEBACK
1792 ccreg
|= (TURBOSPARC_SNENABLE
); /* Do DVMA snooping in Dcache */
1793 ccreg
&= ~(TURBOSPARC_uS2
| TURBOSPARC_WTENABLE
);
1794 /* Write-back D-cache, emulate VLSI
1795 * abortion number three, not number one */
1797 /* For now let's play safe, optimize later */
1798 ccreg
|= (TURBOSPARC_SNENABLE
| TURBOSPARC_WTENABLE
);
1799 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1800 ccreg
&= ~(TURBOSPARC_uS2
);
1801 /* Emulate VLSI abortion number three, not number one */
1804 switch (ccreg
& 7) {
1805 case 0: /* No SE cache */
1806 case 7: /* Test mode */
1809 ccreg
|= (TURBOSPARC_SCENABLE
);
1811 turbosparc_set_ccreg (ccreg
);
1813 mreg
|= (TURBOSPARC_ICENABLE
| TURBOSPARC_DCENABLE
); /* I & D caches on */
1814 mreg
|= (TURBOSPARC_ICSNOOP
); /* Icache snooping on */
1815 srmmu_set_mmureg(mreg
);
1818 static void __init
init_turbosparc(void)
1820 srmmu_name
= "Fujitsu TurboSparc";
1821 srmmu_modtype
= TurboSparc
;
1823 BTFIXUPSET_CALL(flush_cache_all
, turbosparc_flush_cache_all
, BTFIXUPCALL_NORM
);
1824 BTFIXUPSET_CALL(flush_cache_mm
, turbosparc_flush_cache_mm
, BTFIXUPCALL_NORM
);
1825 BTFIXUPSET_CALL(flush_cache_page
, turbosparc_flush_cache_page
, BTFIXUPCALL_NORM
);
1826 BTFIXUPSET_CALL(flush_cache_range
, turbosparc_flush_cache_range
, BTFIXUPCALL_NORM
);
1828 BTFIXUPSET_CALL(flush_tlb_all
, turbosparc_flush_tlb_all
, BTFIXUPCALL_NORM
);
1829 BTFIXUPSET_CALL(flush_tlb_mm
, turbosparc_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1830 BTFIXUPSET_CALL(flush_tlb_page
, turbosparc_flush_tlb_page
, BTFIXUPCALL_NORM
);
1831 BTFIXUPSET_CALL(flush_tlb_range
, turbosparc_flush_tlb_range
, BTFIXUPCALL_NORM
);
1833 BTFIXUPSET_CALL(__flush_page_to_ram
, turbosparc_flush_page_to_ram
, BTFIXUPCALL_NORM
);
1835 BTFIXUPSET_CALL(flush_sig_insns
, turbosparc_flush_sig_insns
, BTFIXUPCALL_NOP
);
1836 BTFIXUPSET_CALL(flush_page_for_dma
, turbosparc_flush_page_for_dma
, BTFIXUPCALL_NORM
);
1838 poke_srmmu
= poke_turbosparc
;
1841 static void __cpuinit
poke_tsunami(void)
1843 unsigned long mreg
= srmmu_get_mmureg();
1845 tsunami_flush_icache();
1846 tsunami_flush_dcache();
1847 mreg
&= ~TSUNAMI_ITD
;
1848 mreg
|= (TSUNAMI_IENAB
| TSUNAMI_DENAB
);
1849 srmmu_set_mmureg(mreg
);
1852 static void __init
init_tsunami(void)
1855 * Tsunami's pretty sane, Sun and TI actually got it
1856 * somewhat right this time. Fujitsu should have
1857 * taken some lessons from them.
1860 srmmu_name
= "TI Tsunami";
1861 srmmu_modtype
= Tsunami
;
1863 BTFIXUPSET_CALL(flush_cache_all
, tsunami_flush_cache_all
, BTFIXUPCALL_NORM
);
1864 BTFIXUPSET_CALL(flush_cache_mm
, tsunami_flush_cache_mm
, BTFIXUPCALL_NORM
);
1865 BTFIXUPSET_CALL(flush_cache_page
, tsunami_flush_cache_page
, BTFIXUPCALL_NORM
);
1866 BTFIXUPSET_CALL(flush_cache_range
, tsunami_flush_cache_range
, BTFIXUPCALL_NORM
);
1869 BTFIXUPSET_CALL(flush_tlb_all
, tsunami_flush_tlb_all
, BTFIXUPCALL_NORM
);
1870 BTFIXUPSET_CALL(flush_tlb_mm
, tsunami_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1871 BTFIXUPSET_CALL(flush_tlb_page
, tsunami_flush_tlb_page
, BTFIXUPCALL_NORM
);
1872 BTFIXUPSET_CALL(flush_tlb_range
, tsunami_flush_tlb_range
, BTFIXUPCALL_NORM
);
1874 BTFIXUPSET_CALL(__flush_page_to_ram
, tsunami_flush_page_to_ram
, BTFIXUPCALL_NOP
);
1875 BTFIXUPSET_CALL(flush_sig_insns
, tsunami_flush_sig_insns
, BTFIXUPCALL_NORM
);
1876 BTFIXUPSET_CALL(flush_page_for_dma
, tsunami_flush_page_for_dma
, BTFIXUPCALL_NORM
);
1878 poke_srmmu
= poke_tsunami
;
1880 tsunami_setup_blockops();
1883 static void __cpuinit
poke_viking(void)
1885 unsigned long mreg
= srmmu_get_mmureg();
1886 static int smp_catch
;
1888 if(viking_mxcc_present
) {
1889 unsigned long mxcc_control
= mxcc_get_creg();
1891 mxcc_control
|= (MXCC_CTL_ECE
| MXCC_CTL_PRE
| MXCC_CTL_MCE
);
1892 mxcc_control
&= ~(MXCC_CTL_RRC
);
1893 mxcc_set_creg(mxcc_control
);
1896 * We don't need memory parity checks.
1897 * XXX This is a mess, have to dig out later. ecd.
1898 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1901 /* We do cache ptables on MXCC. */
1902 mreg
|= VIKING_TCENABLE
;
1904 unsigned long bpreg
;
1906 mreg
&= ~(VIKING_TCENABLE
);
1908 /* Must disable mixed-cmd mode here for other cpu's. */
1909 bpreg
= viking_get_bpreg();
1910 bpreg
&= ~(VIKING_ACTION_MIX
);
1911 viking_set_bpreg(bpreg
);
1913 /* Just in case PROM does something funny. */
1918 mreg
|= VIKING_SPENABLE
;
1919 mreg
|= (VIKING_ICENABLE
| VIKING_DCENABLE
);
1920 mreg
|= VIKING_SBENABLE
;
1921 mreg
&= ~(VIKING_ACENABLE
);
1922 srmmu_set_mmureg(mreg
);
1925 static void __init
init_viking(void)
1927 unsigned long mreg
= srmmu_get_mmureg();
1929 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1930 if(mreg
& VIKING_MMODE
) {
1931 srmmu_name
= "TI Viking";
1932 viking_mxcc_present
= 0;
1935 BTFIXUPSET_CALL(pte_clear
, srmmu_pte_clear
, BTFIXUPCALL_NORM
);
1936 BTFIXUPSET_CALL(pmd_clear
, srmmu_pmd_clear
, BTFIXUPCALL_NORM
);
1937 BTFIXUPSET_CALL(pgd_clear
, srmmu_pgd_clear
, BTFIXUPCALL_NORM
);
1940 * We need this to make sure old viking takes no hits
1941 * on it's cache for dma snoops to workaround the
1942 * "load from non-cacheable memory" interrupt bug.
1943 * This is only necessary because of the new way in
1944 * which we use the IOMMU.
1946 BTFIXUPSET_CALL(flush_page_for_dma
, viking_flush_page
, BTFIXUPCALL_NORM
);
1948 flush_page_for_dma_global
= 0;
1950 srmmu_name
= "TI Viking/MXCC";
1951 viking_mxcc_present
= 1;
1953 srmmu_cache_pagetables
= 1;
1955 /* MXCC vikings lack the DMA snooping bug. */
1956 BTFIXUPSET_CALL(flush_page_for_dma
, viking_flush_page_for_dma
, BTFIXUPCALL_NOP
);
1959 BTFIXUPSET_CALL(flush_cache_all
, viking_flush_cache_all
, BTFIXUPCALL_NORM
);
1960 BTFIXUPSET_CALL(flush_cache_mm
, viking_flush_cache_mm
, BTFIXUPCALL_NORM
);
1961 BTFIXUPSET_CALL(flush_cache_page
, viking_flush_cache_page
, BTFIXUPCALL_NORM
);
1962 BTFIXUPSET_CALL(flush_cache_range
, viking_flush_cache_range
, BTFIXUPCALL_NORM
);
1965 if (sparc_cpu_model
== sun4d
) {
1966 BTFIXUPSET_CALL(flush_tlb_all
, sun4dsmp_flush_tlb_all
, BTFIXUPCALL_NORM
);
1967 BTFIXUPSET_CALL(flush_tlb_mm
, sun4dsmp_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1968 BTFIXUPSET_CALL(flush_tlb_page
, sun4dsmp_flush_tlb_page
, BTFIXUPCALL_NORM
);
1969 BTFIXUPSET_CALL(flush_tlb_range
, sun4dsmp_flush_tlb_range
, BTFIXUPCALL_NORM
);
1973 BTFIXUPSET_CALL(flush_tlb_all
, viking_flush_tlb_all
, BTFIXUPCALL_NORM
);
1974 BTFIXUPSET_CALL(flush_tlb_mm
, viking_flush_tlb_mm
, BTFIXUPCALL_NORM
);
1975 BTFIXUPSET_CALL(flush_tlb_page
, viking_flush_tlb_page
, BTFIXUPCALL_NORM
);
1976 BTFIXUPSET_CALL(flush_tlb_range
, viking_flush_tlb_range
, BTFIXUPCALL_NORM
);
1979 BTFIXUPSET_CALL(__flush_page_to_ram
, viking_flush_page_to_ram
, BTFIXUPCALL_NOP
);
1980 BTFIXUPSET_CALL(flush_sig_insns
, viking_flush_sig_insns
, BTFIXUPCALL_NOP
);
1982 poke_srmmu
= poke_viking
;
1985 #ifdef CONFIG_SPARC_LEON
1987 void __init
poke_leonsparc(void)
1991 void __init
init_leon(void)
1994 srmmu_name
= "LEON";
1996 BTFIXUPSET_CALL(flush_cache_all
, leon_flush_cache_all
,
1998 BTFIXUPSET_CALL(flush_cache_mm
, leon_flush_cache_all
,
2000 BTFIXUPSET_CALL(flush_cache_page
, leon_flush_pcache_all
,
2002 BTFIXUPSET_CALL(flush_cache_range
, leon_flush_cache_all
,
2004 BTFIXUPSET_CALL(flush_page_for_dma
, leon_flush_dcache_all
,
2007 BTFIXUPSET_CALL(flush_tlb_all
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
2008 BTFIXUPSET_CALL(flush_tlb_mm
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
2009 BTFIXUPSET_CALL(flush_tlb_page
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
2010 BTFIXUPSET_CALL(flush_tlb_range
, leon_flush_tlb_all
, BTFIXUPCALL_NORM
);
2012 BTFIXUPSET_CALL(__flush_page_to_ram
, leon_flush_cache_all
,
2014 BTFIXUPSET_CALL(flush_sig_insns
, leon_flush_cache_all
, BTFIXUPCALL_NOP
);
2016 poke_srmmu
= poke_leonsparc
;
2018 srmmu_cache_pagetables
= 0;
2020 leon_flush_during_switch
= leon_flush_needed();
2024 /* Probe for the srmmu chip version. */
2025 static void __init
get_srmmu_type(void)
2027 unsigned long mreg
, psr
;
2028 unsigned long mod_typ
, mod_rev
, psr_typ
, psr_vers
;
2030 srmmu_modtype
= SRMMU_INVAL_MOD
;
2033 mreg
= srmmu_get_mmureg(); psr
= get_psr();
2034 mod_typ
= (mreg
& 0xf0000000) >> 28;
2035 mod_rev
= (mreg
& 0x0f000000) >> 24;
2036 psr_typ
= (psr
>> 28) & 0xf;
2037 psr_vers
= (psr
>> 24) & 0xf;
2039 /* First, check for sparc-leon. */
2040 if (sparc_cpu_model
== sparc_leon
) {
2045 /* Second, check for HyperSparc or Cypress. */
2049 /* UP or MP Hypersparc */
2054 /* Uniprocessor Cypress */
2060 /* _REALLY OLD_ Cypress MP chips... */
2064 /* MP Cypress mmu/cache-controller */
2065 init_cypress_605(mod_rev
);
2068 /* Some other Cypress revision, assume a 605. */
2069 init_cypress_605(mod_rev
);
2076 * Now Fujitsu TurboSparc. It might happen that it is
2077 * in Swift emulation mode, so we will check later...
2079 if (psr_typ
== 0 && psr_vers
== 5) {
2084 /* Next check for Fujitsu Swift. */
2085 if(psr_typ
== 0 && psr_vers
== 4) {
2089 /* Look if it is not a TurboSparc emulating Swift... */
2090 cpunode
= prom_getchild(prom_root_node
);
2091 while((cpunode
= prom_getsibling(cpunode
)) != 0) {
2092 prom_getstring(cpunode
, "device_type", node_str
, sizeof(node_str
));
2093 if(!strcmp(node_str
, "cpu")) {
2094 if (!prom_getintdefault(cpunode
, "psr-implementation", 1) &&
2095 prom_getintdefault(cpunode
, "psr-version", 1) == 5) {
2107 /* Now the Viking family of srmmu. */
2110 ((psr_vers
== 1) && (mod_typ
== 0) && (mod_rev
== 0)))) {
2115 /* Finally the Tsunami. */
2116 if(psr_typ
== 4 && psr_vers
== 1 && (mod_typ
|| mod_rev
)) {
2125 /* don't laugh, static pagetables */
2126 static void srmmu_check_pgt_cache(int low
, int high
)
2130 extern unsigned long spwin_mmu_patchme
, fwin_mmu_patchme
,
2131 tsetup_mmu_patchme
, rtrap_mmu_patchme
;
2133 extern unsigned long spwin_srmmu_stackchk
, srmmu_fwin_stackchk
,
2134 tsetup_srmmu_stackchk
, srmmu_rett_stackchk
;
2137 /* Local cross-calls. */
2138 static void smp_flush_page_for_dma(unsigned long page
)
2140 xc1((smpfunc_t
) BTFIXUP_CALL(local_flush_page_for_dma
), page
);
2141 local_flush_page_for_dma(page
);
2146 /* Load up routines and constants for sun4m and sun4d mmu */
2147 void __init
ld_mmu_srmmu(void)
2149 extern void ld_mmu_iommu(void);
2150 extern void ld_mmu_iounit(void);
2151 extern void ___xchg32_sun4md(void);
2153 BTFIXUPSET_SIMM13(pgdir_shift
, SRMMU_PGDIR_SHIFT
);
2154 BTFIXUPSET_SETHI(pgdir_size
, SRMMU_PGDIR_SIZE
);
2155 BTFIXUPSET_SETHI(pgdir_mask
, SRMMU_PGDIR_MASK
);
2157 BTFIXUPSET_SIMM13(ptrs_per_pmd
, SRMMU_PTRS_PER_PMD
);
2158 BTFIXUPSET_SIMM13(ptrs_per_pgd
, SRMMU_PTRS_PER_PGD
);
2160 BTFIXUPSET_INT(page_none
, pgprot_val(SRMMU_PAGE_NONE
));
2161 PAGE_SHARED
= pgprot_val(SRMMU_PAGE_SHARED
);
2162 BTFIXUPSET_INT(page_copy
, pgprot_val(SRMMU_PAGE_COPY
));
2163 BTFIXUPSET_INT(page_readonly
, pgprot_val(SRMMU_PAGE_RDONLY
));
2164 BTFIXUPSET_INT(page_kernel
, pgprot_val(SRMMU_PAGE_KERNEL
));
2165 page_kernel
= pgprot_val(SRMMU_PAGE_KERNEL
);
2169 BTFIXUPSET_CALL(___xchg32
, ___xchg32_sun4md
, BTFIXUPCALL_SWAPG1G2
);
2171 BTFIXUPSET_CALL(do_check_pgt_cache
, srmmu_check_pgt_cache
, BTFIXUPCALL_NOP
);
2173 BTFIXUPSET_CALL(set_pte
, srmmu_set_pte
, BTFIXUPCALL_SWAPO0O1
);
2174 BTFIXUPSET_CALL(switch_mm
, srmmu_switch_mm
, BTFIXUPCALL_NORM
);
2176 BTFIXUPSET_CALL(pte_pfn
, srmmu_pte_pfn
, BTFIXUPCALL_NORM
);
2177 BTFIXUPSET_CALL(pmd_page
, srmmu_pmd_page
, BTFIXUPCALL_NORM
);
2178 BTFIXUPSET_CALL(pgd_page_vaddr
, srmmu_pgd_page
, BTFIXUPCALL_NORM
);
2180 BTFIXUPSET_CALL(pte_present
, srmmu_pte_present
, BTFIXUPCALL_NORM
);
2181 BTFIXUPSET_CALL(pte_clear
, srmmu_pte_clear
, BTFIXUPCALL_SWAPO0G0
);
2183 BTFIXUPSET_CALL(pmd_bad
, srmmu_pmd_bad
, BTFIXUPCALL_NORM
);
2184 BTFIXUPSET_CALL(pmd_present
, srmmu_pmd_present
, BTFIXUPCALL_NORM
);
2185 BTFIXUPSET_CALL(pmd_clear
, srmmu_pmd_clear
, BTFIXUPCALL_SWAPO0G0
);
2187 BTFIXUPSET_CALL(pgd_none
, srmmu_pgd_none
, BTFIXUPCALL_NORM
);
2188 BTFIXUPSET_CALL(pgd_bad
, srmmu_pgd_bad
, BTFIXUPCALL_NORM
);
2189 BTFIXUPSET_CALL(pgd_present
, srmmu_pgd_present
, BTFIXUPCALL_NORM
);
2190 BTFIXUPSET_CALL(pgd_clear
, srmmu_pgd_clear
, BTFIXUPCALL_SWAPO0G0
);
2192 BTFIXUPSET_CALL(mk_pte
, srmmu_mk_pte
, BTFIXUPCALL_NORM
);
2193 BTFIXUPSET_CALL(mk_pte_phys
, srmmu_mk_pte_phys
, BTFIXUPCALL_NORM
);
2194 BTFIXUPSET_CALL(mk_pte_io
, srmmu_mk_pte_io
, BTFIXUPCALL_NORM
);
2195 BTFIXUPSET_CALL(pgd_set
, srmmu_pgd_set
, BTFIXUPCALL_NORM
);
2196 BTFIXUPSET_CALL(pmd_set
, srmmu_pmd_set
, BTFIXUPCALL_NORM
);
2197 BTFIXUPSET_CALL(pmd_populate
, srmmu_pmd_populate
, BTFIXUPCALL_NORM
);
2199 BTFIXUPSET_INT(pte_modify_mask
, SRMMU_CHG_MASK
);
2200 BTFIXUPSET_CALL(pmd_offset
, srmmu_pmd_offset
, BTFIXUPCALL_NORM
);
2201 BTFIXUPSET_CALL(pte_offset_kernel
, srmmu_pte_offset
, BTFIXUPCALL_NORM
);
2203 BTFIXUPSET_CALL(free_pte_fast
, srmmu_free_pte_fast
, BTFIXUPCALL_NORM
);
2204 BTFIXUPSET_CALL(pte_free
, srmmu_pte_free
, BTFIXUPCALL_NORM
);
2205 BTFIXUPSET_CALL(pte_alloc_one_kernel
, srmmu_pte_alloc_one_kernel
, BTFIXUPCALL_NORM
);
2206 BTFIXUPSET_CALL(pte_alloc_one
, srmmu_pte_alloc_one
, BTFIXUPCALL_NORM
);
2207 BTFIXUPSET_CALL(free_pmd_fast
, srmmu_pmd_free
, BTFIXUPCALL_NORM
);
2208 BTFIXUPSET_CALL(pmd_alloc_one
, srmmu_pmd_alloc_one
, BTFIXUPCALL_NORM
);
2209 BTFIXUPSET_CALL(free_pgd_fast
, srmmu_free_pgd_fast
, BTFIXUPCALL_NORM
);
2210 BTFIXUPSET_CALL(get_pgd_fast
, srmmu_get_pgd_fast
, BTFIXUPCALL_NORM
);
2212 BTFIXUPSET_HALF(pte_writei
, SRMMU_WRITE
);
2213 BTFIXUPSET_HALF(pte_dirtyi
, SRMMU_DIRTY
);
2214 BTFIXUPSET_HALF(pte_youngi
, SRMMU_REF
);
2215 BTFIXUPSET_HALF(pte_filei
, SRMMU_FILE
);
2216 BTFIXUPSET_HALF(pte_wrprotecti
, SRMMU_WRITE
);
2217 BTFIXUPSET_HALF(pte_mkcleani
, SRMMU_DIRTY
);
2218 BTFIXUPSET_HALF(pte_mkoldi
, SRMMU_REF
);
2219 BTFIXUPSET_CALL(pte_mkwrite
, srmmu_pte_mkwrite
, BTFIXUPCALL_ORINT(SRMMU_WRITE
));
2220 BTFIXUPSET_CALL(pte_mkdirty
, srmmu_pte_mkdirty
, BTFIXUPCALL_ORINT(SRMMU_DIRTY
));
2221 BTFIXUPSET_CALL(pte_mkyoung
, srmmu_pte_mkyoung
, BTFIXUPCALL_ORINT(SRMMU_REF
));
2222 BTFIXUPSET_CALL(update_mmu_cache
, srmmu_update_mmu_cache
, BTFIXUPCALL_NOP
);
2223 BTFIXUPSET_CALL(destroy_context
, srmmu_destroy_context
, BTFIXUPCALL_NORM
);
2225 BTFIXUPSET_CALL(sparc_mapiorange
, srmmu_mapiorange
, BTFIXUPCALL_NORM
);
2226 BTFIXUPSET_CALL(sparc_unmapiorange
, srmmu_unmapiorange
, BTFIXUPCALL_NORM
);
2228 BTFIXUPSET_CALL(__swp_type
, srmmu_swp_type
, BTFIXUPCALL_NORM
);
2229 BTFIXUPSET_CALL(__swp_offset
, srmmu_swp_offset
, BTFIXUPCALL_NORM
);
2230 BTFIXUPSET_CALL(__swp_entry
, srmmu_swp_entry
, BTFIXUPCALL_NORM
);
2232 BTFIXUPSET_CALL(mmu_info
, srmmu_mmu_info
, BTFIXUPCALL_NORM
);
2237 /* El switcheroo... */
2239 BTFIXUPCOPY_CALL(local_flush_cache_all
, flush_cache_all
);
2240 BTFIXUPCOPY_CALL(local_flush_cache_mm
, flush_cache_mm
);
2241 BTFIXUPCOPY_CALL(local_flush_cache_range
, flush_cache_range
);
2242 BTFIXUPCOPY_CALL(local_flush_cache_page
, flush_cache_page
);
2243 BTFIXUPCOPY_CALL(local_flush_tlb_all
, flush_tlb_all
);
2244 BTFIXUPCOPY_CALL(local_flush_tlb_mm
, flush_tlb_mm
);
2245 BTFIXUPCOPY_CALL(local_flush_tlb_range
, flush_tlb_range
);
2246 BTFIXUPCOPY_CALL(local_flush_tlb_page
, flush_tlb_page
);
2247 BTFIXUPCOPY_CALL(local_flush_page_to_ram
, __flush_page_to_ram
);
2248 BTFIXUPCOPY_CALL(local_flush_sig_insns
, flush_sig_insns
);
2249 BTFIXUPCOPY_CALL(local_flush_page_for_dma
, flush_page_for_dma
);
2251 BTFIXUPSET_CALL(flush_cache_all
, smp_flush_cache_all
, BTFIXUPCALL_NORM
);
2252 BTFIXUPSET_CALL(flush_cache_mm
, smp_flush_cache_mm
, BTFIXUPCALL_NORM
);
2253 BTFIXUPSET_CALL(flush_cache_range
, smp_flush_cache_range
, BTFIXUPCALL_NORM
);
2254 BTFIXUPSET_CALL(flush_cache_page
, smp_flush_cache_page
, BTFIXUPCALL_NORM
);
2255 if (sparc_cpu_model
!= sun4d
&&
2256 sparc_cpu_model
!= sparc_leon
) {
2257 BTFIXUPSET_CALL(flush_tlb_all
, smp_flush_tlb_all
, BTFIXUPCALL_NORM
);
2258 BTFIXUPSET_CALL(flush_tlb_mm
, smp_flush_tlb_mm
, BTFIXUPCALL_NORM
);
2259 BTFIXUPSET_CALL(flush_tlb_range
, smp_flush_tlb_range
, BTFIXUPCALL_NORM
);
2260 BTFIXUPSET_CALL(flush_tlb_page
, smp_flush_tlb_page
, BTFIXUPCALL_NORM
);
2262 BTFIXUPSET_CALL(__flush_page_to_ram
, smp_flush_page_to_ram
, BTFIXUPCALL_NORM
);
2263 BTFIXUPSET_CALL(flush_sig_insns
, smp_flush_sig_insns
, BTFIXUPCALL_NORM
);
2264 BTFIXUPSET_CALL(flush_page_for_dma
, smp_flush_page_for_dma
, BTFIXUPCALL_NORM
);
2266 if (poke_srmmu
== poke_viking
) {
2267 /* Avoid unnecessary cross calls. */
2268 BTFIXUPCOPY_CALL(flush_cache_all
, local_flush_cache_all
);
2269 BTFIXUPCOPY_CALL(flush_cache_mm
, local_flush_cache_mm
);
2270 BTFIXUPCOPY_CALL(flush_cache_range
, local_flush_cache_range
);
2271 BTFIXUPCOPY_CALL(flush_cache_page
, local_flush_cache_page
);
2272 BTFIXUPCOPY_CALL(__flush_page_to_ram
, local_flush_page_to_ram
);
2273 BTFIXUPCOPY_CALL(flush_sig_insns
, local_flush_sig_insns
);
2274 BTFIXUPCOPY_CALL(flush_page_for_dma
, local_flush_page_for_dma
);
2278 if (sparc_cpu_model
== sun4d
)
2283 if (sparc_cpu_model
== sun4d
)
2285 else if (sparc_cpu_model
== sparc_leon
)