arch/sparc64/kernel/chmc.c

   1 /* chmc.c: Driver for UltraSPARC-III memory controller.
   2  *
   3  * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/types.h>
   9 #include <linux/slab.h>
  10 #include <linux/list.h>
  11 #include <linux/string.h>
  12 #include <linux/sched.h>
  13 #include <linux/smp.h>
  14 #include <linux/errno.h>
  15 #include <linux/init.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <asm/spitfire.h>
  19 #include <asm/chmctrl.h>
  20 #include <asm/cpudata.h>
  21 #include <asm/oplib.h>
  22 #include <asm/prom.h>
  23 #include <asm/head.h>
  24 #include <asm/io.h>
  25
  26 #define DRV_MODULE_NAME         "chmc"
  27 #define PFX DRV_MODULE_NAME     ": "
  28 #define DRV_MODULE_VERSION      "0.2"
  29
  30 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  31 MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
  32 MODULE_LICENSE("GPL");
  33 MODULE_VERSION(DRV_MODULE_VERSION);
  34
  35 #define CHMCTRL_NDGRPS  2
  36 #define CHMCTRL_NDIMMS  4
  37
  38 #define CHMC_DIMMS_PER_MC       (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
  39
  40 /* OBP memory-layout property format. */
  41 struct chmc_obp_map {
  42         unsigned char   dimm_map[144];
  43         unsigned char   pin_map[576];
  44 };
  45
  46 #define DIMM_LABEL_SZ   8
  47
  48 struct chmc_obp_mem_layout {
  49         /* One max 8-byte string label per DIMM.  Usually
  50          * this matches the label on the motherboard where
  51          * that DIMM resides.
  52          */
  53         char                    dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];
  54
  55         /* If symmetric use map[0], else it is
  56          * asymmetric and map[1] should be used.
  57          */
  58         char                    symmetric;
  59
  60         struct chmc_obp_map     map[2];
  61 };
  62
  63 #define CHMCTRL_NBANKS  4
  64
  65 struct chmc_bank_info {
  66         struct chmc             *p;
  67         int                     bank_id;
  68
  69         u64                     raw_reg;
  70         int                     valid;
  71         int                     uk;
  72         int                     um;
  73         int                     lk;
  74         int                     lm;
  75         int                     interleave;
  76         unsigned long           base;
  77         unsigned long           size;
  78 };
  79
  80 struct chmc {
  81         struct list_head                list;
  82         int                             portid;
  83
  84         struct chmc_obp_mem_layout      layout_prop;
  85         int                             layout_size;
  86
  87         void __iomem                    *regs;
  88
  89         u64                             timing_control1;
  90         u64                             timing_control2;
  91         u64                             timing_control3;
  92         u64                             timing_control4;
  93         u64                             memaddr_control;
  94
  95         struct chmc_bank_info           logical_banks[CHMCTRL_NBANKS];
  96 };
  97
  98 static LIST_HEAD(mctrl_list);
  99
 100 /* Does BANK decode PHYS_ADDR? */
 101 static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
 102 {
 103         unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
 104         unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
 105
 106         /* Bank must be enabled to match. */
 107         if (bp->valid == 0)
 108                 return 0;
 109
 110         /* Would BANK match upper bits? */
 111         upper_bits ^= bp->um;           /* What bits are different? */
 112         upper_bits  = ~upper_bits;      /* Invert. */
 113         upper_bits |= bp->uk;           /* What bits don't matter for matching? */
 114         upper_bits  = ~upper_bits;      /* Invert. */
 115
 116         if (upper_bits)
 117                 return 0;
 118
 119         /* Would BANK match lower bits? */
 120         lower_bits ^= bp->lm;           /* What bits are different? */
 121         lower_bits  = ~lower_bits;      /* Invert. */
 122         lower_bits |= bp->lk;           /* What bits don't matter for matching? */
 123         lower_bits  = ~lower_bits;      /* Invert. */
 124
 125         if (lower_bits)
 126                 return 0;
 127
 128         /* I always knew you'd be the one. */
 129         return 1;
 130 }
 131
 132 /* Given PHYS_ADDR, search memory controller banks for a match. */
 133 static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
 134 {
 135         struct list_head *mctrl_head = &mctrl_list;
 136         struct list_head *mctrl_entry = mctrl_head->next;
 137
 138         for (;;) {
 139                 struct chmc *p = list_entry(mctrl_entry, struct chmc, list);
 140                 int bank_no;
 141
 142                 if (mctrl_entry == mctrl_head)
 143                         break;
 144                 mctrl_entry = mctrl_entry->next;
 145
 146                 for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
 147                         struct chmc_bank_info *bp;
 148
 149                         bp = &p->logical_banks[bank_no];
 150                         if (chmc_bank_match(bp, phys_addr))
 151                                 return bp;
 152                 }
 153         }
 154
 155         return NULL;
 156 }
 157
 158 /* This is the main purpose of this driver. */
 159 #define SYNDROME_MIN    -1
 160 #define SYNDROME_MAX    144
 161 int chmc_getunumber(int syndrome_code,
 162                     unsigned long phys_addr,
 163                     char *buf, int buflen)
 164 {
 165         struct chmc_bank_info *bp;
 166         struct chmc_obp_mem_layout *prop;
 167         int bank_in_controller, first_dimm;
 168
 169         bp = chmc_find_bank(phys_addr);
 170         if (bp == NULL ||
 171             syndrome_code < SYNDROME_MIN ||
 172             syndrome_code > SYNDROME_MAX) {
 173                 buf[0] = '?';
 174                 buf[1] = '?';
 175                 buf[2] = '?';
 176                 buf[3] = '\0';
 177                 return 0;
 178         }
 179
 180         prop = &bp->p->layout_prop;
 181         bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
 182         first_dimm  = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
 183         first_dimm *= CHMCTRL_NDIMMS;
 184
 185         if (syndrome_code != SYNDROME_MIN) {
 186                 struct chmc_obp_map *map;
 187                 int qword, where_in_line, where, map_index, map_offset;
 188                 unsigned int map_val;
 189
 190                 /* Yaay, single bit error so we can figure out
 191                  * the exact dimm.
 192                  */
 193                 if (prop->symmetric)
 194                         map = &prop->map[0];
 195                 else
 196                         map = &prop->map[1];
 197
 198                 /* Covert syndrome code into the way the bits are
 199                  * positioned on the bus.
 200                  */
 201                 if (syndrome_code < 144 - 16)
 202                         syndrome_code += 16;
 203                 else if (syndrome_code < 144)
 204                         syndrome_code -= (144 - 7);
 205                 else if (syndrome_code < (144 + 3))
 206                         syndrome_code -= (144 + 3 - 4);
 207                 else
 208                         syndrome_code -= 144 + 3;
 209
 210                 /* All this magic has to do with how a cache line
 211                  * comes over the wire on Safari.  A 64-bit line
 212                  * comes over in 4 quadword cycles, each of which
 213                  * transmit ECC/MTAG info as well as the actual
 214                  * data.  144 bits per quadword, 576 total.
 215                  */
 216 #define LINE_SIZE       64
 217 #define LINE_ADDR_MSK   (LINE_SIZE - 1)
 218 #define QW_PER_LINE     4
 219 #define QW_BYTES        (LINE_SIZE / QW_PER_LINE)
 220 #define QW_BITS         144
 221 #define LAST_BIT        (576 - 1)
 222
 223                 qword = (phys_addr & LINE_ADDR_MSK) / QW_BYTES;
 224                 where_in_line = ((3 - qword) * QW_BITS) + syndrome_code;
 225                 where = (LAST_BIT - where_in_line);
 226                 map_index = where >> 2;
 227                 map_offset = where & 0x3;
 228                 map_val = map->dimm_map[map_index];
 229                 map_val = ((map_val >> ((3 - map_offset) << 1)) & (2 - 1));
 230
 231                 sprintf(buf, "%s, pin %3d",
 232                         prop->dimm_labels[first_dimm + map_val],
 233                         map->pin_map[where_in_line]);
 234         } else {
 235                 int dimm;
 236
 237                 /* Multi-bit error, we just dump out all the
 238                  * dimm labels associated with this bank.
 239                  */
 240                 for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
 241                         sprintf(buf, "%s ",
 242                                 prop->dimm_labels[first_dimm + dimm]);
 243                         buf += strlen(buf);
 244                 }
 245         }
 246         return 0;
 247 }
 248
 249 /* Accessing the registers is slightly complicated.  If you want
 250  * to get at the memory controller which is on the same processor
 251  * the code is executing, you must use special ASI load/store else
 252  * you go through the global mapping.
 253  */
 254 static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
 255 {
 256         unsigned long ret, this_cpu;
 257
 258         preempt_disable();
 259
 260         this_cpu = real_hard_smp_processor_id();
 261
 262         if (p->portid == this_cpu) {
 263                 __asm__ __volatile__("ldxa      [%1] %2, %0"
 264                                      : "=r" (ret)
 265                                      : "r" (offset), "i" (ASI_MCU_CTRL_REG));
 266         } else {
 267                 __asm__ __volatile__("ldxa      [%1] %2, %0"
 268                                      : "=r" (ret)
 269                                      : "r" (p->regs + offset),
 270                                        "i" (ASI_PHYS_BYPASS_EC_E));
 271         }
 272
 273         preempt_enable();
 274
 275         return ret;
 276 }
 277
 278 #if 0 /* currently unused */
 279 static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
 280 {
 281         if (p->portid == smp_processor_id()) {
 282                 __asm__ __volatile__("stxa      %0, [%1] %2"
 283                                      : : "r" (val),
 284                                          "r" (offset), "i" (ASI_MCU_CTRL_REG));
 285         } else {
 286                 __asm__ __volatile__("ldxa      %0, [%1] %2"
 287                                      : : "r" (val),
 288                                          "r" (p->regs + offset),
 289                                          "i" (ASI_PHYS_BYPASS_EC_E));
 290         }
 291 }
 292 #endif
 293
 294 static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
 295 {
 296         struct chmc_bank_info *bp = &p->logical_banks[which_bank];
 297
 298         bp->p = p;
 299         bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
 300         bp->raw_reg = val;
 301         bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
 302         bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
 303         bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
 304         bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
 305         bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
 306
 307         bp->base  =  (bp->um);
 308         bp->base &= ~(bp->uk);
 309         bp->base <<= PA_UPPER_BITS_SHIFT;
 310
 311         switch(bp->lk) {
 312         case 0xf:
 313         default:
 314                 bp->interleave = 1;
 315                 break;
 316
 317         case 0xe:
 318                 bp->interleave = 2;
 319                 break;
 320
 321         case 0xc:
 322                 bp->interleave = 4;
 323                 break;
 324
 325         case 0x8:
 326                 bp->interleave = 8;
 327                 break;
 328
 329         case 0x0:
 330                 bp->interleave = 16;
 331                 break;
 332         };
 333
 334         /* UK[10] is reserved, and UK[11] is not set for the SDRAM
 335          * bank size definition.
 336          */
 337         bp->size = (((unsigned long)bp->uk &
 338                      ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
 339         bp->size /= bp->interleave;
 340 }
 341
 342 static void chmc_fetch_decode_regs(struct chmc *p)
 343 {
 344         if (p->layout_size == 0)
 345                 return;
 346
 347         chmc_interpret_one_decode_reg(p, 0,
 348                                       chmc_read_mcreg(p, CHMCTRL_DECODE1));
 349         chmc_interpret_one_decode_reg(p, 1,
 350                                       chmc_read_mcreg(p, CHMCTRL_DECODE2));
 351         chmc_interpret_one_decode_reg(p, 2,
 352                                       chmc_read_mcreg(p, CHMCTRL_DECODE3));
 353         chmc_interpret_one_decode_reg(p, 3,
 354                                       chmc_read_mcreg(p, CHMCTRL_DECODE4));
 355 }
 356
 357 static int __devinit chmc_probe(struct of_device *op,
 358                                 const struct of_device_id *match)
 359 {
 360         struct device_node *dp = op->node;
 361         unsigned long ver;
 362         const void *pval;
 363         int len, portid;
 364         struct chmc *p;
 365         int err;
 366
 367         err = -ENODEV;
 368         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 369         if ((ver >> 32UL) == __JALAPENO_ID ||
 370             (ver >> 32UL) == __SERRANO_ID)
 371                 goto out;
 372
 373         portid = of_getintprop_default(dp, "portid", -1);
 374         if (portid == -1)
 375                 goto out;
 376
 377         pval = of_get_property(dp, "memory-layout", &len);
 378         if (pval && len > sizeof(p->layout_prop)) {
 379                 printk(KERN_ERR PFX "Unexpected memory-layout property "
 380                        "size %d.\n", len);
 381                 goto out;
 382         }
 383
 384         err = -ENOMEM;
 385         p = kzalloc(sizeof(*p), GFP_KERNEL);
 386         if (!p) {
 387                 printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
 388                 goto out;
 389         }
 390
 391         p->portid = portid;
 392         p->layout_size = len;
 393         if (!pval)
 394                 p->layout_size = 0;
 395         else
 396                 memcpy(&p->layout_prop, pval, len);
 397
 398         p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
 399         if (!p->regs) {
 400                 printk(KERN_ERR PFX "Could not map registers.\n");
 401                 goto out_free;
 402         }
 403
 404         if (p->layout_size != 0UL) {
 405                 p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
 406                 p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
 407                 p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
 408                 p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
 409                 p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
 410         }
 411
 412         chmc_fetch_decode_regs(p);
 413
 414         list_add(&p->list, &mctrl_list);
 415
 416         /* Report the device. */
 417         printk(KERN_INFO PFX "UltraSPARC-III memory controller at %s [%s]\n",
 418                dp->full_name,
 419                (p->layout_size ? "ACTIVE" : "INACTIVE"));
 420
 421         dev_set_drvdata(&op->dev, p);
 422
 423         err = 0;
 424
 425 out:
 426         return err;
 427
 428 out_free:
 429         kfree(p);
 430         goto out;
 431 }
 432
 433 static int __devexit chmc_remove(struct of_device *op)
 434 {
 435         struct chmc *p = dev_get_drvdata(&op->dev);
 436
 437         if (p) {
 438                 list_del(&p->list);
 439                 of_iounmap(&op->resource[0], p->regs, 0x48);
 440                 kfree(p);
 441         }
 442         return 0;
 443 }
 444
 445 static struct of_device_id chmc_match[] = {
 446         {
 447                 .name = "memory-controller",
 448         },
 449         {},
 450 };
 451 MODULE_DEVICE_TABLE(of, chmc_match);
 452
 453 static struct of_platform_driver chmc_driver = {
 454         .name           = "chmc",
 455         .match_table    = chmc_match,
 456         .probe          = chmc_probe,
 457         .remove         = __devexit_p(chmc_remove),
 458 };
 459
 460 static inline bool chmc_platform(void)
 461 {
 462         if (tlb_type == cheetah || tlb_type == cheetah_plus)
 463                 return true;
 464         return false;
 465 }
 466
 467 static int __init chmc_init(void)
 468 {
 469         if (!chmc_platform())
 470                 return -ENODEV;
 471
 472         return of_register_driver(&chmc_driver, &of_bus_type);
 473 }
 474
 475 static void __exit chmc_cleanup(void)
 476 {
 477         if (chmc_platform())
 478                 of_unregister_driver(&chmc_driver);
 479 }
 480
 481 module_init(chmc_init);
 482 module_exit(chmc_cleanup);