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[SPARC64]: Move over to GENERIC_HARDIRQS.
[deliverable/linux.git] / arch / sparc64 / kernel / entry.S
1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10 #include <linux/config.h>
11 #include <linux/errno.h>
12
13 #include <asm/head.h>
14 #include <asm/asi.h>
15 #include <asm/smp.h>
16 #include <asm/ptrace.h>
17 #include <asm/page.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
24 #include <asm/sfafsr.h>
25 #include <asm/pil.h>
26
27 #define curptr g6
28
29 #define NR_SYSCALLS 300 /* Each OS is different... */
30
31 .text
32 .align 32
33
34 /* This is trivial with the new code... */
35 .globl do_fpdis
36 do_fpdis:
37 sethi %hi(TSTATE_PEF), %g4
38 rdpr %tstate, %g5
39 andcc %g5, %g4, %g0
40 be,pt %xcc, 1f
41 nop
42 rd %fprs, %g5
43 andcc %g5, FPRS_FEF, %g0
44 be,pt %xcc, 1f
45 nop
46
47 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
48 sethi %hi(109f), %g7
49 ba,pt %xcc, etrap
50 109: or %g7, %lo(109b), %g7
51 add %g0, %g0, %g0
52 ba,a,pt %xcc, rtrap_clr_l6
53
54 1: TRAP_LOAD_THREAD_REG(%g6, %g1)
55 ldub [%g6 + TI_FPSAVED], %g5
56 wr %g0, FPRS_FEF, %fprs
57 andcc %g5, FPRS_FEF, %g0
58 be,a,pt %icc, 1f
59 clr %g7
60 ldx [%g6 + TI_GSR], %g7
61 1: andcc %g5, FPRS_DL, %g0
62 bne,pn %icc, 2f
63 fzero %f0
64 andcc %g5, FPRS_DU, %g0
65 bne,pn %icc, 1f
66 fzero %f2
67 faddd %f0, %f2, %f4
68 fmuld %f0, %f2, %f6
69 faddd %f0, %f2, %f8
70 fmuld %f0, %f2, %f10
71 faddd %f0, %f2, %f12
72 fmuld %f0, %f2, %f14
73 faddd %f0, %f2, %f16
74 fmuld %f0, %f2, %f18
75 faddd %f0, %f2, %f20
76 fmuld %f0, %f2, %f22
77 faddd %f0, %f2, %f24
78 fmuld %f0, %f2, %f26
79 faddd %f0, %f2, %f28
80 fmuld %f0, %f2, %f30
81 faddd %f0, %f2, %f32
82 fmuld %f0, %f2, %f34
83 faddd %f0, %f2, %f36
84 fmuld %f0, %f2, %f38
85 faddd %f0, %f2, %f40
86 fmuld %f0, %f2, %f42
87 faddd %f0, %f2, %f44
88 fmuld %f0, %f2, %f46
89 faddd %f0, %f2, %f48
90 fmuld %f0, %f2, %f50
91 faddd %f0, %f2, %f52
92 fmuld %f0, %f2, %f54
93 faddd %f0, %f2, %f56
94 fmuld %f0, %f2, %f58
95 b,pt %xcc, fpdis_exit2
96 faddd %f0, %f2, %f60
97 1: mov SECONDARY_CONTEXT, %g3
98 add %g6, TI_FPREGS + 0x80, %g1
99 faddd %f0, %f2, %f4
100 fmuld %f0, %f2, %f6
101
102 661: ldxa [%g3] ASI_DMMU, %g5
103 .section .sun4v_1insn_patch, "ax"
104 .word 661b
105 ldxa [%g3] ASI_MMU, %g5
106 .previous
107
108 sethi %hi(sparc64_kern_sec_context), %g2
109 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
110
111 661: stxa %g2, [%g3] ASI_DMMU
112 .section .sun4v_1insn_patch, "ax"
113 .word 661b
114 stxa %g2, [%g3] ASI_MMU
115 .previous
116
117 membar #Sync
118 add %g6, TI_FPREGS + 0xc0, %g2
119 faddd %f0, %f2, %f8
120 fmuld %f0, %f2, %f10
121 membar #Sync
122 ldda [%g1] ASI_BLK_S, %f32
123 ldda [%g2] ASI_BLK_S, %f48
124 membar #Sync
125 faddd %f0, %f2, %f12
126 fmuld %f0, %f2, %f14
127 faddd %f0, %f2, %f16
128 fmuld %f0, %f2, %f18
129 faddd %f0, %f2, %f20
130 fmuld %f0, %f2, %f22
131 faddd %f0, %f2, %f24
132 fmuld %f0, %f2, %f26
133 faddd %f0, %f2, %f28
134 fmuld %f0, %f2, %f30
135 b,pt %xcc, fpdis_exit
136 nop
137 2: andcc %g5, FPRS_DU, %g0
138 bne,pt %icc, 3f
139 fzero %f32
140 mov SECONDARY_CONTEXT, %g3
141 fzero %f34
142
143 661: ldxa [%g3] ASI_DMMU, %g5
144 .section .sun4v_1insn_patch, "ax"
145 .word 661b
146 ldxa [%g3] ASI_MMU, %g5
147 .previous
148
149 add %g6, TI_FPREGS, %g1
150 sethi %hi(sparc64_kern_sec_context), %g2
151 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
152
153 661: stxa %g2, [%g3] ASI_DMMU
154 .section .sun4v_1insn_patch, "ax"
155 .word 661b
156 stxa %g2, [%g3] ASI_MMU
157 .previous
158
159 membar #Sync
160 add %g6, TI_FPREGS + 0x40, %g2
161 faddd %f32, %f34, %f36
162 fmuld %f32, %f34, %f38
163 membar #Sync
164 ldda [%g1] ASI_BLK_S, %f0
165 ldda [%g2] ASI_BLK_S, %f16
166 membar #Sync
167 faddd %f32, %f34, %f40
168 fmuld %f32, %f34, %f42
169 faddd %f32, %f34, %f44
170 fmuld %f32, %f34, %f46
171 faddd %f32, %f34, %f48
172 fmuld %f32, %f34, %f50
173 faddd %f32, %f34, %f52
174 fmuld %f32, %f34, %f54
175 faddd %f32, %f34, %f56
176 fmuld %f32, %f34, %f58
177 faddd %f32, %f34, %f60
178 fmuld %f32, %f34, %f62
179 ba,pt %xcc, fpdis_exit
180 nop
181 3: mov SECONDARY_CONTEXT, %g3
182 add %g6, TI_FPREGS, %g1
183
184 661: ldxa [%g3] ASI_DMMU, %g5
185 .section .sun4v_1insn_patch, "ax"
186 .word 661b
187 ldxa [%g3] ASI_MMU, %g5
188 .previous
189
190 sethi %hi(sparc64_kern_sec_context), %g2
191 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
192
193 661: stxa %g2, [%g3] ASI_DMMU
194 .section .sun4v_1insn_patch, "ax"
195 .word 661b
196 stxa %g2, [%g3] ASI_MMU
197 .previous
198
199 membar #Sync
200 mov 0x40, %g2
201 membar #Sync
202 ldda [%g1] ASI_BLK_S, %f0
203 ldda [%g1 + %g2] ASI_BLK_S, %f16
204 add %g1, 0x80, %g1
205 ldda [%g1] ASI_BLK_S, %f32
206 ldda [%g1 + %g2] ASI_BLK_S, %f48
207 membar #Sync
208 fpdis_exit:
209
210 661: stxa %g5, [%g3] ASI_DMMU
211 .section .sun4v_1insn_patch, "ax"
212 .word 661b
213 stxa %g5, [%g3] ASI_MMU
214 .previous
215
216 membar #Sync
217 fpdis_exit2:
218 wr %g7, 0, %gsr
219 ldx [%g6 + TI_XFSR], %fsr
220 rdpr %tstate, %g3
221 or %g3, %g4, %g3 ! anal...
222 wrpr %g3, %tstate
223 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
224 retry
225
226 .align 32
227 fp_other_bounce:
228 call do_fpother
229 add %sp, PTREGS_OFF, %o0
230 ba,pt %xcc, rtrap
231 clr %l6
232
233 .globl do_fpother_check_fitos
234 .align 32
235 do_fpother_check_fitos:
236 TRAP_LOAD_THREAD_REG(%g6, %g1)
237 sethi %hi(fp_other_bounce - 4), %g7
238 or %g7, %lo(fp_other_bounce - 4), %g7
239
240 /* NOTE: Need to preserve %g7 until we fully commit
241 * to the fitos fixup.
242 */
243 stx %fsr, [%g6 + TI_XFSR]
244 rdpr %tstate, %g3
245 andcc %g3, TSTATE_PRIV, %g0
246 bne,pn %xcc, do_fptrap_after_fsr
247 nop
248 ldx [%g6 + TI_XFSR], %g3
249 srlx %g3, 14, %g1
250 and %g1, 7, %g1
251 cmp %g1, 2 ! Unfinished FP-OP
252 bne,pn %xcc, do_fptrap_after_fsr
253 sethi %hi(1 << 23), %g1 ! Inexact
254 andcc %g3, %g1, %g0
255 bne,pn %xcc, do_fptrap_after_fsr
256 rdpr %tpc, %g1
257 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
258 #define FITOS_MASK 0xc1f83fe0
259 #define FITOS_COMPARE 0x81a01880
260 sethi %hi(FITOS_MASK), %g1
261 or %g1, %lo(FITOS_MASK), %g1
262 and %g3, %g1, %g1
263 sethi %hi(FITOS_COMPARE), %g2
264 or %g2, %lo(FITOS_COMPARE), %g2
265 cmp %g1, %g2
266 bne,pn %xcc, do_fptrap_after_fsr
267 nop
268 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
269 sethi %hi(fitos_table_1), %g1
270 and %g3, 0x1f, %g2
271 or %g1, %lo(fitos_table_1), %g1
272 sllx %g2, 2, %g2
273 jmpl %g1 + %g2, %g0
274 ba,pt %xcc, fitos_emul_continue
275
276 fitos_table_1:
277 fitod %f0, %f62
278 fitod %f1, %f62
279 fitod %f2, %f62
280 fitod %f3, %f62
281 fitod %f4, %f62
282 fitod %f5, %f62
283 fitod %f6, %f62
284 fitod %f7, %f62
285 fitod %f8, %f62
286 fitod %f9, %f62
287 fitod %f10, %f62
288 fitod %f11, %f62
289 fitod %f12, %f62
290 fitod %f13, %f62
291 fitod %f14, %f62
292 fitod %f15, %f62
293 fitod %f16, %f62
294 fitod %f17, %f62
295 fitod %f18, %f62
296 fitod %f19, %f62
297 fitod %f20, %f62
298 fitod %f21, %f62
299 fitod %f22, %f62
300 fitod %f23, %f62
301 fitod %f24, %f62
302 fitod %f25, %f62
303 fitod %f26, %f62
304 fitod %f27, %f62
305 fitod %f28, %f62
306 fitod %f29, %f62
307 fitod %f30, %f62
308 fitod %f31, %f62
309
310 fitos_emul_continue:
311 sethi %hi(fitos_table_2), %g1
312 srl %g3, 25, %g2
313 or %g1, %lo(fitos_table_2), %g1
314 and %g2, 0x1f, %g2
315 sllx %g2, 2, %g2
316 jmpl %g1 + %g2, %g0
317 ba,pt %xcc, fitos_emul_fini
318
319 fitos_table_2:
320 fdtos %f62, %f0
321 fdtos %f62, %f1
322 fdtos %f62, %f2
323 fdtos %f62, %f3
324 fdtos %f62, %f4
325 fdtos %f62, %f5
326 fdtos %f62, %f6
327 fdtos %f62, %f7
328 fdtos %f62, %f8
329 fdtos %f62, %f9
330 fdtos %f62, %f10
331 fdtos %f62, %f11
332 fdtos %f62, %f12
333 fdtos %f62, %f13
334 fdtos %f62, %f14
335 fdtos %f62, %f15
336 fdtos %f62, %f16
337 fdtos %f62, %f17
338 fdtos %f62, %f18
339 fdtos %f62, %f19
340 fdtos %f62, %f20
341 fdtos %f62, %f21
342 fdtos %f62, %f22
343 fdtos %f62, %f23
344 fdtos %f62, %f24
345 fdtos %f62, %f25
346 fdtos %f62, %f26
347 fdtos %f62, %f27
348 fdtos %f62, %f28
349 fdtos %f62, %f29
350 fdtos %f62, %f30
351 fdtos %f62, %f31
352
353 fitos_emul_fini:
354 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
355 done
356
357 .globl do_fptrap
358 .align 32
359 do_fptrap:
360 TRAP_LOAD_THREAD_REG(%g6, %g1)
361 stx %fsr, [%g6 + TI_XFSR]
362 do_fptrap_after_fsr:
363 ldub [%g6 + TI_FPSAVED], %g3
364 rd %fprs, %g1
365 or %g3, %g1, %g3
366 stb %g3, [%g6 + TI_FPSAVED]
367 rd %gsr, %g3
368 stx %g3, [%g6 + TI_GSR]
369 mov SECONDARY_CONTEXT, %g3
370
371 661: ldxa [%g3] ASI_DMMU, %g5
372 .section .sun4v_1insn_patch, "ax"
373 .word 661b
374 ldxa [%g3] ASI_MMU, %g5
375 .previous
376
377 sethi %hi(sparc64_kern_sec_context), %g2
378 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
379
380 661: stxa %g2, [%g3] ASI_DMMU
381 .section .sun4v_1insn_patch, "ax"
382 .word 661b
383 stxa %g2, [%g3] ASI_MMU
384 .previous
385
386 membar #Sync
387 add %g6, TI_FPREGS, %g2
388 andcc %g1, FPRS_DL, %g0
389 be,pn %icc, 4f
390 mov 0x40, %g3
391 stda %f0, [%g2] ASI_BLK_S
392 stda %f16, [%g2 + %g3] ASI_BLK_S
393 andcc %g1, FPRS_DU, %g0
394 be,pn %icc, 5f
395 4: add %g2, 128, %g2
396 stda %f32, [%g2] ASI_BLK_S
397 stda %f48, [%g2 + %g3] ASI_BLK_S
398 5: mov SECONDARY_CONTEXT, %g1
399 membar #Sync
400
401 661: stxa %g5, [%g1] ASI_DMMU
402 .section .sun4v_1insn_patch, "ax"
403 .word 661b
404 stxa %g5, [%g1] ASI_MMU
405 .previous
406
407 membar #Sync
408 ba,pt %xcc, etrap
409 wr %g0, 0, %fprs
410
411 /* The registers for cross calls will be:
412 *
413 * DATA 0: [low 32-bits] Address of function to call, jmp to this
414 * [high 32-bits] MMU Context Argument 0, place in %g5
415 * DATA 1: Address Argument 1, place in %g1
416 * DATA 2: Address Argument 2, place in %g7
417 *
418 * With this method we can do most of the cross-call tlb/cache
419 * flushing very quickly.
420 */
421 .text
422 .align 32
423 .globl do_ivec
424 do_ivec:
425 mov 0x40, %g3
426 ldxa [%g3 + %g0] ASI_INTR_R, %g3
427 sethi %hi(KERNBASE), %g4
428 cmp %g3, %g4
429 bgeu,pn %xcc, do_ivec_xcall
430 srlx %g3, 32, %g5
431 stxa %g0, [%g0] ASI_INTR_RECEIVE
432 membar #Sync
433
434 sethi %hi(ivector_table), %g2
435 sllx %g3, 3, %g3
436 or %g2, %lo(ivector_table), %g2
437 add %g2, %g3, %g3
438
439 TRAP_LOAD_IRQ_WORK(%g6, %g1)
440
441 lduw [%g6], %g5 /* g5 = irq_work(cpu) */
442 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
443 stw %g3, [%g6] /* irq_work(cpu) = bucket */
444 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
445 retry
446 do_ivec_xcall:
447 mov 0x50, %g1
448 ldxa [%g1 + %g0] ASI_INTR_R, %g1
449 srl %g3, 0, %g3
450
451 mov 0x60, %g7
452 ldxa [%g7 + %g0] ASI_INTR_R, %g7
453 stxa %g0, [%g0] ASI_INTR_RECEIVE
454 membar #Sync
455 ba,pt %xcc, 1f
456 nop
457
458 .align 32
459 1: jmpl %g3, %g0
460 nop
461
462 .globl getcc, setcc
463 getcc:
464 ldx [%o0 + PT_V9_TSTATE], %o1
465 srlx %o1, 32, %o1
466 and %o1, 0xf, %o1
467 retl
468 stx %o1, [%o0 + PT_V9_G1]
469 setcc:
470 ldx [%o0 + PT_V9_TSTATE], %o1
471 ldx [%o0 + PT_V9_G1], %o2
472 or %g0, %ulo(TSTATE_ICC), %o3
473 sllx %o3, 32, %o3
474 andn %o1, %o3, %o1
475 sllx %o2, 32, %o2
476 and %o2, %o3, %o2
477 or %o1, %o2, %o1
478 retl
479 stx %o1, [%o0 + PT_V9_TSTATE]
480
481 .globl utrap_trap
482 utrap_trap: /* %g3=handler,%g4=level */
483 TRAP_LOAD_THREAD_REG(%g6, %g1)
484 ldx [%g6 + TI_UTRAPS], %g1
485 brnz,pt %g1, invoke_utrap
486 nop
487
488 ba,pt %xcc, etrap
489 rd %pc, %g7
490 mov %l4, %o1
491 call bad_trap
492 add %sp, PTREGS_OFF, %o0
493 ba,pt %xcc, rtrap
494 clr %l6
495
496 invoke_utrap:
497 sllx %g3, 3, %g3
498 ldx [%g1 + %g3], %g1
499 save %sp, -128, %sp
500 rdpr %tstate, %l6
501 rdpr %cwp, %l7
502 andn %l6, TSTATE_CWP, %l6
503 wrpr %l6, %l7, %tstate
504 rdpr %tpc, %l6
505 rdpr %tnpc, %l7
506 wrpr %g1, 0, %tnpc
507 done
508
509 /* We need to carefully read the error status, ACK
510 * the errors, prevent recursive traps, and pass the
511 * information on to C code for logging.
512 *
513 * We pass the AFAR in as-is, and we encode the status
514 * information as described in asm-sparc64/sfafsr.h
515 */
516 .globl __spitfire_access_error
517 __spitfire_access_error:
518 /* Disable ESTATE error reporting so that we do not
519 * take recursive traps and RED state the processor.
520 */
521 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
522 membar #Sync
523
524 mov UDBE_UE, %g1
525 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
526
527 /* __spitfire_cee_trap branches here with AFSR in %g4 and
528 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
529 * ESTATE Error Enable register.
530 */
531 __spitfire_cee_trap_continue:
532 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
533
534 rdpr %tt, %g3
535 and %g3, 0x1ff, %g3 ! Paranoia
536 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
537 or %g4, %g3, %g4
538 rdpr %tl, %g3
539 cmp %g3, 1
540 mov 1, %g3
541 bleu %xcc, 1f
542 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
543
544 or %g4, %g3, %g4
545
546 /* Read in the UDB error register state, clearing the
547 * sticky error bits as-needed. We only clear them if
548 * the UE bit is set. Likewise, __spitfire_cee_trap
549 * below will only do so if the CE bit is set.
550 *
551 * NOTE: UltraSparc-I/II have high and low UDB error
552 * registers, corresponding to the two UDB units
553 * present on those chips. UltraSparc-IIi only
554 * has a single UDB, called "SDB" in the manual.
555 * For IIi the upper UDB register always reads
556 * as zero so for our purposes things will just
557 * work with the checks below.
558 */
559 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
560 and %g3, 0x3ff, %g7 ! Paranoia
561 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
562 or %g4, %g7, %g4
563 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
564 be,pn %xcc, 1f
565 nop
566 stxa %g3, [%g0] ASI_UDB_ERROR_W
567 membar #Sync
568
569 1: mov 0x18, %g3
570 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
571 and %g3, 0x3ff, %g7 ! Paranoia
572 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
573 or %g4, %g7, %g4
574 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
575 be,pn %xcc, 1f
576 nop
577 mov 0x18, %g7
578 stxa %g3, [%g7] ASI_UDB_ERROR_W
579 membar #Sync
580
581 1: /* Ok, now that we've latched the error state,
582 * clear the sticky bits in the AFSR.
583 */
584 stxa %g4, [%g0] ASI_AFSR
585 membar #Sync
586
587 rdpr %tl, %g2
588 cmp %g2, 1
589 rdpr %pil, %g2
590 bleu,pt %xcc, 1f
591 wrpr %g0, 15, %pil
592
593 ba,pt %xcc, etraptl1
594 rd %pc, %g7
595
596 ba,pt %xcc, 2f
597 nop
598
599 1: ba,pt %xcc, etrap_irq
600 rd %pc, %g7
601
602 2: mov %l4, %o1
603 mov %l5, %o2
604 call spitfire_access_error
605 add %sp, PTREGS_OFF, %o0
606 ba,pt %xcc, rtrap
607 clr %l6
608
609 /* This is the trap handler entry point for ECC correctable
610 * errors. They are corrected, but we listen for the trap
611 * so that the event can be logged.
612 *
613 * Disrupting errors are either:
614 * 1) single-bit ECC errors during UDB reads to system
615 * memory
616 * 2) data parity errors during write-back events
617 *
618 * As far as I can make out from the manual, the CEE trap
619 * is only for correctable errors during memory read
620 * accesses by the front-end of the processor.
621 *
622 * The code below is only for trap level 1 CEE events,
623 * as it is the only situation where we can safely record
624 * and log. For trap level >1 we just clear the CE bit
625 * in the AFSR and return.
626 *
627 * This is just like __spiftire_access_error above, but it
628 * specifically handles correctable errors. If an
629 * uncorrectable error is indicated in the AFSR we
630 * will branch directly above to __spitfire_access_error
631 * to handle it instead. Uncorrectable therefore takes
632 * priority over correctable, and the error logging
633 * C code will notice this case by inspecting the
634 * trap type.
635 */
636 .globl __spitfire_cee_trap
637 __spitfire_cee_trap:
638 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
639 mov 1, %g3
640 sllx %g3, SFAFSR_UE_SHIFT, %g3
641 andcc %g4, %g3, %g0 ! Check for UE
642 bne,pn %xcc, __spitfire_access_error
643 nop
644
645 /* Ok, in this case we only have a correctable error.
646 * Indicate we only wish to capture that state in register
647 * %g1, and we only disable CE error reporting unlike UE
648 * handling which disables all errors.
649 */
650 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
651 andn %g3, ESTATE_ERR_CE, %g3
652 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
653 membar #Sync
654
655 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
656 ba,pt %xcc, __spitfire_cee_trap_continue
657 mov UDBE_CE, %g1
658
659 .globl __spitfire_data_access_exception
660 .globl __spitfire_data_access_exception_tl1
661 __spitfire_data_access_exception_tl1:
662 rdpr %pstate, %g4
663 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
664 mov TLB_SFSR, %g3
665 mov DMMU_SFAR, %g5
666 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
667 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
668 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
669 membar #Sync
670 rdpr %tt, %g3
671 cmp %g3, 0x80 ! first win spill/fill trap
672 blu,pn %xcc, 1f
673 cmp %g3, 0xff ! last win spill/fill trap
674 bgu,pn %xcc, 1f
675 nop
676 ba,pt %xcc, winfix_dax
677 rdpr %tpc, %g3
678 1: sethi %hi(109f), %g7
679 ba,pt %xcc, etraptl1
680 109: or %g7, %lo(109b), %g7
681 mov %l4, %o1
682 mov %l5, %o2
683 call spitfire_data_access_exception_tl1
684 add %sp, PTREGS_OFF, %o0
685 ba,pt %xcc, rtrap
686 clr %l6
687
688 __spitfire_data_access_exception:
689 rdpr %pstate, %g4
690 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
691 mov TLB_SFSR, %g3
692 mov DMMU_SFAR, %g5
693 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
694 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
695 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
696 membar #Sync
697 sethi %hi(109f), %g7
698 ba,pt %xcc, etrap
699 109: or %g7, %lo(109b), %g7
700 mov %l4, %o1
701 mov %l5, %o2
702 call spitfire_data_access_exception
703 add %sp, PTREGS_OFF, %o0
704 ba,pt %xcc, rtrap
705 clr %l6
706
707 .globl __spitfire_insn_access_exception
708 .globl __spitfire_insn_access_exception_tl1
709 __spitfire_insn_access_exception_tl1:
710 rdpr %pstate, %g4
711 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
712 mov TLB_SFSR, %g3
713 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
714 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
715 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
716 membar #Sync
717 sethi %hi(109f), %g7
718 ba,pt %xcc, etraptl1
719 109: or %g7, %lo(109b), %g7
720 mov %l4, %o1
721 mov %l5, %o2
722 call spitfire_insn_access_exception_tl1
723 add %sp, PTREGS_OFF, %o0
724 ba,pt %xcc, rtrap
725 clr %l6
726
727 __spitfire_insn_access_exception:
728 rdpr %pstate, %g4
729 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
730 mov TLB_SFSR, %g3
731 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
732 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
733 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
734 membar #Sync
735 sethi %hi(109f), %g7
736 ba,pt %xcc, etrap
737 109: or %g7, %lo(109b), %g7
738 mov %l4, %o1
739 mov %l5, %o2
740 call spitfire_insn_access_exception
741 add %sp, PTREGS_OFF, %o0
742 ba,pt %xcc, rtrap
743 clr %l6
744
745 /* These get patched into the trap table at boot time
746 * once we know we have a cheetah processor.
747 */
748 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
749 cheetah_fecc_trap_vector:
750 membar #Sync
751 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
752 andn %g1, DCU_DC | DCU_IC, %g1
753 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
754 membar #Sync
755 sethi %hi(cheetah_fast_ecc), %g2
756 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
757 mov 0, %g1
758 cheetah_fecc_trap_vector_tl1:
759 membar #Sync
760 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
761 andn %g1, DCU_DC | DCU_IC, %g1
762 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
763 membar #Sync
764 sethi %hi(cheetah_fast_ecc), %g2
765 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
766 mov 1, %g1
767 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
768 cheetah_cee_trap_vector:
769 membar #Sync
770 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
771 andn %g1, DCU_IC, %g1
772 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
773 membar #Sync
774 sethi %hi(cheetah_cee), %g2
775 jmpl %g2 + %lo(cheetah_cee), %g0
776 mov 0, %g1
777 cheetah_cee_trap_vector_tl1:
778 membar #Sync
779 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
780 andn %g1, DCU_IC, %g1
781 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
782 membar #Sync
783 sethi %hi(cheetah_cee), %g2
784 jmpl %g2 + %lo(cheetah_cee), %g0
785 mov 1, %g1
786 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
787 cheetah_deferred_trap_vector:
788 membar #Sync
789 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
790 andn %g1, DCU_DC | DCU_IC, %g1;
791 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
792 membar #Sync;
793 sethi %hi(cheetah_deferred_trap), %g2
794 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
795 mov 0, %g1
796 cheetah_deferred_trap_vector_tl1:
797 membar #Sync;
798 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
799 andn %g1, DCU_DC | DCU_IC, %g1;
800 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
801 membar #Sync;
802 sethi %hi(cheetah_deferred_trap), %g2
803 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
804 mov 1, %g1
805
806 /* Cheetah+ specific traps. These are for the new I/D cache parity
807 * error traps. The first argument to cheetah_plus_parity_handler
808 * is encoded as follows:
809 *
810 * Bit0: 0=dcache,1=icache
811 * Bit1: 0=recoverable,1=unrecoverable
812 */
813 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
814 cheetah_plus_dcpe_trap_vector:
815 membar #Sync
816 sethi %hi(do_cheetah_plus_data_parity), %g7
817 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
818 nop
819 nop
820 nop
821 nop
822 nop
823
824 do_cheetah_plus_data_parity:
825 rdpr %pil, %g2
826 wrpr %g0, 15, %pil
827 ba,pt %xcc, etrap_irq
828 rd %pc, %g7
829 mov 0x0, %o0
830 call cheetah_plus_parity_error
831 add %sp, PTREGS_OFF, %o1
832 ba,a,pt %xcc, rtrap_irq
833
834 cheetah_plus_dcpe_trap_vector_tl1:
835 membar #Sync
836 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
837 sethi %hi(do_dcpe_tl1), %g3
838 jmpl %g3 + %lo(do_dcpe_tl1), %g0
839 nop
840 nop
841 nop
842 nop
843
844 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
845 cheetah_plus_icpe_trap_vector:
846 membar #Sync
847 sethi %hi(do_cheetah_plus_insn_parity), %g7
848 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
849 nop
850 nop
851 nop
852 nop
853 nop
854
855 do_cheetah_plus_insn_parity:
856 rdpr %pil, %g2
857 wrpr %g0, 15, %pil
858 ba,pt %xcc, etrap_irq
859 rd %pc, %g7
860 mov 0x1, %o0
861 call cheetah_plus_parity_error
862 add %sp, PTREGS_OFF, %o1
863 ba,a,pt %xcc, rtrap_irq
864
865 cheetah_plus_icpe_trap_vector_tl1:
866 membar #Sync
867 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
868 sethi %hi(do_icpe_tl1), %g3
869 jmpl %g3 + %lo(do_icpe_tl1), %g0
870 nop
871 nop
872 nop
873 nop
874
875 /* If we take one of these traps when tl >= 1, then we
876 * jump to interrupt globals. If some trap level above us
877 * was also using interrupt globals, we cannot recover.
878 * We may use all interrupt global registers except %g6.
879 */
880 .globl do_dcpe_tl1, do_icpe_tl1
881 do_dcpe_tl1:
882 rdpr %tl, %g1 ! Save original trap level
883 mov 1, %g2 ! Setup TSTATE checking loop
884 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
885 1: wrpr %g2, %tl ! Set trap level to check
886 rdpr %tstate, %g4 ! Read TSTATE for this level
887 andcc %g4, %g3, %g0 ! Interrupt globals in use?
888 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
889 wrpr %g1, %tl ! Restore original trap level
890 add %g2, 1, %g2 ! Next trap level
891 cmp %g2, %g1 ! Hit them all yet?
892 ble,pt %icc, 1b ! Not yet
893 nop
894 wrpr %g1, %tl ! Restore original trap level
895 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
896 sethi %hi(dcache_parity_tl1_occurred), %g2
897 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
898 add %g1, 1, %g1
899 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
900 /* Reset D-cache parity */
901 sethi %hi(1 << 16), %g1 ! D-cache size
902 mov (1 << 5), %g2 ! D-cache line size
903 sub %g1, %g2, %g1 ! Move down 1 cacheline
904 1: srl %g1, 14, %g3 ! Compute UTAG
905 membar #Sync
906 stxa %g3, [%g1] ASI_DCACHE_UTAG
907 membar #Sync
908 sub %g2, 8, %g3 ! 64-bit data word within line
909 2: membar #Sync
910 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
911 membar #Sync
912 subcc %g3, 8, %g3 ! Next 64-bit data word
913 bge,pt %icc, 2b
914 nop
915 subcc %g1, %g2, %g1 ! Next cacheline
916 bge,pt %icc, 1b
917 nop
918 ba,pt %xcc, dcpe_icpe_tl1_common
919 nop
920
921 do_dcpe_tl1_fatal:
922 sethi %hi(1f), %g7
923 ba,pt %xcc, etraptl1
924 1: or %g7, %lo(1b), %g7
925 mov 0x2, %o0
926 call cheetah_plus_parity_error
927 add %sp, PTREGS_OFF, %o1
928 ba,pt %xcc, rtrap
929 clr %l6
930
931 do_icpe_tl1:
932 rdpr %tl, %g1 ! Save original trap level
933 mov 1, %g2 ! Setup TSTATE checking loop
934 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
935 1: wrpr %g2, %tl ! Set trap level to check
936 rdpr %tstate, %g4 ! Read TSTATE for this level
937 andcc %g4, %g3, %g0 ! Interrupt globals in use?
938 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
939 wrpr %g1, %tl ! Restore original trap level
940 add %g2, 1, %g2 ! Next trap level
941 cmp %g2, %g1 ! Hit them all yet?
942 ble,pt %icc, 1b ! Not yet
943 nop
944 wrpr %g1, %tl ! Restore original trap level
945 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
946 sethi %hi(icache_parity_tl1_occurred), %g2
947 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
948 add %g1, 1, %g1
949 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
950 /* Flush I-cache */
951 sethi %hi(1 << 15), %g1 ! I-cache size
952 mov (1 << 5), %g2 ! I-cache line size
953 sub %g1, %g2, %g1
954 1: or %g1, (2 << 3), %g3
955 stxa %g0, [%g3] ASI_IC_TAG
956 membar #Sync
957 subcc %g1, %g2, %g1
958 bge,pt %icc, 1b
959 nop
960 ba,pt %xcc, dcpe_icpe_tl1_common
961 nop
962
963 do_icpe_tl1_fatal:
964 sethi %hi(1f), %g7
965 ba,pt %xcc, etraptl1
966 1: or %g7, %lo(1b), %g7
967 mov 0x3, %o0
968 call cheetah_plus_parity_error
969 add %sp, PTREGS_OFF, %o1
970 ba,pt %xcc, rtrap
971 clr %l6
972
973 dcpe_icpe_tl1_common:
974 /* Flush D-cache, re-enable D/I caches in DCU and finally
975 * retry the trapping instruction.
976 */
977 sethi %hi(1 << 16), %g1 ! D-cache size
978 mov (1 << 5), %g2 ! D-cache line size
979 sub %g1, %g2, %g1
980 1: stxa %g0, [%g1] ASI_DCACHE_TAG
981 membar #Sync
982 subcc %g1, %g2, %g1
983 bge,pt %icc, 1b
984 nop
985 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
986 or %g1, (DCU_DC | DCU_IC), %g1
987 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
988 membar #Sync
989 retry
990
991 /* Capture I/D/E-cache state into per-cpu error scoreboard.
992 *
993 * %g1: (TL>=0) ? 1 : 0
994 * %g2: scratch
995 * %g3: scratch
996 * %g4: AFSR
997 * %g5: AFAR
998 * %g6: unused, will have current thread ptr after etrap
999 * %g7: scratch
1000 */
1001 __cheetah_log_error:
1002 /* Put "TL1" software bit into AFSR. */
1003 and %g1, 0x1, %g1
1004 sllx %g1, 63, %g2
1005 or %g4, %g2, %g4
1006
1007 /* Get log entry pointer for this cpu at this trap level. */
1008 BRANCH_IF_JALAPENO(g2,g3,50f)
1009 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1010 srlx %g2, 17, %g2
1011 ba,pt %xcc, 60f
1012 and %g2, 0x3ff, %g2
1013
1014 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1015 srlx %g2, 17, %g2
1016 and %g2, 0x1f, %g2
1017
1018 60: sllx %g2, 9, %g2
1019 sethi %hi(cheetah_error_log), %g3
1020 ldx [%g3 + %lo(cheetah_error_log)], %g3
1021 brz,pn %g3, 80f
1022 nop
1023
1024 add %g3, %g2, %g3
1025 sllx %g1, 8, %g1
1026 add %g3, %g1, %g1
1027
1028 /* %g1 holds pointer to the top of the logging scoreboard */
1029 ldx [%g1 + 0x0], %g7
1030 cmp %g7, -1
1031 bne,pn %xcc, 80f
1032 nop
1033
1034 stx %g4, [%g1 + 0x0]
1035 stx %g5, [%g1 + 0x8]
1036 add %g1, 0x10, %g1
1037
1038 /* %g1 now points to D-cache logging area */
1039 set 0x3ff8, %g2 /* DC_addr mask */
1040 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1041 srlx %g5, 12, %g3
1042 or %g3, 1, %g3 /* PHYS tag + valid */
1043
1044 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
1045 cmp %g3, %g7 /* TAG match? */
1046 bne,pt %xcc, 13f
1047 nop
1048
1049 /* Yep, what we want, capture state. */
1050 stx %g2, [%g1 + 0x20]
1051 stx %g7, [%g1 + 0x28]
1052
1053 /* A membar Sync is required before and after utag access. */
1054 membar #Sync
1055 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1056 membar #Sync
1057 stx %g7, [%g1 + 0x30]
1058 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1059 stx %g7, [%g1 + 0x38]
1060 clr %g3
1061
1062 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1063 stx %g7, [%g1]
1064 add %g3, (1 << 5), %g3
1065 cmp %g3, (4 << 5)
1066 bl,pt %xcc, 12b
1067 add %g1, 0x8, %g1
1068
1069 ba,pt %xcc, 20f
1070 add %g1, 0x20, %g1
1071
1072 13: sethi %hi(1 << 14), %g7
1073 add %g2, %g7, %g2
1074 srlx %g2, 14, %g7
1075 cmp %g7, 4
1076 bl,pt %xcc, 10b
1077 nop
1078
1079 add %g1, 0x40, %g1
1080
1081 /* %g1 now points to I-cache logging area */
1082 20: set 0x1fe0, %g2 /* IC_addr mask */
1083 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1084 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1085 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1086 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1087
1088 21: ldxa [%g2] ASI_IC_TAG, %g7
1089 andn %g7, 0xff, %g7
1090 cmp %g3, %g7
1091 bne,pt %xcc, 23f
1092 nop
1093
1094 /* Yep, what we want, capture state. */
1095 stx %g2, [%g1 + 0x40]
1096 stx %g7, [%g1 + 0x48]
1097 add %g2, (1 << 3), %g2
1098 ldxa [%g2] ASI_IC_TAG, %g7
1099 add %g2, (1 << 3), %g2
1100 stx %g7, [%g1 + 0x50]
1101 ldxa [%g2] ASI_IC_TAG, %g7
1102 add %g2, (1 << 3), %g2
1103 stx %g7, [%g1 + 0x60]
1104 ldxa [%g2] ASI_IC_TAG, %g7
1105 stx %g7, [%g1 + 0x68]
1106 sub %g2, (3 << 3), %g2
1107 ldxa [%g2] ASI_IC_STAG, %g7
1108 stx %g7, [%g1 + 0x58]
1109 clr %g3
1110 srlx %g2, 2, %g2
1111
1112 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1113 stx %g7, [%g1]
1114 add %g3, (1 << 3), %g3
1115 cmp %g3, (8 << 3)
1116 bl,pt %xcc, 22b
1117 add %g1, 0x8, %g1
1118
1119 ba,pt %xcc, 30f
1120 add %g1, 0x30, %g1
1121
1122 23: sethi %hi(1 << 14), %g7
1123 add %g2, %g7, %g2
1124 srlx %g2, 14, %g7
1125 cmp %g7, 4
1126 bl,pt %xcc, 21b
1127 nop
1128
1129 add %g1, 0x70, %g1
1130
1131 /* %g1 now points to E-cache logging area */
1132 30: andn %g5, (32 - 1), %g2
1133 stx %g2, [%g1 + 0x20]
1134 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1135 stx %g7, [%g1 + 0x28]
1136 ldxa [%g2] ASI_EC_R, %g0
1137 clr %g3
1138
1139 31: ldxa [%g3] ASI_EC_DATA, %g7
1140 stx %g7, [%g1 + %g3]
1141 add %g3, 0x8, %g3
1142 cmp %g3, 0x20
1143
1144 bl,pt %xcc, 31b
1145 nop
1146 80:
1147 rdpr %tt, %g2
1148 cmp %g2, 0x70
1149 be c_fast_ecc
1150 cmp %g2, 0x63
1151 be c_cee
1152 nop
1153 ba,pt %xcc, c_deferred
1154
1155 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1156 * in the trap table. That code has done a memory barrier
1157 * and has disabled both the I-cache and D-cache in the DCU
1158 * control register. The I-cache is disabled so that we may
1159 * capture the corrupted cache line, and the D-cache is disabled
1160 * because corrupt data may have been placed there and we don't
1161 * want to reference it.
1162 *
1163 * %g1 is one if this trap occurred at %tl >= 1.
1164 *
1165 * Next, we turn off error reporting so that we don't recurse.
1166 */
1167 .globl cheetah_fast_ecc
1168 cheetah_fast_ecc:
1169 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1170 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1171 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1172 membar #Sync
1173
1174 /* Fetch and clear AFSR/AFAR */
1175 ldxa [%g0] ASI_AFSR, %g4
1176 ldxa [%g0] ASI_AFAR, %g5
1177 stxa %g4, [%g0] ASI_AFSR
1178 membar #Sync
1179
1180 ba,pt %xcc, __cheetah_log_error
1181 nop
1182
1183 c_fast_ecc:
1184 rdpr %pil, %g2
1185 wrpr %g0, 15, %pil
1186 ba,pt %xcc, etrap_irq
1187 rd %pc, %g7
1188 mov %l4, %o1
1189 mov %l5, %o2
1190 call cheetah_fecc_handler
1191 add %sp, PTREGS_OFF, %o0
1192 ba,a,pt %xcc, rtrap_irq
1193
1194 /* Our caller has disabled I-cache and performed membar Sync. */
1195 .globl cheetah_cee
1196 cheetah_cee:
1197 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1198 andn %g2, ESTATE_ERROR_CEEN, %g2
1199 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1200 membar #Sync
1201
1202 /* Fetch and clear AFSR/AFAR */
1203 ldxa [%g0] ASI_AFSR, %g4
1204 ldxa [%g0] ASI_AFAR, %g5
1205 stxa %g4, [%g0] ASI_AFSR
1206 membar #Sync
1207
1208 ba,pt %xcc, __cheetah_log_error
1209 nop
1210
1211 c_cee:
1212 rdpr %pil, %g2
1213 wrpr %g0, 15, %pil
1214 ba,pt %xcc, etrap_irq
1215 rd %pc, %g7
1216 mov %l4, %o1
1217 mov %l5, %o2
1218 call cheetah_cee_handler
1219 add %sp, PTREGS_OFF, %o0
1220 ba,a,pt %xcc, rtrap_irq
1221
1222 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1223 .globl cheetah_deferred_trap
1224 cheetah_deferred_trap:
1225 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1226 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1227 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1228 membar #Sync
1229
1230 /* Fetch and clear AFSR/AFAR */
1231 ldxa [%g0] ASI_AFSR, %g4
1232 ldxa [%g0] ASI_AFAR, %g5
1233 stxa %g4, [%g0] ASI_AFSR
1234 membar #Sync
1235
1236 ba,pt %xcc, __cheetah_log_error
1237 nop
1238
1239 c_deferred:
1240 rdpr %pil, %g2
1241 wrpr %g0, 15, %pil
1242 ba,pt %xcc, etrap_irq
1243 rd %pc, %g7
1244 mov %l4, %o1
1245 mov %l5, %o2
1246 call cheetah_deferred_handler
1247 add %sp, PTREGS_OFF, %o0
1248 ba,a,pt %xcc, rtrap_irq
1249
1250 .globl __do_privact
1251 __do_privact:
1252 mov TLB_SFSR, %g3
1253 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1254 membar #Sync
1255 sethi %hi(109f), %g7
1256 ba,pt %xcc, etrap
1257 109: or %g7, %lo(109b), %g7
1258 call do_privact
1259 add %sp, PTREGS_OFF, %o0
1260 ba,pt %xcc, rtrap
1261 clr %l6
1262
1263 .globl do_mna
1264 do_mna:
1265 rdpr %tl, %g3
1266 cmp %g3, 1
1267
1268 /* Setup %g4/%g5 now as they are used in the
1269 * winfixup code.
1270 */
1271 mov TLB_SFSR, %g3
1272 mov DMMU_SFAR, %g4
1273 ldxa [%g4] ASI_DMMU, %g4
1274 ldxa [%g3] ASI_DMMU, %g5
1275 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1276 membar #Sync
1277 bgu,pn %icc, winfix_mna
1278 rdpr %tpc, %g3
1279
1280 1: sethi %hi(109f), %g7
1281 ba,pt %xcc, etrap
1282 109: or %g7, %lo(109b), %g7
1283 mov %l4, %o1
1284 mov %l5, %o2
1285 call mem_address_unaligned
1286 add %sp, PTREGS_OFF, %o0
1287 ba,pt %xcc, rtrap
1288 clr %l6
1289
1290 .globl do_lddfmna
1291 do_lddfmna:
1292 sethi %hi(109f), %g7
1293 mov TLB_SFSR, %g4
1294 ldxa [%g4] ASI_DMMU, %g5
1295 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1296 membar #Sync
1297 mov DMMU_SFAR, %g4
1298 ldxa [%g4] ASI_DMMU, %g4
1299 ba,pt %xcc, etrap
1300 109: or %g7, %lo(109b), %g7
1301 mov %l4, %o1
1302 mov %l5, %o2
1303 call handle_lddfmna
1304 add %sp, PTREGS_OFF, %o0
1305 ba,pt %xcc, rtrap
1306 clr %l6
1307
1308 .globl do_stdfmna
1309 do_stdfmna:
1310 sethi %hi(109f), %g7
1311 mov TLB_SFSR, %g4
1312 ldxa [%g4] ASI_DMMU, %g5
1313 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1314 membar #Sync
1315 mov DMMU_SFAR, %g4
1316 ldxa [%g4] ASI_DMMU, %g4
1317 ba,pt %xcc, etrap
1318 109: or %g7, %lo(109b), %g7
1319 mov %l4, %o1
1320 mov %l5, %o2
1321 call handle_stdfmna
1322 add %sp, PTREGS_OFF, %o0
1323 ba,pt %xcc, rtrap
1324 clr %l6
1325
1326 .globl breakpoint_trap
1327 breakpoint_trap:
1328 call sparc_breakpoint
1329 add %sp, PTREGS_OFF, %o0
1330 ba,pt %xcc, rtrap
1331 nop
1332
1333 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1334 defined(CONFIG_SOLARIS_EMUL_MODULE)
1335 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1336 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1337 * This is complete brain damage.
1338 */
1339 .globl sunos_indir
1340 sunos_indir:
1341 srl %o0, 0, %o0
1342 mov %o7, %l4
1343 cmp %o0, NR_SYSCALLS
1344 blu,a,pt %icc, 1f
1345 sll %o0, 0x2, %o0
1346 sethi %hi(sunos_nosys), %l6
1347 b,pt %xcc, 2f
1348 or %l6, %lo(sunos_nosys), %l6
1349 1: sethi %hi(sunos_sys_table), %l7
1350 or %l7, %lo(sunos_sys_table), %l7
1351 lduw [%l7 + %o0], %l6
1352 2: mov %o1, %o0
1353 mov %o2, %o1
1354 mov %o3, %o2
1355 mov %o4, %o3
1356 mov %o5, %o4
1357 call %l6
1358 mov %l4, %o7
1359
1360 .globl sunos_getpid
1361 sunos_getpid:
1362 call sys_getppid
1363 nop
1364 call sys_getpid
1365 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1366 b,pt %xcc, ret_sys_call
1367 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1368
1369 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1370 .globl sunos_getuid
1371 sunos_getuid:
1372 call sys32_geteuid16
1373 nop
1374 call sys32_getuid16
1375 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1376 b,pt %xcc, ret_sys_call
1377 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1378
1379 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1380 .globl sunos_getgid
1381 sunos_getgid:
1382 call sys32_getegid16
1383 nop
1384 call sys32_getgid16
1385 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1386 b,pt %xcc, ret_sys_call
1387 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1388 #endif
1389
1390 /* SunOS's execv() call only specifies the argv argument, the
1391 * environment settings are the same as the calling processes.
1392 */
1393 .globl sunos_execv
1394 sys_execve:
1395 sethi %hi(sparc_execve), %g1
1396 ba,pt %xcc, execve_merge
1397 or %g1, %lo(sparc_execve), %g1
1398 #ifdef CONFIG_COMPAT
1399 .globl sys_execve
1400 sunos_execv:
1401 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1402 .globl sys32_execve
1403 sys32_execve:
1404 sethi %hi(sparc32_execve), %g1
1405 or %g1, %lo(sparc32_execve), %g1
1406 #endif
1407 execve_merge:
1408 flushw
1409 jmpl %g1, %g0
1410 add %sp, PTREGS_OFF, %o0
1411
1412 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1413 .globl sys_rt_sigreturn
1414 .globl sys_ptrace
1415 .globl sys_sigaltstack
1416 .align 32
1417 sys_pipe: ba,pt %xcc, sparc_pipe
1418 add %sp, PTREGS_OFF, %o0
1419 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1420 add %sp, PTREGS_OFF, %o0
1421 sys_memory_ordering:
1422 ba,pt %xcc, sparc_memory_ordering
1423 add %sp, PTREGS_OFF, %o1
1424 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1425 add %i6, STACK_BIAS, %o2
1426 #ifdef CONFIG_COMPAT
1427 .globl sys32_sigstack
1428 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1429 mov %i6, %o2
1430 .globl sys32_sigaltstack
1431 sys32_sigaltstack:
1432 ba,pt %xcc, do_sys32_sigaltstack
1433 mov %i6, %o2
1434 #endif
1435 .align 32
1436 #ifdef CONFIG_COMPAT
1437 .globl sys32_sigreturn
1438 sys32_sigreturn:
1439 add %sp, PTREGS_OFF, %o0
1440 call do_sigreturn32
1441 add %o7, 1f-.-4, %o7
1442 nop
1443 #endif
1444 sys_rt_sigreturn:
1445 add %sp, PTREGS_OFF, %o0
1446 call do_rt_sigreturn
1447 add %o7, 1f-.-4, %o7
1448 nop
1449 #ifdef CONFIG_COMPAT
1450 .globl sys32_rt_sigreturn
1451 sys32_rt_sigreturn:
1452 add %sp, PTREGS_OFF, %o0
1453 call do_rt_sigreturn32
1454 add %o7, 1f-.-4, %o7
1455 nop
1456 #endif
1457 sys_ptrace: add %sp, PTREGS_OFF, %o0
1458 call do_ptrace
1459 add %o7, 1f-.-4, %o7
1460 nop
1461 .align 32
1462 1: ldx [%curptr + TI_FLAGS], %l5
1463 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1464 be,pt %icc, rtrap
1465 clr %l6
1466 add %sp, PTREGS_OFF, %o0
1467 call syscall_trace
1468 mov 1, %o1
1469
1470 ba,pt %xcc, rtrap
1471 clr %l6
1472
1473 /* This is how fork() was meant to be done, 8 instruction entry.
1474 *
1475 * I questioned the following code briefly, let me clear things
1476 * up so you must not reason on it like I did.
1477 *
1478 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1479 * need it here because the only piece of window state we copy to
1480 * the child is the CWP register. Even if the parent sleeps,
1481 * we are safe because we stuck it into pt_regs of the parent
1482 * so it will not change.
1483 *
1484 * XXX This raises the question, whether we can do the same on
1485 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1486 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1487 * XXX fork_kwim in UREG_G1 (global registers are considered
1488 * XXX volatile across a system call in the sparc ABI I think
1489 * XXX if it isn't we can use regs->y instead, anyone who depends
1490 * XXX upon the Y register being preserved across a fork deserves
1491 * XXX to lose).
1492 *
1493 * In fact we should take advantage of that fact for other things
1494 * during system calls...
1495 */
1496 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1497 .globl ret_from_syscall
1498 .align 32
1499 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1500 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1501 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1502 ba,pt %xcc, sys_clone
1503 sys_fork: clr %o1
1504 mov SIGCHLD, %o0
1505 sys_clone: flushw
1506 movrz %o1, %fp, %o1
1507 mov 0, %o3
1508 ba,pt %xcc, sparc_do_fork
1509 add %sp, PTREGS_OFF, %o2
1510 ret_from_syscall:
1511 /* Clear current_thread_info()->new_child, and
1512 * check performance counter stuff too.
1513 */
1514 stb %g0, [%g6 + TI_NEW_CHILD]
1515 ldx [%g6 + TI_FLAGS], %l0
1516 call schedule_tail
1517 mov %g7, %o0
1518 andcc %l0, _TIF_PERFCTR, %g0
1519 be,pt %icc, 1f
1520 nop
1521 ldx [%g6 + TI_PCR], %o7
1522 wr %g0, %o7, %pcr
1523
1524 /* Blackbird errata workaround. See commentary in
1525 * smp.c:smp_percpu_timer_interrupt() for more
1526 * information.
1527 */
1528 ba,pt %xcc, 99f
1529 nop
1530 .align 64
1531 99: wr %g0, %g0, %pic
1532 rd %pic, %g0
1533
1534 1: b,pt %xcc, ret_sys_call
1535 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1536 sparc_exit: rdpr %pstate, %g2
1537 wrpr %g2, PSTATE_IE, %pstate
1538 rdpr %otherwin, %g1
1539 rdpr %cansave, %g3
1540 add %g3, %g1, %g3
1541 wrpr %g3, 0x0, %cansave
1542 wrpr %g0, 0x0, %otherwin
1543 wrpr %g2, 0x0, %pstate
1544 ba,pt %xcc, sys_exit
1545 stb %g0, [%g6 + TI_WSAVED]
1546
1547 linux_sparc_ni_syscall:
1548 sethi %hi(sys_ni_syscall), %l7
1549 b,pt %xcc, 4f
1550 or %l7, %lo(sys_ni_syscall), %l7
1551
1552 linux_syscall_trace32:
1553 add %sp, PTREGS_OFF, %o0
1554 call syscall_trace
1555 clr %o1
1556 srl %i0, 0, %o0
1557 srl %i4, 0, %o4
1558 srl %i1, 0, %o1
1559 srl %i2, 0, %o2
1560 b,pt %xcc, 2f
1561 srl %i3, 0, %o3
1562
1563 linux_syscall_trace:
1564 add %sp, PTREGS_OFF, %o0
1565 call syscall_trace
1566 clr %o1
1567 mov %i0, %o0
1568 mov %i1, %o1
1569 mov %i2, %o2
1570 mov %i3, %o3
1571 b,pt %xcc, 2f
1572 mov %i4, %o4
1573
1574
1575 /* Linux 32-bit and SunOS system calls enter here... */
1576 .align 32
1577 .globl linux_sparc_syscall32
1578 linux_sparc_syscall32:
1579 /* Direct access to user regs, much faster. */
1580 cmp %g1, NR_SYSCALLS ! IEU1 Group
1581 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1582 srl %i0, 0, %o0 ! IEU0
1583 sll %g1, 2, %l4 ! IEU0 Group
1584 srl %i4, 0, %o4 ! IEU1
1585 lduw [%l7 + %l4], %l7 ! Load
1586 srl %i1, 0, %o1 ! IEU0 Group
1587 ldx [%curptr + TI_FLAGS], %l0 ! Load
1588
1589 srl %i5, 0, %o5 ! IEU1
1590 srl %i2, 0, %o2 ! IEU0 Group
1591 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1592 bne,pn %icc, linux_syscall_trace32 ! CTI
1593 mov %i0, %l5 ! IEU1
1594 call %l7 ! CTI Group brk forced
1595 srl %i3, 0, %o3 ! IEU0
1596 ba,a,pt %xcc, 3f
1597
1598 /* Linux native and SunOS system calls enter here... */
1599 .align 32
1600 .globl linux_sparc_syscall, ret_sys_call
1601 linux_sparc_syscall:
1602 /* Direct access to user regs, much faster. */
1603 cmp %g1, NR_SYSCALLS ! IEU1 Group
1604 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1605 mov %i0, %o0 ! IEU0
1606 sll %g1, 2, %l4 ! IEU0 Group
1607 mov %i1, %o1 ! IEU1
1608 lduw [%l7 + %l4], %l7 ! Load
1609 4: mov %i2, %o2 ! IEU0 Group
1610 ldx [%curptr + TI_FLAGS], %l0 ! Load
1611
1612 mov %i3, %o3 ! IEU1
1613 mov %i4, %o4 ! IEU0 Group
1614 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1615 bne,pn %icc, linux_syscall_trace ! CTI Group
1616 mov %i0, %l5 ! IEU0
1617 2: call %l7 ! CTI Group brk forced
1618 mov %i5, %o5 ! IEU0
1619 nop
1620
1621 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1622 ret_sys_call:
1623 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1624 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1625 sra %o0, 0, %o0
1626 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1627 sllx %g2, 32, %g2
1628
1629 /* Check if force_successful_syscall_return()
1630 * was invoked.
1631 */
1632 ldub [%curptr + TI_SYS_NOERROR], %l2
1633 brnz,a,pn %l2, 80f
1634 stb %g0, [%curptr + TI_SYS_NOERROR]
1635
1636 cmp %o0, -ERESTART_RESTARTBLOCK
1637 bgeu,pn %xcc, 1f
1638 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1639 80:
1640 /* System call success, clear Carry condition code. */
1641 andn %g3, %g2, %g3
1642 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1643 bne,pn %icc, linux_syscall_trace2
1644 add %l1, 0x4, %l2 ! npc = npc+4
1645 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1646 ba,pt %xcc, rtrap_clr_l6
1647 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1648
1649 1:
1650 /* System call failure, set Carry condition code.
1651 * Also, get abs(errno) to return to the process.
1652 */
1653 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1654 sub %g0, %o0, %o0
1655 or %g3, %g2, %g3
1656 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1657 mov 1, %l6
1658 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1659 bne,pn %icc, linux_syscall_trace2
1660 add %l1, 0x4, %l2 ! npc = npc+4
1661 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1662
1663 b,pt %xcc, rtrap
1664 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1665 linux_syscall_trace2:
1666 add %sp, PTREGS_OFF, %o0
1667 call syscall_trace
1668 mov 1, %o1
1669 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1670 ba,pt %xcc, rtrap
1671 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1672
1673 .align 32
1674 .globl __flushw_user
1675 __flushw_user:
1676 rdpr %otherwin, %g1
1677 brz,pn %g1, 2f
1678 clr %g2
1679 1: save %sp, -128, %sp
1680 rdpr %otherwin, %g1
1681 brnz,pt %g1, 1b
1682 add %g2, 1, %g2
1683 1: sub %g2, 1, %g2
1684 brnz,pt %g2, 1b
1685 restore %g0, %g0, %g0
1686 2: retl
1687 nop
1688
1689 #ifdef CONFIG_SMP
1690 .globl hard_smp_processor_id
1691 hard_smp_processor_id:
1692 #endif
1693 .globl real_hard_smp_processor_id
1694 real_hard_smp_processor_id:
1695 __GET_CPUID(%o0)
1696 retl
1697 nop
1698
1699 /* %o0: devhandle
1700 * %o1: devino
1701 *
1702 * returns %o0: sysino
1703 */
1704 .globl sun4v_devino_to_sysino
1705 sun4v_devino_to_sysino:
1706 mov HV_FAST_INTR_DEVINO2SYSINO, %o5
1707 ta HV_FAST_TRAP
1708 retl
1709 mov %o1, %o0
1710
1711 /* %o0: sysino
1712 *
1713 * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1714 */
1715 .globl sun4v_intr_getenabled
1716 sun4v_intr_getenabled:
1717 mov HV_FAST_INTR_GETENABLED, %o5
1718 ta HV_FAST_TRAP
1719 retl
1720 mov %o1, %o0
1721
1722 /* %o0: sysino
1723 * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1724 */
1725 .globl sun4v_intr_setenabled
1726 sun4v_intr_setenabled:
1727 mov HV_FAST_INTR_SETENABLED, %o5
1728 ta HV_FAST_TRAP
1729 retl
1730 nop
1731
1732 /* %o0: sysino
1733 *
1734 * returns %o0: intr_state (HV_INTR_STATE_*)
1735 */
1736 .globl sun4v_intr_getstate
1737 sun4v_intr_getstate:
1738 mov HV_FAST_INTR_GETSTATE, %o5
1739 ta HV_FAST_TRAP
1740 retl
1741 mov %o1, %o0
1742
1743 /* %o0: sysino
1744 * %o1: intr_state (HV_INTR_STATE_*)
1745 */
1746 .globl sun4v_intr_setstate
1747 sun4v_intr_setstate:
1748 mov HV_FAST_INTR_SETSTATE, %o5
1749 ta HV_FAST_TRAP
1750 retl
1751 nop
1752
1753 /* %o0: sysino
1754 *
1755 * returns %o0: cpuid
1756 */
1757 .globl sun4v_intr_gettarget
1758 sun4v_intr_gettarget:
1759 mov HV_FAST_INTR_GETTARGET, %o5
1760 ta HV_FAST_TRAP
1761 retl
1762 mov %o1, %o0
1763
1764 /* %o0: sysino
1765 * %o1: cpuid
1766 */
1767 .globl sun4v_intr_settarget
1768 sun4v_intr_settarget:
1769 mov HV_FAST_INTR_SETTARGET, %o5
1770 ta HV_FAST_TRAP
1771 retl
1772 nop
1773
1774 /* %o0: type
1775 * %o1: queue paddr
1776 * %o2: num queue entries
1777 *
1778 * returns %o0: status
1779 */
1780 .globl sun4v_cpu_qconf
1781 sun4v_cpu_qconf:
1782 mov HV_FAST_CPU_QCONF, %o5
1783 ta HV_FAST_TRAP
1784 retl
1785 nop
1786
1787 /* returns %o0: status
1788 */
1789 .globl sun4v_cpu_yield
1790 sun4v_cpu_yield:
1791 mov HV_FAST_CPU_YIELD, %o5
1792 ta HV_FAST_TRAP
1793 retl
1794 nop
1795
1796 /* %o0: num cpus in cpu list
1797 * %o1: cpu list paddr
1798 * %o2: mondo block paddr
1799 *
1800 * returns %o0: status
1801 */
1802 .globl sun4v_cpu_mondo_send
1803 sun4v_cpu_mondo_send:
1804 mov HV_FAST_CPU_MONDO_SEND, %o5
1805 ta HV_FAST_TRAP
1806 retl
1807 nop
1808
1809 /* %o0: CPU ID
1810 *
1811 * returns %o0: -status if status non-zero, else
1812 * %o0: cpu state as HV_CPU_STATE_*
1813 */
1814 .globl sun4v_cpu_state
1815 sun4v_cpu_state:
1816 mov HV_FAST_CPU_STATE, %o5
1817 ta HV_FAST_TRAP
1818 brnz,pn %o0, 1f
1819 sub %g0, %o0, %o0
1820 mov %o1, %o0
1821 1: retl
1822 nop
Linux kernel - Deliverables
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