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Merge branch 'release' of master.kernel.org:/pub/scm/linux/kernel/git/aegl/linux-2.6
[deliverable/linux.git] / arch / sparc64 / kernel / entry.S
1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10 #include <linux/config.h>
11 #include <linux/errno.h>
12
13 #include <asm/head.h>
14 #include <asm/asi.h>
15 #include <asm/smp.h>
16 #include <asm/ptrace.h>
17 #include <asm/page.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
24 #include <asm/sfafsr.h>
25
26 #define curptr g6
27
28 #define NR_SYSCALLS 284 /* Each OS is different... */
29
30 .text
31 .align 32
32
33 /* This is trivial with the new code... */
34 .globl do_fpdis
35 do_fpdis:
36 sethi %hi(TSTATE_PEF), %g4 ! IEU0
37 rdpr %tstate, %g5
38 andcc %g5, %g4, %g0
39 be,pt %xcc, 1f
40 nop
41 rd %fprs, %g5
42 andcc %g5, FPRS_FEF, %g0
43 be,pt %xcc, 1f
44 nop
45
46 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
47 sethi %hi(109f), %g7
48 ba,pt %xcc, etrap
49 109: or %g7, %lo(109b), %g7
50 add %g0, %g0, %g0
51 ba,a,pt %xcc, rtrap_clr_l6
52
53 1: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
54 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
55 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
56 be,a,pt %icc, 1f ! CTI
57 clr %g7 ! IEU0
58 ldx [%g6 + TI_GSR], %g7 ! Load Group
59 1: andcc %g5, FPRS_DL, %g0 ! IEU1
60 bne,pn %icc, 2f ! CTI
61 fzero %f0 ! FPA
62 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
63 bne,pn %icc, 1f ! CTI
64 fzero %f2 ! FPA
65 faddd %f0, %f2, %f4
66 fmuld %f0, %f2, %f6
67 faddd %f0, %f2, %f8
68 fmuld %f0, %f2, %f10
69 faddd %f0, %f2, %f12
70 fmuld %f0, %f2, %f14
71 faddd %f0, %f2, %f16
72 fmuld %f0, %f2, %f18
73 faddd %f0, %f2, %f20
74 fmuld %f0, %f2, %f22
75 faddd %f0, %f2, %f24
76 fmuld %f0, %f2, %f26
77 faddd %f0, %f2, %f28
78 fmuld %f0, %f2, %f30
79 faddd %f0, %f2, %f32
80 fmuld %f0, %f2, %f34
81 faddd %f0, %f2, %f36
82 fmuld %f0, %f2, %f38
83 faddd %f0, %f2, %f40
84 fmuld %f0, %f2, %f42
85 faddd %f0, %f2, %f44
86 fmuld %f0, %f2, %f46
87 faddd %f0, %f2, %f48
88 fmuld %f0, %f2, %f50
89 faddd %f0, %f2, %f52
90 fmuld %f0, %f2, %f54
91 faddd %f0, %f2, %f56
92 fmuld %f0, %f2, %f58
93 b,pt %xcc, fpdis_exit2
94 faddd %f0, %f2, %f60
95 1: mov SECONDARY_CONTEXT, %g3
96 add %g6, TI_FPREGS + 0x80, %g1
97 faddd %f0, %f2, %f4
98 fmuld %f0, %f2, %f6
99 ldxa [%g3] ASI_DMMU, %g5
100 sethi %hi(sparc64_kern_sec_context), %g2
101 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
102 stxa %g2, [%g3] ASI_DMMU
103 membar #Sync
104 add %g6, TI_FPREGS + 0xc0, %g2
105 faddd %f0, %f2, %f8
106 fmuld %f0, %f2, %f10
107 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
108 ldda [%g2] ASI_BLK_S, %f48
109 faddd %f0, %f2, %f12
110 fmuld %f0, %f2, %f14
111 faddd %f0, %f2, %f16
112 fmuld %f0, %f2, %f18
113 faddd %f0, %f2, %f20
114 fmuld %f0, %f2, %f22
115 faddd %f0, %f2, %f24
116 fmuld %f0, %f2, %f26
117 faddd %f0, %f2, %f28
118 fmuld %f0, %f2, %f30
119 membar #Sync
120 b,pt %xcc, fpdis_exit
121 nop
122 2: andcc %g5, FPRS_DU, %g0
123 bne,pt %icc, 3f
124 fzero %f32
125 mov SECONDARY_CONTEXT, %g3
126 fzero %f34
127 ldxa [%g3] ASI_DMMU, %g5
128 add %g6, TI_FPREGS, %g1
129 sethi %hi(sparc64_kern_sec_context), %g2
130 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
131 stxa %g2, [%g3] ASI_DMMU
132 membar #Sync
133 add %g6, TI_FPREGS + 0x40, %g2
134 faddd %f32, %f34, %f36
135 fmuld %f32, %f34, %f38
136 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
137 ldda [%g2] ASI_BLK_S, %f16
138 faddd %f32, %f34, %f40
139 fmuld %f32, %f34, %f42
140 faddd %f32, %f34, %f44
141 fmuld %f32, %f34, %f46
142 faddd %f32, %f34, %f48
143 fmuld %f32, %f34, %f50
144 faddd %f32, %f34, %f52
145 fmuld %f32, %f34, %f54
146 faddd %f32, %f34, %f56
147 fmuld %f32, %f34, %f58
148 faddd %f32, %f34, %f60
149 fmuld %f32, %f34, %f62
150 membar #Sync
151 ba,pt %xcc, fpdis_exit
152 nop
153 3: mov SECONDARY_CONTEXT, %g3
154 add %g6, TI_FPREGS, %g1
155 ldxa [%g3] ASI_DMMU, %g5
156 sethi %hi(sparc64_kern_sec_context), %g2
157 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
158 stxa %g2, [%g3] ASI_DMMU
159 membar #Sync
160 mov 0x40, %g2
161 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
162 ldda [%g1 + %g2] ASI_BLK_S, %f16
163 add %g1, 0x80, %g1
164 ldda [%g1] ASI_BLK_S, %f32
165 ldda [%g1 + %g2] ASI_BLK_S, %f48
166 membar #Sync
167 fpdis_exit:
168 stxa %g5, [%g3] ASI_DMMU
169 membar #Sync
170 fpdis_exit2:
171 wr %g7, 0, %gsr
172 ldx [%g6 + TI_XFSR], %fsr
173 rdpr %tstate, %g3
174 or %g3, %g4, %g3 ! anal...
175 wrpr %g3, %tstate
176 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
177 retry
178
179 .align 32
180 fp_other_bounce:
181 call do_fpother
182 add %sp, PTREGS_OFF, %o0
183 ba,pt %xcc, rtrap
184 clr %l6
185
186 .globl do_fpother_check_fitos
187 .align 32
188 do_fpother_check_fitos:
189 sethi %hi(fp_other_bounce - 4), %g7
190 or %g7, %lo(fp_other_bounce - 4), %g7
191
192 /* NOTE: Need to preserve %g7 until we fully commit
193 * to the fitos fixup.
194 */
195 stx %fsr, [%g6 + TI_XFSR]
196 rdpr %tstate, %g3
197 andcc %g3, TSTATE_PRIV, %g0
198 bne,pn %xcc, do_fptrap_after_fsr
199 nop
200 ldx [%g6 + TI_XFSR], %g3
201 srlx %g3, 14, %g1
202 and %g1, 7, %g1
203 cmp %g1, 2 ! Unfinished FP-OP
204 bne,pn %xcc, do_fptrap_after_fsr
205 sethi %hi(1 << 23), %g1 ! Inexact
206 andcc %g3, %g1, %g0
207 bne,pn %xcc, do_fptrap_after_fsr
208 rdpr %tpc, %g1
209 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
210 #define FITOS_MASK 0xc1f83fe0
211 #define FITOS_COMPARE 0x81a01880
212 sethi %hi(FITOS_MASK), %g1
213 or %g1, %lo(FITOS_MASK), %g1
214 and %g3, %g1, %g1
215 sethi %hi(FITOS_COMPARE), %g2
216 or %g2, %lo(FITOS_COMPARE), %g2
217 cmp %g1, %g2
218 bne,pn %xcc, do_fptrap_after_fsr
219 nop
220 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
221 sethi %hi(fitos_table_1), %g1
222 and %g3, 0x1f, %g2
223 or %g1, %lo(fitos_table_1), %g1
224 sllx %g2, 2, %g2
225 jmpl %g1 + %g2, %g0
226 ba,pt %xcc, fitos_emul_continue
227
228 fitos_table_1:
229 fitod %f0, %f62
230 fitod %f1, %f62
231 fitod %f2, %f62
232 fitod %f3, %f62
233 fitod %f4, %f62
234 fitod %f5, %f62
235 fitod %f6, %f62
236 fitod %f7, %f62
237 fitod %f8, %f62
238 fitod %f9, %f62
239 fitod %f10, %f62
240 fitod %f11, %f62
241 fitod %f12, %f62
242 fitod %f13, %f62
243 fitod %f14, %f62
244 fitod %f15, %f62
245 fitod %f16, %f62
246 fitod %f17, %f62
247 fitod %f18, %f62
248 fitod %f19, %f62
249 fitod %f20, %f62
250 fitod %f21, %f62
251 fitod %f22, %f62
252 fitod %f23, %f62
253 fitod %f24, %f62
254 fitod %f25, %f62
255 fitod %f26, %f62
256 fitod %f27, %f62
257 fitod %f28, %f62
258 fitod %f29, %f62
259 fitod %f30, %f62
260 fitod %f31, %f62
261
262 fitos_emul_continue:
263 sethi %hi(fitos_table_2), %g1
264 srl %g3, 25, %g2
265 or %g1, %lo(fitos_table_2), %g1
266 and %g2, 0x1f, %g2
267 sllx %g2, 2, %g2
268 jmpl %g1 + %g2, %g0
269 ba,pt %xcc, fitos_emul_fini
270
271 fitos_table_2:
272 fdtos %f62, %f0
273 fdtos %f62, %f1
274 fdtos %f62, %f2
275 fdtos %f62, %f3
276 fdtos %f62, %f4
277 fdtos %f62, %f5
278 fdtos %f62, %f6
279 fdtos %f62, %f7
280 fdtos %f62, %f8
281 fdtos %f62, %f9
282 fdtos %f62, %f10
283 fdtos %f62, %f11
284 fdtos %f62, %f12
285 fdtos %f62, %f13
286 fdtos %f62, %f14
287 fdtos %f62, %f15
288 fdtos %f62, %f16
289 fdtos %f62, %f17
290 fdtos %f62, %f18
291 fdtos %f62, %f19
292 fdtos %f62, %f20
293 fdtos %f62, %f21
294 fdtos %f62, %f22
295 fdtos %f62, %f23
296 fdtos %f62, %f24
297 fdtos %f62, %f25
298 fdtos %f62, %f26
299 fdtos %f62, %f27
300 fdtos %f62, %f28
301 fdtos %f62, %f29
302 fdtos %f62, %f30
303 fdtos %f62, %f31
304
305 fitos_emul_fini:
306 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
307 done
308
309 .globl do_fptrap
310 .align 32
311 do_fptrap:
312 stx %fsr, [%g6 + TI_XFSR]
313 do_fptrap_after_fsr:
314 ldub [%g6 + TI_FPSAVED], %g3
315 rd %fprs, %g1
316 or %g3, %g1, %g3
317 stb %g3, [%g6 + TI_FPSAVED]
318 rd %gsr, %g3
319 stx %g3, [%g6 + TI_GSR]
320 mov SECONDARY_CONTEXT, %g3
321 ldxa [%g3] ASI_DMMU, %g5
322 sethi %hi(sparc64_kern_sec_context), %g2
323 ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
324 stxa %g2, [%g3] ASI_DMMU
325 membar #Sync
326 add %g6, TI_FPREGS, %g2
327 andcc %g1, FPRS_DL, %g0
328 be,pn %icc, 4f
329 mov 0x40, %g3
330 stda %f0, [%g2] ASI_BLK_S
331 stda %f16, [%g2 + %g3] ASI_BLK_S
332 andcc %g1, FPRS_DU, %g0
333 be,pn %icc, 5f
334 4: add %g2, 128, %g2
335 stda %f32, [%g2] ASI_BLK_S
336 stda %f48, [%g2 + %g3] ASI_BLK_S
337 5: mov SECONDARY_CONTEXT, %g1
338 membar #Sync
339 stxa %g5, [%g1] ASI_DMMU
340 membar #Sync
341 ba,pt %xcc, etrap
342 wr %g0, 0, %fprs
343
344 /* The registers for cross calls will be:
345 *
346 * DATA 0: [low 32-bits] Address of function to call, jmp to this
347 * [high 32-bits] MMU Context Argument 0, place in %g5
348 * DATA 1: Address Argument 1, place in %g1
349 * DATA 2: Address Argument 2, place in %g7
350 *
351 * With this method we can do most of the cross-call tlb/cache
352 * flushing very quickly.
353 *
354 * Current CPU's IRQ worklist table is locked into %g6, don't touch.
355 */
356 .text
357 .align 32
358 .globl do_ivec
359 do_ivec:
360 mov 0x40, %g3
361 ldxa [%g3 + %g0] ASI_INTR_R, %g3
362 sethi %hi(KERNBASE), %g4
363 cmp %g3, %g4
364 bgeu,pn %xcc, do_ivec_xcall
365 srlx %g3, 32, %g5
366 stxa %g0, [%g0] ASI_INTR_RECEIVE
367 membar #Sync
368
369 sethi %hi(ivector_table), %g2
370 sllx %g3, 5, %g3
371 or %g2, %lo(ivector_table), %g2
372 add %g2, %g3, %g3
373 ldub [%g3 + 0x04], %g4 /* pil */
374 mov 1, %g2
375 sllx %g2, %g4, %g2
376 sllx %g4, 2, %g4
377
378 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
379 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
380 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
381 wr %g2, 0x0, %set_softint
382 retry
383 do_ivec_xcall:
384 mov 0x50, %g1
385 ldxa [%g1 + %g0] ASI_INTR_R, %g1
386 srl %g3, 0, %g3
387
388 mov 0x60, %g7
389 ldxa [%g7 + %g0] ASI_INTR_R, %g7
390 stxa %g0, [%g0] ASI_INTR_RECEIVE
391 membar #Sync
392 ba,pt %xcc, 1f
393 nop
394
395 .align 32
396 1: jmpl %g3, %g0
397 nop
398
399 .globl save_alternate_globals
400 save_alternate_globals: /* %o0 = save_area */
401 rdpr %pstate, %o5
402 andn %o5, PSTATE_IE, %o1
403 wrpr %o1, PSTATE_AG, %pstate
404 stx %g0, [%o0 + 0x00]
405 stx %g1, [%o0 + 0x08]
406 stx %g2, [%o0 + 0x10]
407 stx %g3, [%o0 + 0x18]
408 stx %g4, [%o0 + 0x20]
409 stx %g5, [%o0 + 0x28]
410 stx %g6, [%o0 + 0x30]
411 stx %g7, [%o0 + 0x38]
412 wrpr %o1, PSTATE_IG, %pstate
413 stx %g0, [%o0 + 0x40]
414 stx %g1, [%o0 + 0x48]
415 stx %g2, [%o0 + 0x50]
416 stx %g3, [%o0 + 0x58]
417 stx %g4, [%o0 + 0x60]
418 stx %g5, [%o0 + 0x68]
419 stx %g6, [%o0 + 0x70]
420 stx %g7, [%o0 + 0x78]
421 wrpr %o1, PSTATE_MG, %pstate
422 stx %g0, [%o0 + 0x80]
423 stx %g1, [%o0 + 0x88]
424 stx %g2, [%o0 + 0x90]
425 stx %g3, [%o0 + 0x98]
426 stx %g4, [%o0 + 0xa0]
427 stx %g5, [%o0 + 0xa8]
428 stx %g6, [%o0 + 0xb0]
429 stx %g7, [%o0 + 0xb8]
430 wrpr %o5, 0x0, %pstate
431 retl
432 nop
433
434 .globl restore_alternate_globals
435 restore_alternate_globals: /* %o0 = save_area */
436 rdpr %pstate, %o5
437 andn %o5, PSTATE_IE, %o1
438 wrpr %o1, PSTATE_AG, %pstate
439 ldx [%o0 + 0x00], %g0
440 ldx [%o0 + 0x08], %g1
441 ldx [%o0 + 0x10], %g2
442 ldx [%o0 + 0x18], %g3
443 ldx [%o0 + 0x20], %g4
444 ldx [%o0 + 0x28], %g5
445 ldx [%o0 + 0x30], %g6
446 ldx [%o0 + 0x38], %g7
447 wrpr %o1, PSTATE_IG, %pstate
448 ldx [%o0 + 0x40], %g0
449 ldx [%o0 + 0x48], %g1
450 ldx [%o0 + 0x50], %g2
451 ldx [%o0 + 0x58], %g3
452 ldx [%o0 + 0x60], %g4
453 ldx [%o0 + 0x68], %g5
454 ldx [%o0 + 0x70], %g6
455 ldx [%o0 + 0x78], %g7
456 wrpr %o1, PSTATE_MG, %pstate
457 ldx [%o0 + 0x80], %g0
458 ldx [%o0 + 0x88], %g1
459 ldx [%o0 + 0x90], %g2
460 ldx [%o0 + 0x98], %g3
461 ldx [%o0 + 0xa0], %g4
462 ldx [%o0 + 0xa8], %g5
463 ldx [%o0 + 0xb0], %g6
464 ldx [%o0 + 0xb8], %g7
465 wrpr %o5, 0x0, %pstate
466 retl
467 nop
468
469 .globl getcc, setcc
470 getcc:
471 ldx [%o0 + PT_V9_TSTATE], %o1
472 srlx %o1, 32, %o1
473 and %o1, 0xf, %o1
474 retl
475 stx %o1, [%o0 + PT_V9_G1]
476 setcc:
477 ldx [%o0 + PT_V9_TSTATE], %o1
478 ldx [%o0 + PT_V9_G1], %o2
479 or %g0, %ulo(TSTATE_ICC), %o3
480 sllx %o3, 32, %o3
481 andn %o1, %o3, %o1
482 sllx %o2, 32, %o2
483 and %o2, %o3, %o2
484 or %o1, %o2, %o1
485 retl
486 stx %o1, [%o0 + PT_V9_TSTATE]
487
488 .globl utrap, utrap_ill
489 utrap: brz,pn %g1, etrap
490 nop
491 save %sp, -128, %sp
492 rdpr %tstate, %l6
493 rdpr %cwp, %l7
494 andn %l6, TSTATE_CWP, %l6
495 wrpr %l6, %l7, %tstate
496 rdpr %tpc, %l6
497 rdpr %tnpc, %l7
498 wrpr %g1, 0, %tnpc
499 done
500 utrap_ill:
501 call bad_trap
502 add %sp, PTREGS_OFF, %o0
503 ba,pt %xcc, rtrap
504 clr %l6
505
506 /* XXX Here is stuff we still need to write... -DaveM XXX */
507 .globl netbsd_syscall
508 netbsd_syscall:
509 retl
510 nop
511
512 /* We need to carefully read the error status, ACK
513 * the errors, prevent recursive traps, and pass the
514 * information on to C code for logging.
515 *
516 * We pass the AFAR in as-is, and we encode the status
517 * information as described in asm-sparc64/sfafsr.h
518 */
519 .globl __spitfire_access_error
520 __spitfire_access_error:
521 /* Disable ESTATE error reporting so that we do not
522 * take recursive traps and RED state the processor.
523 */
524 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
525 membar #Sync
526
527 mov UDBE_UE, %g1
528 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
529
530 /* __spitfire_cee_trap branches here with AFSR in %g4 and
531 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
532 * ESTATE Error Enable register.
533 */
534 __spitfire_cee_trap_continue:
535 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
536
537 rdpr %tt, %g3
538 and %g3, 0x1ff, %g3 ! Paranoia
539 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
540 or %g4, %g3, %g4
541 rdpr %tl, %g3
542 cmp %g3, 1
543 mov 1, %g3
544 bleu %xcc, 1f
545 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
546
547 or %g4, %g3, %g4
548
549 /* Read in the UDB error register state, clearing the
550 * sticky error bits as-needed. We only clear them if
551 * the UE bit is set. Likewise, __spitfire_cee_trap
552 * below will only do so if the CE bit is set.
553 *
554 * NOTE: UltraSparc-I/II have high and low UDB error
555 * registers, corresponding to the two UDB units
556 * present on those chips. UltraSparc-IIi only
557 * has a single UDB, called "SDB" in the manual.
558 * For IIi the upper UDB register always reads
559 * as zero so for our purposes things will just
560 * work with the checks below.
561 */
562 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
563 and %g3, 0x3ff, %g7 ! Paranoia
564 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
565 or %g4, %g7, %g4
566 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
567 be,pn %xcc, 1f
568 nop
569 stxa %g3, [%g0] ASI_UDB_ERROR_W
570 membar #Sync
571
572 1: mov 0x18, %g3
573 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
574 and %g3, 0x3ff, %g7 ! Paranoia
575 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
576 or %g4, %g7, %g4
577 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
578 be,pn %xcc, 1f
579 nop
580 mov 0x18, %g7
581 stxa %g3, [%g7] ASI_UDB_ERROR_W
582 membar #Sync
583
584 1: /* Ok, now that we've latched the error state,
585 * clear the sticky bits in the AFSR.
586 */
587 stxa %g4, [%g0] ASI_AFSR
588 membar #Sync
589
590 rdpr %tl, %g2
591 cmp %g2, 1
592 rdpr %pil, %g2
593 bleu,pt %xcc, 1f
594 wrpr %g0, 15, %pil
595
596 ba,pt %xcc, etraptl1
597 rd %pc, %g7
598
599 ba,pt %xcc, 2f
600 nop
601
602 1: ba,pt %xcc, etrap_irq
603 rd %pc, %g7
604
605 2: mov %l4, %o1
606 mov %l5, %o2
607 call spitfire_access_error
608 add %sp, PTREGS_OFF, %o0
609 ba,pt %xcc, rtrap
610 clr %l6
611
612 /* This is the trap handler entry point for ECC correctable
613 * errors. They are corrected, but we listen for the trap
614 * so that the event can be logged.
615 *
616 * Disrupting errors are either:
617 * 1) single-bit ECC errors during UDB reads to system
618 * memory
619 * 2) data parity errors during write-back events
620 *
621 * As far as I can make out from the manual, the CEE trap
622 * is only for correctable errors during memory read
623 * accesses by the front-end of the processor.
624 *
625 * The code below is only for trap level 1 CEE events,
626 * as it is the only situation where we can safely record
627 * and log. For trap level >1 we just clear the CE bit
628 * in the AFSR and return.
629 *
630 * This is just like __spiftire_access_error above, but it
631 * specifically handles correctable errors. If an
632 * uncorrectable error is indicated in the AFSR we
633 * will branch directly above to __spitfire_access_error
634 * to handle it instead. Uncorrectable therefore takes
635 * priority over correctable, and the error logging
636 * C code will notice this case by inspecting the
637 * trap type.
638 */
639 .globl __spitfire_cee_trap
640 __spitfire_cee_trap:
641 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
642 mov 1, %g3
643 sllx %g3, SFAFSR_UE_SHIFT, %g3
644 andcc %g4, %g3, %g0 ! Check for UE
645 bne,pn %xcc, __spitfire_access_error
646 nop
647
648 /* Ok, in this case we only have a correctable error.
649 * Indicate we only wish to capture that state in register
650 * %g1, and we only disable CE error reporting unlike UE
651 * handling which disables all errors.
652 */
653 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
654 andn %g3, ESTATE_ERR_CE, %g3
655 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
656 membar #Sync
657
658 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
659 ba,pt %xcc, __spitfire_cee_trap_continue
660 mov UDBE_CE, %g1
661
662 .globl __spitfire_data_access_exception
663 .globl __spitfire_data_access_exception_tl1
664 __spitfire_data_access_exception_tl1:
665 rdpr %pstate, %g4
666 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
667 mov TLB_SFSR, %g3
668 mov DMMU_SFAR, %g5
669 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
670 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
671 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
672 membar #Sync
673 rdpr %tt, %g3
674 cmp %g3, 0x80 ! first win spill/fill trap
675 blu,pn %xcc, 1f
676 cmp %g3, 0xff ! last win spill/fill trap
677 bgu,pn %xcc, 1f
678 nop
679 ba,pt %xcc, winfix_dax
680 rdpr %tpc, %g3
681 1: sethi %hi(109f), %g7
682 ba,pt %xcc, etraptl1
683 109: or %g7, %lo(109b), %g7
684 mov %l4, %o1
685 mov %l5, %o2
686 call spitfire_data_access_exception_tl1
687 add %sp, PTREGS_OFF, %o0
688 ba,pt %xcc, rtrap
689 clr %l6
690
691 __spitfire_data_access_exception:
692 rdpr %pstate, %g4
693 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
694 mov TLB_SFSR, %g3
695 mov DMMU_SFAR, %g5
696 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
697 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
698 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
699 membar #Sync
700 sethi %hi(109f), %g7
701 ba,pt %xcc, etrap
702 109: or %g7, %lo(109b), %g7
703 mov %l4, %o1
704 mov %l5, %o2
705 call spitfire_data_access_exception
706 add %sp, PTREGS_OFF, %o0
707 ba,pt %xcc, rtrap
708 clr %l6
709
710 .globl __spitfire_insn_access_exception
711 .globl __spitfire_insn_access_exception_tl1
712 __spitfire_insn_access_exception_tl1:
713 rdpr %pstate, %g4
714 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
715 mov TLB_SFSR, %g3
716 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
717 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
718 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
719 membar #Sync
720 sethi %hi(109f), %g7
721 ba,pt %xcc, etraptl1
722 109: or %g7, %lo(109b), %g7
723 mov %l4, %o1
724 mov %l5, %o2
725 call spitfire_insn_access_exception_tl1
726 add %sp, PTREGS_OFF, %o0
727 ba,pt %xcc, rtrap
728 clr %l6
729
730 __spitfire_insn_access_exception:
731 rdpr %pstate, %g4
732 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
733 mov TLB_SFSR, %g3
734 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
735 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
736 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
737 membar #Sync
738 sethi %hi(109f), %g7
739 ba,pt %xcc, etrap
740 109: or %g7, %lo(109b), %g7
741 mov %l4, %o1
742 mov %l5, %o2
743 call spitfire_insn_access_exception
744 add %sp, PTREGS_OFF, %o0
745 ba,pt %xcc, rtrap
746 clr %l6
747
748 /* These get patched into the trap table at boot time
749 * once we know we have a cheetah processor.
750 */
751 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
752 cheetah_fecc_trap_vector:
753 membar #Sync
754 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
755 andn %g1, DCU_DC | DCU_IC, %g1
756 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
757 membar #Sync
758 sethi %hi(cheetah_fast_ecc), %g2
759 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
760 mov 0, %g1
761 cheetah_fecc_trap_vector_tl1:
762 membar #Sync
763 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
764 andn %g1, DCU_DC | DCU_IC, %g1
765 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
766 membar #Sync
767 sethi %hi(cheetah_fast_ecc), %g2
768 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
769 mov 1, %g1
770 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
771 cheetah_cee_trap_vector:
772 membar #Sync
773 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
774 andn %g1, DCU_IC, %g1
775 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
776 membar #Sync
777 sethi %hi(cheetah_cee), %g2
778 jmpl %g2 + %lo(cheetah_cee), %g0
779 mov 0, %g1
780 cheetah_cee_trap_vector_tl1:
781 membar #Sync
782 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
783 andn %g1, DCU_IC, %g1
784 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
785 membar #Sync
786 sethi %hi(cheetah_cee), %g2
787 jmpl %g2 + %lo(cheetah_cee), %g0
788 mov 1, %g1
789 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
790 cheetah_deferred_trap_vector:
791 membar #Sync
792 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
793 andn %g1, DCU_DC | DCU_IC, %g1;
794 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
795 membar #Sync;
796 sethi %hi(cheetah_deferred_trap), %g2
797 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
798 mov 0, %g1
799 cheetah_deferred_trap_vector_tl1:
800 membar #Sync;
801 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
802 andn %g1, DCU_DC | DCU_IC, %g1;
803 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
804 membar #Sync;
805 sethi %hi(cheetah_deferred_trap), %g2
806 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
807 mov 1, %g1
808
809 /* Cheetah+ specific traps. These are for the new I/D cache parity
810 * error traps. The first argument to cheetah_plus_parity_handler
811 * is encoded as follows:
812 *
813 * Bit0: 0=dcache,1=icache
814 * Bit1: 0=recoverable,1=unrecoverable
815 */
816 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
817 cheetah_plus_dcpe_trap_vector:
818 membar #Sync
819 sethi %hi(do_cheetah_plus_data_parity), %g7
820 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
821 nop
822 nop
823 nop
824 nop
825 nop
826
827 do_cheetah_plus_data_parity:
828 rdpr %pil, %g2
829 wrpr %g0, 15, %pil
830 ba,pt %xcc, etrap_irq
831 rd %pc, %g7
832 mov 0x0, %o0
833 call cheetah_plus_parity_error
834 add %sp, PTREGS_OFF, %o1
835 ba,a,pt %xcc, rtrap_irq
836
837 cheetah_plus_dcpe_trap_vector_tl1:
838 membar #Sync
839 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
840 sethi %hi(do_dcpe_tl1), %g3
841 jmpl %g3 + %lo(do_dcpe_tl1), %g0
842 nop
843 nop
844 nop
845 nop
846
847 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
848 cheetah_plus_icpe_trap_vector:
849 membar #Sync
850 sethi %hi(do_cheetah_plus_insn_parity), %g7
851 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
852 nop
853 nop
854 nop
855 nop
856 nop
857
858 do_cheetah_plus_insn_parity:
859 rdpr %pil, %g2
860 wrpr %g0, 15, %pil
861 ba,pt %xcc, etrap_irq
862 rd %pc, %g7
863 mov 0x1, %o0
864 call cheetah_plus_parity_error
865 add %sp, PTREGS_OFF, %o1
866 ba,a,pt %xcc, rtrap_irq
867
868 cheetah_plus_icpe_trap_vector_tl1:
869 membar #Sync
870 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
871 sethi %hi(do_icpe_tl1), %g3
872 jmpl %g3 + %lo(do_icpe_tl1), %g0
873 nop
874 nop
875 nop
876 nop
877
878 /* If we take one of these traps when tl >= 1, then we
879 * jump to interrupt globals. If some trap level above us
880 * was also using interrupt globals, we cannot recover.
881 * We may use all interrupt global registers except %g6.
882 */
883 .globl do_dcpe_tl1, do_icpe_tl1
884 do_dcpe_tl1:
885 rdpr %tl, %g1 ! Save original trap level
886 mov 1, %g2 ! Setup TSTATE checking loop
887 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
888 1: wrpr %g2, %tl ! Set trap level to check
889 rdpr %tstate, %g4 ! Read TSTATE for this level
890 andcc %g4, %g3, %g0 ! Interrupt globals in use?
891 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
892 wrpr %g1, %tl ! Restore original trap level
893 add %g2, 1, %g2 ! Next trap level
894 cmp %g2, %g1 ! Hit them all yet?
895 ble,pt %icc, 1b ! Not yet
896 nop
897 wrpr %g1, %tl ! Restore original trap level
898 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
899 sethi %hi(dcache_parity_tl1_occurred), %g2
900 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
901 add %g1, 1, %g1
902 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
903 /* Reset D-cache parity */
904 sethi %hi(1 << 16), %g1 ! D-cache size
905 mov (1 << 5), %g2 ! D-cache line size
906 sub %g1, %g2, %g1 ! Move down 1 cacheline
907 1: srl %g1, 14, %g3 ! Compute UTAG
908 membar #Sync
909 stxa %g3, [%g1] ASI_DCACHE_UTAG
910 membar #Sync
911 sub %g2, 8, %g3 ! 64-bit data word within line
912 2: membar #Sync
913 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
914 membar #Sync
915 subcc %g3, 8, %g3 ! Next 64-bit data word
916 bge,pt %icc, 2b
917 nop
918 subcc %g1, %g2, %g1 ! Next cacheline
919 bge,pt %icc, 1b
920 nop
921 ba,pt %xcc, dcpe_icpe_tl1_common
922 nop
923
924 do_dcpe_tl1_fatal:
925 sethi %hi(1f), %g7
926 ba,pt %xcc, etraptl1
927 1: or %g7, %lo(1b), %g7
928 mov 0x2, %o0
929 call cheetah_plus_parity_error
930 add %sp, PTREGS_OFF, %o1
931 ba,pt %xcc, rtrap
932 clr %l6
933
934 do_icpe_tl1:
935 rdpr %tl, %g1 ! Save original trap level
936 mov 1, %g2 ! Setup TSTATE checking loop
937 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
938 1: wrpr %g2, %tl ! Set trap level to check
939 rdpr %tstate, %g4 ! Read TSTATE for this level
940 andcc %g4, %g3, %g0 ! Interrupt globals in use?
941 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
942 wrpr %g1, %tl ! Restore original trap level
943 add %g2, 1, %g2 ! Next trap level
944 cmp %g2, %g1 ! Hit them all yet?
945 ble,pt %icc, 1b ! Not yet
946 nop
947 wrpr %g1, %tl ! Restore original trap level
948 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
949 sethi %hi(icache_parity_tl1_occurred), %g2
950 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
951 add %g1, 1, %g1
952 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
953 /* Flush I-cache */
954 sethi %hi(1 << 15), %g1 ! I-cache size
955 mov (1 << 5), %g2 ! I-cache line size
956 sub %g1, %g2, %g1
957 1: or %g1, (2 << 3), %g3
958 stxa %g0, [%g3] ASI_IC_TAG
959 membar #Sync
960 subcc %g1, %g2, %g1
961 bge,pt %icc, 1b
962 nop
963 ba,pt %xcc, dcpe_icpe_tl1_common
964 nop
965
966 do_icpe_tl1_fatal:
967 sethi %hi(1f), %g7
968 ba,pt %xcc, etraptl1
969 1: or %g7, %lo(1b), %g7
970 mov 0x3, %o0
971 call cheetah_plus_parity_error
972 add %sp, PTREGS_OFF, %o1
973 ba,pt %xcc, rtrap
974 clr %l6
975
976 dcpe_icpe_tl1_common:
977 /* Flush D-cache, re-enable D/I caches in DCU and finally
978 * retry the trapping instruction.
979 */
980 sethi %hi(1 << 16), %g1 ! D-cache size
981 mov (1 << 5), %g2 ! D-cache line size
982 sub %g1, %g2, %g1
983 1: stxa %g0, [%g1] ASI_DCACHE_TAG
984 membar #Sync
985 subcc %g1, %g2, %g1
986 bge,pt %icc, 1b
987 nop
988 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
989 or %g1, (DCU_DC | DCU_IC), %g1
990 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
991 membar #Sync
992 retry
993
994 /* Capture I/D/E-cache state into per-cpu error scoreboard.
995 *
996 * %g1: (TL>=0) ? 1 : 0
997 * %g2: scratch
998 * %g3: scratch
999 * %g4: AFSR
1000 * %g5: AFAR
1001 * %g6: current thread ptr
1002 * %g7: scratch
1003 */
1004 __cheetah_log_error:
1005 /* Put "TL1" software bit into AFSR. */
1006 and %g1, 0x1, %g1
1007 sllx %g1, 63, %g2
1008 or %g4, %g2, %g4
1009
1010 /* Get log entry pointer for this cpu at this trap level. */
1011 BRANCH_IF_JALAPENO(g2,g3,50f)
1012 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1013 srlx %g2, 17, %g2
1014 ba,pt %xcc, 60f
1015 and %g2, 0x3ff, %g2
1016
1017 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1018 srlx %g2, 17, %g2
1019 and %g2, 0x1f, %g2
1020
1021 60: sllx %g2, 9, %g2
1022 sethi %hi(cheetah_error_log), %g3
1023 ldx [%g3 + %lo(cheetah_error_log)], %g3
1024 brz,pn %g3, 80f
1025 nop
1026
1027 add %g3, %g2, %g3
1028 sllx %g1, 8, %g1
1029 add %g3, %g1, %g1
1030
1031 /* %g1 holds pointer to the top of the logging scoreboard */
1032 ldx [%g1 + 0x0], %g7
1033 cmp %g7, -1
1034 bne,pn %xcc, 80f
1035 nop
1036
1037 stx %g4, [%g1 + 0x0]
1038 stx %g5, [%g1 + 0x8]
1039 add %g1, 0x10, %g1
1040
1041 /* %g1 now points to D-cache logging area */
1042 set 0x3ff8, %g2 /* DC_addr mask */
1043 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1044 srlx %g5, 12, %g3
1045 or %g3, 1, %g3 /* PHYS tag + valid */
1046
1047 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
1048 cmp %g3, %g7 /* TAG match? */
1049 bne,pt %xcc, 13f
1050 nop
1051
1052 /* Yep, what we want, capture state. */
1053 stx %g2, [%g1 + 0x20]
1054 stx %g7, [%g1 + 0x28]
1055
1056 /* A membar Sync is required before and after utag access. */
1057 membar #Sync
1058 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1059 membar #Sync
1060 stx %g7, [%g1 + 0x30]
1061 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1062 stx %g7, [%g1 + 0x38]
1063 clr %g3
1064
1065 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1066 stx %g7, [%g1]
1067 add %g3, (1 << 5), %g3
1068 cmp %g3, (4 << 5)
1069 bl,pt %xcc, 12b
1070 add %g1, 0x8, %g1
1071
1072 ba,pt %xcc, 20f
1073 add %g1, 0x20, %g1
1074
1075 13: sethi %hi(1 << 14), %g7
1076 add %g2, %g7, %g2
1077 srlx %g2, 14, %g7
1078 cmp %g7, 4
1079 bl,pt %xcc, 10b
1080 nop
1081
1082 add %g1, 0x40, %g1
1083
1084 /* %g1 now points to I-cache logging area */
1085 20: set 0x1fe0, %g2 /* IC_addr mask */
1086 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1087 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1088 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1089 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1090
1091 21: ldxa [%g2] ASI_IC_TAG, %g7
1092 andn %g7, 0xff, %g7
1093 cmp %g3, %g7
1094 bne,pt %xcc, 23f
1095 nop
1096
1097 /* Yep, what we want, capture state. */
1098 stx %g2, [%g1 + 0x40]
1099 stx %g7, [%g1 + 0x48]
1100 add %g2, (1 << 3), %g2
1101 ldxa [%g2] ASI_IC_TAG, %g7
1102 add %g2, (1 << 3), %g2
1103 stx %g7, [%g1 + 0x50]
1104 ldxa [%g2] ASI_IC_TAG, %g7
1105 add %g2, (1 << 3), %g2
1106 stx %g7, [%g1 + 0x60]
1107 ldxa [%g2] ASI_IC_TAG, %g7
1108 stx %g7, [%g1 + 0x68]
1109 sub %g2, (3 << 3), %g2
1110 ldxa [%g2] ASI_IC_STAG, %g7
1111 stx %g7, [%g1 + 0x58]
1112 clr %g3
1113 srlx %g2, 2, %g2
1114
1115 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1116 stx %g7, [%g1]
1117 add %g3, (1 << 3), %g3
1118 cmp %g3, (8 << 3)
1119 bl,pt %xcc, 22b
1120 add %g1, 0x8, %g1
1121
1122 ba,pt %xcc, 30f
1123 add %g1, 0x30, %g1
1124
1125 23: sethi %hi(1 << 14), %g7
1126 add %g2, %g7, %g2
1127 srlx %g2, 14, %g7
1128 cmp %g7, 4
1129 bl,pt %xcc, 21b
1130 nop
1131
1132 add %g1, 0x70, %g1
1133
1134 /* %g1 now points to E-cache logging area */
1135 30: andn %g5, (32 - 1), %g2
1136 stx %g2, [%g1 + 0x20]
1137 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1138 stx %g7, [%g1 + 0x28]
1139 ldxa [%g2] ASI_EC_R, %g0
1140 clr %g3
1141
1142 31: ldxa [%g3] ASI_EC_DATA, %g7
1143 stx %g7, [%g1 + %g3]
1144 add %g3, 0x8, %g3
1145 cmp %g3, 0x20
1146
1147 bl,pt %xcc, 31b
1148 nop
1149 80:
1150 rdpr %tt, %g2
1151 cmp %g2, 0x70
1152 be c_fast_ecc
1153 cmp %g2, 0x63
1154 be c_cee
1155 nop
1156 ba,pt %xcc, c_deferred
1157
1158 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1159 * in the trap table. That code has done a memory barrier
1160 * and has disabled both the I-cache and D-cache in the DCU
1161 * control register. The I-cache is disabled so that we may
1162 * capture the corrupted cache line, and the D-cache is disabled
1163 * because corrupt data may have been placed there and we don't
1164 * want to reference it.
1165 *
1166 * %g1 is one if this trap occurred at %tl >= 1.
1167 *
1168 * Next, we turn off error reporting so that we don't recurse.
1169 */
1170 .globl cheetah_fast_ecc
1171 cheetah_fast_ecc:
1172 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1173 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1174 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1175 membar #Sync
1176
1177 /* Fetch and clear AFSR/AFAR */
1178 ldxa [%g0] ASI_AFSR, %g4
1179 ldxa [%g0] ASI_AFAR, %g5
1180 stxa %g4, [%g0] ASI_AFSR
1181 membar #Sync
1182
1183 ba,pt %xcc, __cheetah_log_error
1184 nop
1185
1186 c_fast_ecc:
1187 rdpr %pil, %g2
1188 wrpr %g0, 15, %pil
1189 ba,pt %xcc, etrap_irq
1190 rd %pc, %g7
1191 mov %l4, %o1
1192 mov %l5, %o2
1193 call cheetah_fecc_handler
1194 add %sp, PTREGS_OFF, %o0
1195 ba,a,pt %xcc, rtrap_irq
1196
1197 /* Our caller has disabled I-cache and performed membar Sync. */
1198 .globl cheetah_cee
1199 cheetah_cee:
1200 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1201 andn %g2, ESTATE_ERROR_CEEN, %g2
1202 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1203 membar #Sync
1204
1205 /* Fetch and clear AFSR/AFAR */
1206 ldxa [%g0] ASI_AFSR, %g4
1207 ldxa [%g0] ASI_AFAR, %g5
1208 stxa %g4, [%g0] ASI_AFSR
1209 membar #Sync
1210
1211 ba,pt %xcc, __cheetah_log_error
1212 nop
1213
1214 c_cee:
1215 rdpr %pil, %g2
1216 wrpr %g0, 15, %pil
1217 ba,pt %xcc, etrap_irq
1218 rd %pc, %g7
1219 mov %l4, %o1
1220 mov %l5, %o2
1221 call cheetah_cee_handler
1222 add %sp, PTREGS_OFF, %o0
1223 ba,a,pt %xcc, rtrap_irq
1224
1225 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1226 .globl cheetah_deferred_trap
1227 cheetah_deferred_trap:
1228 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1229 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1230 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1231 membar #Sync
1232
1233 /* Fetch and clear AFSR/AFAR */
1234 ldxa [%g0] ASI_AFSR, %g4
1235 ldxa [%g0] ASI_AFAR, %g5
1236 stxa %g4, [%g0] ASI_AFSR
1237 membar #Sync
1238
1239 ba,pt %xcc, __cheetah_log_error
1240 nop
1241
1242 c_deferred:
1243 rdpr %pil, %g2
1244 wrpr %g0, 15, %pil
1245 ba,pt %xcc, etrap_irq
1246 rd %pc, %g7
1247 mov %l4, %o1
1248 mov %l5, %o2
1249 call cheetah_deferred_handler
1250 add %sp, PTREGS_OFF, %o0
1251 ba,a,pt %xcc, rtrap_irq
1252
1253 .globl __do_privact
1254 __do_privact:
1255 mov TLB_SFSR, %g3
1256 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1257 membar #Sync
1258 sethi %hi(109f), %g7
1259 ba,pt %xcc, etrap
1260 109: or %g7, %lo(109b), %g7
1261 call do_privact
1262 add %sp, PTREGS_OFF, %o0
1263 ba,pt %xcc, rtrap
1264 clr %l6
1265
1266 .globl do_mna
1267 do_mna:
1268 rdpr %tl, %g3
1269 cmp %g3, 1
1270
1271 /* Setup %g4/%g5 now as they are used in the
1272 * winfixup code.
1273 */
1274 mov TLB_SFSR, %g3
1275 mov DMMU_SFAR, %g4
1276 ldxa [%g4] ASI_DMMU, %g4
1277 ldxa [%g3] ASI_DMMU, %g5
1278 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1279 membar #Sync
1280 bgu,pn %icc, winfix_mna
1281 rdpr %tpc, %g3
1282
1283 1: sethi %hi(109f), %g7
1284 ba,pt %xcc, etrap
1285 109: or %g7, %lo(109b), %g7
1286 mov %l4, %o1
1287 mov %l5, %o2
1288 call mem_address_unaligned
1289 add %sp, PTREGS_OFF, %o0
1290 ba,pt %xcc, rtrap
1291 clr %l6
1292
1293 .globl do_lddfmna
1294 do_lddfmna:
1295 sethi %hi(109f), %g7
1296 mov TLB_SFSR, %g4
1297 ldxa [%g4] ASI_DMMU, %g5
1298 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1299 membar #Sync
1300 mov DMMU_SFAR, %g4
1301 ldxa [%g4] ASI_DMMU, %g4
1302 ba,pt %xcc, etrap
1303 109: or %g7, %lo(109b), %g7
1304 mov %l4, %o1
1305 mov %l5, %o2
1306 call handle_lddfmna
1307 add %sp, PTREGS_OFF, %o0
1308 ba,pt %xcc, rtrap
1309 clr %l6
1310
1311 .globl do_stdfmna
1312 do_stdfmna:
1313 sethi %hi(109f), %g7
1314 mov TLB_SFSR, %g4
1315 ldxa [%g4] ASI_DMMU, %g5
1316 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1317 membar #Sync
1318 mov DMMU_SFAR, %g4
1319 ldxa [%g4] ASI_DMMU, %g4
1320 ba,pt %xcc, etrap
1321 109: or %g7, %lo(109b), %g7
1322 mov %l4, %o1
1323 mov %l5, %o2
1324 call handle_stdfmna
1325 add %sp, PTREGS_OFF, %o0
1326 ba,pt %xcc, rtrap
1327 clr %l6
1328
1329 .globl breakpoint_trap
1330 breakpoint_trap:
1331 call sparc_breakpoint
1332 add %sp, PTREGS_OFF, %o0
1333 ba,pt %xcc, rtrap
1334 nop
1335
1336 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1337 defined(CONFIG_SOLARIS_EMUL_MODULE)
1338 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1339 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1340 * This is complete brain damage.
1341 */
1342 .globl sunos_indir
1343 sunos_indir:
1344 srl %o0, 0, %o0
1345 mov %o7, %l4
1346 cmp %o0, NR_SYSCALLS
1347 blu,a,pt %icc, 1f
1348 sll %o0, 0x2, %o0
1349 sethi %hi(sunos_nosys), %l6
1350 b,pt %xcc, 2f
1351 or %l6, %lo(sunos_nosys), %l6
1352 1: sethi %hi(sunos_sys_table), %l7
1353 or %l7, %lo(sunos_sys_table), %l7
1354 lduw [%l7 + %o0], %l6
1355 2: mov %o1, %o0
1356 mov %o2, %o1
1357 mov %o3, %o2
1358 mov %o4, %o3
1359 mov %o5, %o4
1360 call %l6
1361 mov %l4, %o7
1362
1363 .globl sunos_getpid
1364 sunos_getpid:
1365 call sys_getppid
1366 nop
1367 call sys_getpid
1368 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1369 b,pt %xcc, ret_sys_call
1370 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1371
1372 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1373 .globl sunos_getuid
1374 sunos_getuid:
1375 call sys32_geteuid16
1376 nop
1377 call sys32_getuid16
1378 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1379 b,pt %xcc, ret_sys_call
1380 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1381
1382 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1383 .globl sunos_getgid
1384 sunos_getgid:
1385 call sys32_getegid16
1386 nop
1387 call sys32_getgid16
1388 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1389 b,pt %xcc, ret_sys_call
1390 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1391 #endif
1392
1393 /* SunOS's execv() call only specifies the argv argument, the
1394 * environment settings are the same as the calling processes.
1395 */
1396 .globl sunos_execv
1397 sys_execve:
1398 sethi %hi(sparc_execve), %g1
1399 ba,pt %xcc, execve_merge
1400 or %g1, %lo(sparc_execve), %g1
1401 #ifdef CONFIG_COMPAT
1402 .globl sys_execve
1403 sunos_execv:
1404 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1405 .globl sys32_execve
1406 sys32_execve:
1407 sethi %hi(sparc32_execve), %g1
1408 or %g1, %lo(sparc32_execve), %g1
1409 #endif
1410 execve_merge:
1411 flushw
1412 jmpl %g1, %g0
1413 add %sp, PTREGS_OFF, %o0
1414
1415 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1416 .globl sys_sigsuspend, sys_rt_sigsuspend
1417 .globl sys_rt_sigreturn
1418 .globl sys_ptrace
1419 .globl sys_sigaltstack
1420 .align 32
1421 sys_pipe: ba,pt %xcc, sparc_pipe
1422 add %sp, PTREGS_OFF, %o0
1423 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1424 add %sp, PTREGS_OFF, %o0
1425 sys_memory_ordering:
1426 ba,pt %xcc, sparc_memory_ordering
1427 add %sp, PTREGS_OFF, %o1
1428 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1429 add %i6, STACK_BIAS, %o2
1430 #ifdef CONFIG_COMPAT
1431 .globl sys32_sigstack
1432 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1433 mov %i6, %o2
1434 .globl sys32_sigaltstack
1435 sys32_sigaltstack:
1436 ba,pt %xcc, do_sys32_sigaltstack
1437 mov %i6, %o2
1438 #endif
1439 .align 32
1440 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1441 call do_sigsuspend
1442 add %o7, 1f-.-4, %o7
1443 nop
1444 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1445 add %sp, PTREGS_OFF, %o2
1446 call do_rt_sigsuspend
1447 add %o7, 1f-.-4, %o7
1448 nop
1449 #ifdef CONFIG_COMPAT
1450 .globl sys32_rt_sigsuspend
1451 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1452 srl %o0, 0, %o0
1453 add %sp, PTREGS_OFF, %o2
1454 call do_rt_sigsuspend32
1455 add %o7, 1f-.-4, %o7
1456 #endif
1457 /* NOTE: %o0 has a correct value already */
1458 sys_sigpause: add %sp, PTREGS_OFF, %o1
1459 call do_sigpause
1460 add %o7, 1f-.-4, %o7
1461 nop
1462 #ifdef CONFIG_COMPAT
1463 .globl sys32_sigreturn
1464 sys32_sigreturn:
1465 add %sp, PTREGS_OFF, %o0
1466 call do_sigreturn32
1467 add %o7, 1f-.-4, %o7
1468 nop
1469 #endif
1470 sys_rt_sigreturn:
1471 add %sp, PTREGS_OFF, %o0
1472 call do_rt_sigreturn
1473 add %o7, 1f-.-4, %o7
1474 nop
1475 #ifdef CONFIG_COMPAT
1476 .globl sys32_rt_sigreturn
1477 sys32_rt_sigreturn:
1478 add %sp, PTREGS_OFF, %o0
1479 call do_rt_sigreturn32
1480 add %o7, 1f-.-4, %o7
1481 nop
1482 #endif
1483 sys_ptrace: add %sp, PTREGS_OFF, %o0
1484 call do_ptrace
1485 add %o7, 1f-.-4, %o7
1486 nop
1487 .align 32
1488 1: ldx [%curptr + TI_FLAGS], %l5
1489 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1490 be,pt %icc, rtrap
1491 clr %l6
1492 add %sp, PTREGS_OFF, %o0
1493 call syscall_trace
1494 mov 1, %o1
1495
1496 ba,pt %xcc, rtrap
1497 clr %l6
1498
1499 /* This is how fork() was meant to be done, 8 instruction entry.
1500 *
1501 * I questioned the following code briefly, let me clear things
1502 * up so you must not reason on it like I did.
1503 *
1504 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1505 * need it here because the only piece of window state we copy to
1506 * the child is the CWP register. Even if the parent sleeps,
1507 * we are safe because we stuck it into pt_regs of the parent
1508 * so it will not change.
1509 *
1510 * XXX This raises the question, whether we can do the same on
1511 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1512 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1513 * XXX fork_kwim in UREG_G1 (global registers are considered
1514 * XXX volatile across a system call in the sparc ABI I think
1515 * XXX if it isn't we can use regs->y instead, anyone who depends
1516 * XXX upon the Y register being preserved across a fork deserves
1517 * XXX to lose).
1518 *
1519 * In fact we should take advantage of that fact for other things
1520 * during system calls...
1521 */
1522 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1523 .globl ret_from_syscall
1524 .align 32
1525 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1526 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1527 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1528 ba,pt %xcc, sys_clone
1529 sys_fork: clr %o1
1530 mov SIGCHLD, %o0
1531 sys_clone: flushw
1532 movrz %o1, %fp, %o1
1533 mov 0, %o3
1534 ba,pt %xcc, sparc_do_fork
1535 add %sp, PTREGS_OFF, %o2
1536 ret_from_syscall:
1537 /* Clear current_thread_info()->new_child, and
1538 * check performance counter stuff too.
1539 */
1540 stb %g0, [%g6 + TI_NEW_CHILD]
1541 ldx [%g6 + TI_FLAGS], %l0
1542 call schedule_tail
1543 mov %g7, %o0
1544 andcc %l0, _TIF_PERFCTR, %g0
1545 be,pt %icc, 1f
1546 nop
1547 ldx [%g6 + TI_PCR], %o7
1548 wr %g0, %o7, %pcr
1549
1550 /* Blackbird errata workaround. See commentary in
1551 * smp.c:smp_percpu_timer_interrupt() for more
1552 * information.
1553 */
1554 ba,pt %xcc, 99f
1555 nop
1556 .align 64
1557 99: wr %g0, %g0, %pic
1558 rd %pic, %g0
1559
1560 1: b,pt %xcc, ret_sys_call
1561 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1562 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1563 rdpr %otherwin, %g1
1564 rdpr %cansave, %g3
1565 add %g3, %g1, %g3
1566 wrpr %g3, 0x0, %cansave
1567 wrpr %g0, 0x0, %otherwin
1568 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1569 ba,pt %xcc, sys_exit
1570 stb %g0, [%g6 + TI_WSAVED]
1571
1572 linux_sparc_ni_syscall:
1573 sethi %hi(sys_ni_syscall), %l7
1574 b,pt %xcc, 4f
1575 or %l7, %lo(sys_ni_syscall), %l7
1576
1577 linux_syscall_trace32:
1578 add %sp, PTREGS_OFF, %o0
1579 call syscall_trace
1580 clr %o1
1581 srl %i0, 0, %o0
1582 srl %i4, 0, %o4
1583 srl %i1, 0, %o1
1584 srl %i2, 0, %o2
1585 b,pt %xcc, 2f
1586 srl %i3, 0, %o3
1587
1588 linux_syscall_trace:
1589 add %sp, PTREGS_OFF, %o0
1590 call syscall_trace
1591 clr %o1
1592 mov %i0, %o0
1593 mov %i1, %o1
1594 mov %i2, %o2
1595 mov %i3, %o3
1596 b,pt %xcc, 2f
1597 mov %i4, %o4
1598
1599
1600 /* Linux 32-bit and SunOS system calls enter here... */
1601 .align 32
1602 .globl linux_sparc_syscall32
1603 linux_sparc_syscall32:
1604 /* Direct access to user regs, much faster. */
1605 cmp %g1, NR_SYSCALLS ! IEU1 Group
1606 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1607 srl %i0, 0, %o0 ! IEU0
1608 sll %g1, 2, %l4 ! IEU0 Group
1609 srl %i4, 0, %o4 ! IEU1
1610 lduw [%l7 + %l4], %l7 ! Load
1611 srl %i1, 0, %o1 ! IEU0 Group
1612 ldx [%curptr + TI_FLAGS], %l0 ! Load
1613
1614 srl %i5, 0, %o5 ! IEU1
1615 srl %i2, 0, %o2 ! IEU0 Group
1616 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1617 bne,pn %icc, linux_syscall_trace32 ! CTI
1618 mov %i0, %l5 ! IEU1
1619 call %l7 ! CTI Group brk forced
1620 srl %i3, 0, %o3 ! IEU0
1621 ba,a,pt %xcc, 3f
1622
1623 /* Linux native and SunOS system calls enter here... */
1624 .align 32
1625 .globl linux_sparc_syscall, ret_sys_call
1626 linux_sparc_syscall:
1627 /* Direct access to user regs, much faster. */
1628 cmp %g1, NR_SYSCALLS ! IEU1 Group
1629 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1630 mov %i0, %o0 ! IEU0
1631 sll %g1, 2, %l4 ! IEU0 Group
1632 mov %i1, %o1 ! IEU1
1633 lduw [%l7 + %l4], %l7 ! Load
1634 4: mov %i2, %o2 ! IEU0 Group
1635 ldx [%curptr + TI_FLAGS], %l0 ! Load
1636
1637 mov %i3, %o3 ! IEU1
1638 mov %i4, %o4 ! IEU0 Group
1639 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1640 bne,pn %icc, linux_syscall_trace ! CTI Group
1641 mov %i0, %l5 ! IEU0
1642 2: call %l7 ! CTI Group brk forced
1643 mov %i5, %o5 ! IEU0
1644 nop
1645
1646 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1647 ret_sys_call:
1648 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1649 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1650 sra %o0, 0, %o0
1651 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1652 sllx %g2, 32, %g2
1653
1654 /* Check if force_successful_syscall_return()
1655 * was invoked.
1656 */
1657 ldub [%curptr + TI_SYS_NOERROR], %l0
1658 brz,pt %l0, 1f
1659 nop
1660 ba,pt %xcc, 80f
1661 stb %g0, [%curptr + TI_SYS_NOERROR]
1662
1663 1:
1664 cmp %o0, -ERESTART_RESTARTBLOCK
1665 bgeu,pn %xcc, 1f
1666 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1667 80:
1668 /* System call success, clear Carry condition code. */
1669 andn %g3, %g2, %g3
1670 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1671 bne,pn %icc, linux_syscall_trace2
1672 add %l1, 0x4, %l2 ! npc = npc+4
1673 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1674 ba,pt %xcc, rtrap_clr_l6
1675 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1676
1677 1:
1678 /* System call failure, set Carry condition code.
1679 * Also, get abs(errno) to return to the process.
1680 */
1681 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1682 sub %g0, %o0, %o0
1683 or %g3, %g2, %g3
1684 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1685 mov 1, %l6
1686 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1687 bne,pn %icc, linux_syscall_trace2
1688 add %l1, 0x4, %l2 ! npc = npc+4
1689 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1690
1691 b,pt %xcc, rtrap
1692 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1693 linux_syscall_trace2:
1694 add %sp, PTREGS_OFF, %o0
1695 call syscall_trace
1696 mov 1, %o1
1697 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1698 ba,pt %xcc, rtrap
1699 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1700
1701 .align 32
1702 .globl __flushw_user
1703 __flushw_user:
1704 rdpr %otherwin, %g1
1705 brz,pn %g1, 2f
1706 clr %g2
1707 1: save %sp, -128, %sp
1708 rdpr %otherwin, %g1
1709 brnz,pt %g1, 1b
1710 add %g2, 1, %g2
1711 1: sub %g2, 1, %g2
1712 brnz,pt %g2, 1b
1713 restore %g0, %g0, %g0
1714 2: retl
1715 nop
Linux kernel - Deliverables
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