arch/sparc64/kernel/etrap.S

   1 /* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
   2  * etrap.S: Preparing for entry into the kernel on Sparc V9.
   3  *
   4  * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/config.h>
   9
  10 #include <asm/asi.h>
  11 #include <asm/pstate.h>
  12 #include <asm/ptrace.h>
  13 #include <asm/page.h>
  14 #include <asm/spitfire.h>
  15 #include <asm/head.h>
  16 #include <asm/processor.h>
  17 #include <asm/mmu.h>
  18
  19 #define         TASK_REGOFF             (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
  20 #define         ETRAP_PSTATE1           (PSTATE_RMO | PSTATE_PRIV)
  21 #define         ETRAP_PSTATE2           \
  22                 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
  23
  24 /*
  25  * On entry, %g7 is return address - 0x4.
  26  * %g4 and %g5 will be preserved %l4 and %l5 respectively.
  27  */
  28
  29                 .text
  30                 .align  64
  31                 .globl  etrap, etrap_irq, etraptl1
  32 etrap:          rdpr    %pil, %g2
  33 etrap_irq:
  34                 TRAP_LOAD_THREAD_REG(%g6, %g1)
  35                 rdpr    %tstate, %g1
  36                 sllx    %g2, 20, %g3
  37                 andcc   %g1, TSTATE_PRIV, %g0
  38                 or      %g1, %g3, %g1
  39                 bne,pn  %xcc, 1f
  40                  sub    %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
  41                 wrpr    %g0, 7, %cleanwin
  42
  43                 sethi   %hi(TASK_REGOFF), %g2
  44                 sethi   %hi(TSTATE_PEF), %g3
  45                 or      %g2, %lo(TASK_REGOFF), %g2
  46                 and     %g1, %g3, %g3
  47                 brnz,pn %g3, 1f
  48                  add    %g6, %g2, %g2
  49                 wr      %g0, 0, %fprs
  50 1:              rdpr    %tpc, %g3
  51
  52                 stx     %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
  53                 rdpr    %tnpc, %g1
  54                 stx     %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
  55                 rd      %y, %g3
  56                 stx     %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
  57                 st      %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
  58
  59                 rdpr    %cansave, %g1
  60                 brnz,pt %g1, etrap_save
  61                  nop
  62
  63                 rdpr    %cwp, %g1
  64                 add     %g1, 2, %g1
  65                 wrpr    %g1, %cwp
  66                 be,pt   %xcc, etrap_user_spill
  67                  mov    ASI_AIUP, %g3
  68
  69                 rdpr    %otherwin, %g3
  70                 brz     %g3, etrap_kernel_spill
  71                  mov    ASI_AIUS, %g3
  72
  73 etrap_user_spill:
  74
  75                 wr      %g3, 0x0, %asi
  76                 ldx     [%g6 + TI_FLAGS], %g3
  77                 and     %g3, _TIF_32BIT, %g3
  78                 brnz,pt %g3, etrap_user_spill_32bit
  79                  nop
  80                 ba,a,pt %xcc, etrap_user_spill_64bit
  81
  82 etrap_save:     save    %g2, -STACK_BIAS, %sp
  83                 mov     %g6, %l6
  84
  85                 bne,pn  %xcc, 3f
  86                  mov    PRIMARY_CONTEXT, %l4
  87                 rdpr    %canrestore, %g3
  88                 rdpr    %wstate, %g2
  89                 wrpr    %g0, 0, %canrestore
  90                 sll     %g2, 3, %g2
  91                 mov     1, %l5
  92                 stb     %l5, [%l6 + TI_FPDEPTH]
  93
  94                 wrpr    %g3, 0, %otherwin
  95                 wrpr    %g2, 0, %wstate
  96                 sethi   %hi(sparc64_kern_pri_context), %g2
  97                 ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g3
  98                 stxa    %g3, [%l4] ASI_DMMU
  99                 sethi   %hi(KERNBASE), %l4
 100                 flush   %l4
 101                 mov     ASI_AIUS, %l7
 102 2:              mov     %g4, %l4
 103                 mov     %g5, %l5
 104                 add     %g7, 4, %l2
 105
 106                 /* Go to trap time globals so we can save them.  */
 107 661:            wrpr    %g0, ETRAP_PSTATE1, %pstate
 108                 .section .gl_1insn_patch, "ax"
 109                 .word   661b
 110                 SET_GL(0)
 111                 .previous
 112
 113                 stx     %g1, [%sp + PTREGS_OFF + PT_V9_G1]
 114                 stx     %g2, [%sp + PTREGS_OFF + PT_V9_G2]
 115                 sllx    %l7, 24, %l7
 116                 stx     %g3, [%sp + PTREGS_OFF + PT_V9_G3]
 117                 rdpr    %cwp, %l0
 118                 stx     %g4, [%sp + PTREGS_OFF + PT_V9_G4]
 119                 stx     %g5, [%sp + PTREGS_OFF + PT_V9_G5]
 120                 stx     %g6, [%sp + PTREGS_OFF + PT_V9_G6]
 121                 stx     %g7, [%sp + PTREGS_OFF + PT_V9_G7]
 122                 or      %l7, %l0, %l7
 123                 sethi   %hi(TSTATE_RMO | TSTATE_PEF), %l0
 124                 or      %l7, %l0, %l7
 125                 wrpr    %l2, %tnpc
 126                 wrpr    %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
 127                 stx     %i0, [%sp + PTREGS_OFF + PT_V9_I0]
 128                 stx     %i1, [%sp + PTREGS_OFF + PT_V9_I1]
 129                 stx     %i2, [%sp + PTREGS_OFF + PT_V9_I2]
 130                 stx     %i3, [%sp + PTREGS_OFF + PT_V9_I3]
 131                 stx     %i4, [%sp + PTREGS_OFF + PT_V9_I4]
 132                 stx     %i5, [%sp + PTREGS_OFF + PT_V9_I5]
 133                 stx     %i6, [%sp + PTREGS_OFF + PT_V9_I6]
 134                 mov     %l6, %g6
 135                 stx     %i7, [%sp + PTREGS_OFF + PT_V9_I7]
 136                 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
 137                 ldx     [%g6 + TI_TASK], %g4
 138                 done
 139
 140 3:              mov     ASI_P, %l7
 141                 ldub    [%l6 + TI_FPDEPTH], %l5
 142                 add     %l6, TI_FPSAVED + 1, %l4
 143                 srl     %l5, 1, %l3
 144                 add     %l5, 2, %l5
 145                 stb     %l5, [%l6 + TI_FPDEPTH]
 146                 ba,pt   %xcc, 2b
 147                  stb    %g0, [%l4 + %l3]
 148                 nop
 149
 150 etraptl1:       /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
 151                  * We place this right after pt_regs on the trap stack.
 152                  * The layout is:
 153                  *      0x00    TL1's TSTATE
 154                  *      0x08    TL1's TPC
 155                  *      0x10    TL1's TNPC
 156                  *      0x18    TL1's TT
 157                  *       ...
 158                  *      0x58    TL4's TT
 159                  *      0x60    TL
 160                  */
 161                 TRAP_LOAD_THREAD_REG(%g6, %g1)
 162                 sub     %sp, ((4 * 8) * 4) + 8, %g2
 163                 rdpr    %tl, %g1
 164
 165                 wrpr    %g0, 1, %tl
 166                 rdpr    %tstate, %g3
 167                 stx     %g3, [%g2 + STACK_BIAS + 0x00]
 168                 rdpr    %tpc, %g3
 169                 stx     %g3, [%g2 + STACK_BIAS + 0x08]
 170                 rdpr    %tnpc, %g3
 171                 stx     %g3, [%g2 + STACK_BIAS + 0x10]
 172                 rdpr    %tt, %g3
 173                 stx     %g3, [%g2 + STACK_BIAS + 0x18]
 174
 175                 wrpr    %g0, 2, %tl
 176                 rdpr    %tstate, %g3
 177                 stx     %g3, [%g2 + STACK_BIAS + 0x20]
 178                 rdpr    %tpc, %g3
 179                 stx     %g3, [%g2 + STACK_BIAS + 0x28]
 180                 rdpr    %tnpc, %g3
 181                 stx     %g3, [%g2 + STACK_BIAS + 0x30]
 182                 rdpr    %tt, %g3
 183                 stx     %g3, [%g2 + STACK_BIAS + 0x38]
 184
 185                 wrpr    %g0, 3, %tl
 186                 rdpr    %tstate, %g3
 187                 stx     %g3, [%g2 + STACK_BIAS + 0x40]
 188                 rdpr    %tpc, %g3
 189                 stx     %g3, [%g2 + STACK_BIAS + 0x48]
 190                 rdpr    %tnpc, %g3
 191                 stx     %g3, [%g2 + STACK_BIAS + 0x50]
 192                 rdpr    %tt, %g3
 193                 stx     %g3, [%g2 + STACK_BIAS + 0x58]
 194
 195                 wrpr    %g0, 4, %tl
 196                 rdpr    %tstate, %g3
 197                 stx     %g3, [%g2 + STACK_BIAS + 0x60]
 198                 rdpr    %tpc, %g3
 199                 stx     %g3, [%g2 + STACK_BIAS + 0x68]
 200                 rdpr    %tnpc, %g3
 201                 stx     %g3, [%g2 + STACK_BIAS + 0x70]
 202                 rdpr    %tt, %g3
 203                 stx     %g3, [%g2 + STACK_BIAS + 0x78]
 204
 205                 stx     %g1, [%g2 + STACK_BIAS + 0x80]
 206
 207                 wrpr    %g0, 1, %tl
 208 661:            nop
 209                 .section .gl_1insn_patch, "ax"
 210                 .word   661b
 211                 SET_GL(1)
 212                 .previous
 213
 214                 rdpr    %tstate, %g1
 215                 sub     %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
 216                 ba,pt   %xcc, 1b
 217                  andcc  %g1, TSTATE_PRIV, %g0
 218
 219 #undef TASK_REGOFF
 220 #undef ETRAP_PSTATE1