arch/sparc64/kernel/etrap.S

   1 /* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
   2  * etrap.S: Preparing for entry into the kernel on Sparc V9.
   3  *
   4  * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/config.h>
   9
  10 #include <asm/asi.h>
  11 #include <asm/pstate.h>
  12 #include <asm/ptrace.h>
  13 #include <asm/page.h>
  14 #include <asm/spitfire.h>
  15 #include <asm/head.h>
  16 #include <asm/processor.h>
  17 #include <asm/mmu.h>
  18
  19 #define         TASK_REGOFF             (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
  20 #define         ETRAP_PSTATE1           (PSTATE_RMO | PSTATE_PRIV)
  21 #define         ETRAP_PSTATE2           \
  22                 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
  23
  24 /*
  25  * On entry, %g7 is return address - 0x4.
  26  * %g4 and %g5 will be preserved %l4 and %l5 respectively.
  27  */
  28
  29                 .text
  30                 .align  64
  31                 .globl  etrap, etrap_irq, etraptl1
  32 etrap:          rdpr    %pil, %g2
  33 etrap_irq:
  34                 rdpr    %tstate, %g1
  35                 sllx    %g2, 20, %g3
  36                 andcc   %g1, TSTATE_PRIV, %g0
  37                 or      %g1, %g3, %g1
  38                 bne,pn  %xcc, 1f
  39                  sub    %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
  40                 wrpr    %g0, 7, %cleanwin
  41
  42                 sethi   %hi(TASK_REGOFF), %g2
  43                 sethi   %hi(TSTATE_PEF), %g3
  44                 or      %g2, %lo(TASK_REGOFF), %g2
  45                 and     %g1, %g3, %g3
  46                 brnz,pn %g3, 1f
  47                  add    %g6, %g2, %g2
  48                 wr      %g0, 0, %fprs
  49 1:              rdpr    %tpc, %g3
  50
  51                 stx     %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
  52                 rdpr    %tnpc, %g1
  53                 stx     %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
  54                 rd      %y, %g3
  55                 stx     %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
  56                 st      %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
  57                 save    %g2, -STACK_BIAS, %sp   ! Ordering here is critical
  58                 mov     %g6, %l6
  59
  60                 bne,pn  %xcc, 3f
  61                  mov    PRIMARY_CONTEXT, %l4
  62                 rdpr    %canrestore, %g3
  63                 rdpr    %wstate, %g2
  64                 wrpr    %g0, 0, %canrestore
  65                 sll     %g2, 3, %g2
  66                 mov     1, %l5
  67                 stb     %l5, [%l6 + TI_FPDEPTH]
  68
  69                 wrpr    %g3, 0, %otherwin
  70                 wrpr    %g2, 0, %wstate
  71                 sethi   %hi(sparc64_kern_pri_context), %g2
  72                 ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g3
  73                 stxa    %g3, [%l4] ASI_DMMU
  74                 flush   %l6
  75                 wr      %g0, ASI_AIUS, %asi
  76 2:              wrpr    %g0, 0x0, %tl
  77                 mov     %g4, %l4
  78                 mov     %g5, %l5
  79
  80                 mov     %g7, %l2
  81                 wrpr    %g0, ETRAP_PSTATE1, %pstate
  82                 stx     %g1, [%sp + PTREGS_OFF + PT_V9_G1]
  83                 stx     %g2, [%sp + PTREGS_OFF + PT_V9_G2]
  84                 stx     %g3, [%sp + PTREGS_OFF + PT_V9_G3]
  85                 stx     %g4, [%sp + PTREGS_OFF + PT_V9_G4]
  86                 stx     %g5, [%sp + PTREGS_OFF + PT_V9_G5]
  87                 stx     %g6, [%sp + PTREGS_OFF + PT_V9_G6]
  88
  89                 stx     %g7, [%sp + PTREGS_OFF + PT_V9_G7]
  90                 stx     %i0, [%sp + PTREGS_OFF + PT_V9_I0]
  91                 stx     %i1, [%sp + PTREGS_OFF + PT_V9_I1]
  92                 stx     %i2, [%sp + PTREGS_OFF + PT_V9_I2]
  93                 stx     %i3, [%sp + PTREGS_OFF + PT_V9_I3]
  94                 stx     %i4, [%sp + PTREGS_OFF + PT_V9_I4]
  95                 stx     %i5, [%sp + PTREGS_OFF + PT_V9_I5]
  96
  97                 stx     %i6, [%sp + PTREGS_OFF + PT_V9_I6]
  98                 stx     %i7, [%sp + PTREGS_OFF + PT_V9_I7]
  99                 wrpr    %g0, ETRAP_PSTATE2, %pstate
 100                 mov     %l6, %g6
 101 #ifdef CONFIG_SMP
 102 #error IMMU TSB usage must be fixed
 103                 mov     TSB_REG, %g3
 104                 ldxa    [%g3] ASI_IMMU, %g5
 105 #endif
 106                 jmpl    %l2 + 0x4, %g0
 107                  ldx    [%g6 + TI_TASK], %g4
 108
 109 3:              ldub    [%l6 + TI_FPDEPTH], %l5
 110                 add     %l6, TI_FPSAVED + 1, %l4
 111                 srl     %l5, 1, %l3
 112                 add     %l5, 2, %l5
 113                 stb     %l5, [%l6 + TI_FPDEPTH]
 114                 ba,pt   %xcc, 2b
 115                  stb    %g0, [%l4 + %l3]
 116                 nop
 117
 118 etraptl1:       /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
 119                  * We place this right after pt_regs on the trap stack.
 120                  * The layout is:
 121                  *      0x00    TL1's TSTATE
 122                  *      0x08    TL1's TPC
 123                  *      0x10    TL1's TNPC
 124                  *      0x18    TL1's TT
 125                  *       ...
 126                  *      0x58    TL4's TT
 127                  *      0x60    TL
 128                  */
 129                 sub     %sp, ((4 * 8) * 4) + 8, %g2
 130                 rdpr    %tl, %g1
 131
 132                 wrpr    %g0, 1, %tl
 133                 rdpr    %tstate, %g3
 134                 stx     %g3, [%g2 + STACK_BIAS + 0x00]
 135                 rdpr    %tpc, %g3
 136                 stx     %g3, [%g2 + STACK_BIAS + 0x08]
 137                 rdpr    %tnpc, %g3
 138                 stx     %g3, [%g2 + STACK_BIAS + 0x10]
 139                 rdpr    %tt, %g3
 140                 stx     %g3, [%g2 + STACK_BIAS + 0x18]
 141
 142                 wrpr    %g0, 2, %tl
 143                 rdpr    %tstate, %g3
 144                 stx     %g3, [%g2 + STACK_BIAS + 0x20]
 145                 rdpr    %tpc, %g3
 146                 stx     %g3, [%g2 + STACK_BIAS + 0x28]
 147                 rdpr    %tnpc, %g3
 148                 stx     %g3, [%g2 + STACK_BIAS + 0x30]
 149                 rdpr    %tt, %g3
 150                 stx     %g3, [%g2 + STACK_BIAS + 0x38]
 151
 152                 wrpr    %g0, 3, %tl
 153                 rdpr    %tstate, %g3
 154                 stx     %g3, [%g2 + STACK_BIAS + 0x40]
 155                 rdpr    %tpc, %g3
 156                 stx     %g3, [%g2 + STACK_BIAS + 0x48]
 157                 rdpr    %tnpc, %g3
 158                 stx     %g3, [%g2 + STACK_BIAS + 0x50]
 159                 rdpr    %tt, %g3
 160                 stx     %g3, [%g2 + STACK_BIAS + 0x58]
 161
 162                 wrpr    %g0, 4, %tl
 163                 rdpr    %tstate, %g3
 164                 stx     %g3, [%g2 + STACK_BIAS + 0x60]
 165                 rdpr    %tpc, %g3
 166                 stx     %g3, [%g2 + STACK_BIAS + 0x68]
 167                 rdpr    %tnpc, %g3
 168                 stx     %g3, [%g2 + STACK_BIAS + 0x70]
 169                 rdpr    %tt, %g3
 170                 stx     %g3, [%g2 + STACK_BIAS + 0x78]
 171
 172                 wrpr    %g1, %tl
 173                 stx     %g1, [%g2 + STACK_BIAS + 0x80]
 174
 175                 rdpr    %tstate, %g1
 176                 sub     %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
 177                 ba,pt   %xcc, 1b
 178                  andcc  %g1, TSTATE_PRIV, %g0
 179
 180                 .align  64
 181                 .globl  scetrap
 182 scetrap:        rdpr    %pil, %g2
 183                 rdpr    %tstate, %g1
 184                 sllx    %g2, 20, %g3
 185                 andcc   %g1, TSTATE_PRIV, %g0
 186                 or      %g1, %g3, %g1
 187                 bne,pn  %xcc, 1f
 188                  sub    %sp, (STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS), %g2
 189                 wrpr    %g0, 7, %cleanwin
 190
 191                 sllx    %g1, 51, %g3
 192                 sethi   %hi(TASK_REGOFF), %g2
 193                 or      %g2, %lo(TASK_REGOFF), %g2
 194                 brlz,pn %g3, 1f
 195                  add    %g6, %g2, %g2
 196                 wr      %g0, 0, %fprs
 197 1:              rdpr    %tpc, %g3
 198                 stx     %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
 199
 200                 rdpr    %tnpc, %g1
 201                 stx     %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
 202                 stx     %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
 203                 save    %g2, -STACK_BIAS, %sp   ! Ordering here is critical
 204                 mov     %g6, %l6
 205                 bne,pn  %xcc, 2f
 206                  mov    ASI_P, %l7
 207                 rdpr    %canrestore, %g3
 208
 209                 rdpr    %wstate, %g2
 210                 wrpr    %g0, 0, %canrestore
 211                 sll     %g2, 3, %g2
 212                 mov     PRIMARY_CONTEXT, %l4
 213                 wrpr    %g3, 0, %otherwin
 214                 wrpr    %g2, 0, %wstate
 215                 sethi   %hi(sparc64_kern_pri_context), %g2
 216                 ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g3
 217                 stxa    %g3, [%l4] ASI_DMMU
 218                 flush   %l6
 219
 220                 mov     ASI_AIUS, %l7
 221 2:              mov     %g4, %l4
 222                 mov     %g5, %l5
 223                 add     %g7, 0x4, %l2
 224                 wrpr    %g0, ETRAP_PSTATE1, %pstate
 225                 stx     %g1, [%sp + PTREGS_OFF + PT_V9_G1]
 226                 stx     %g2, [%sp + PTREGS_OFF + PT_V9_G2]
 227                 sllx    %l7, 24, %l7
 228
 229                 stx     %g3, [%sp + PTREGS_OFF + PT_V9_G3]
 230                 rdpr    %cwp, %l0
 231                 stx     %g4, [%sp + PTREGS_OFF + PT_V9_G4]
 232                 stx     %g5, [%sp + PTREGS_OFF + PT_V9_G5]
 233                 stx     %g6, [%sp + PTREGS_OFF + PT_V9_G6]
 234                 stx     %g7, [%sp + PTREGS_OFF + PT_V9_G7]
 235                 or      %l7, %l0, %l7
 236                 sethi   %hi(TSTATE_RMO | TSTATE_PEF), %l0
 237
 238                 or      %l7, %l0, %l7
 239                 wrpr    %l2, %tnpc
 240                 wrpr    %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
 241                 stx     %i0, [%sp + PTREGS_OFF + PT_V9_I0]
 242                 stx     %i1, [%sp + PTREGS_OFF + PT_V9_I1]
 243                 stx     %i2, [%sp + PTREGS_OFF + PT_V9_I2]
 244                 stx     %i3, [%sp + PTREGS_OFF + PT_V9_I3]
 245                 stx     %i4, [%sp + PTREGS_OFF + PT_V9_I4]
 246
 247                 stx     %i5, [%sp + PTREGS_OFF + PT_V9_I5]
 248                 stx     %i6, [%sp + PTREGS_OFF + PT_V9_I6]
 249                 mov     %l6, %g6
 250                 stx     %i7, [%sp + PTREGS_OFF + PT_V9_I7]
 251 #ifdef CONFIG_SMP
 252 #error IMMU TSB usage must be fixed
 253                 mov     TSB_REG, %g3
 254                 ldxa    [%g3] ASI_IMMU, %g5
 255 #endif
 256                 ldx     [%g6 + TI_TASK], %g4
 257                 done
 258
 259 #undef TASK_REGOFF
 260 #undef ETRAP_PSTATE1