1 /* irq.c: UltraSparc IRQ handling/init/registry.
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/module.h>
9 #include <linux/sched.h>
10 #include <linux/ptrace.h>
11 #include <linux/errno.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/signal.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/random.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/proc_fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/bootmem.h>
23 #include <linux/irq.h>
24 #include <linux/msi.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
33 #include <asm/iommu.h>
35 #include <asm/oplib.h>
37 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/uaccess.h>
41 #include <asm/cache.h>
42 #include <asm/cpudata.h>
43 #include <asm/auxio.h>
45 #include <asm/hypervisor.h>
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 * The IVEC handler does not need to act atomically, the PIL dispatch
56 * code uses CAS to get an atomic snapshot of the list and clear it
59 * If you make changes to ino_bucket, please update hand coded assembler
60 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
63 /* Next handler in per-CPU IRQ worklist. We know that
64 * bucket pointers have the high 32-bits clear, so to
65 * save space we only store the bits we need.
67 /*0x00*/unsigned int irq_chain
;
69 /* Virtual interrupt number assigned to this INO. */
70 /*0x04*/unsigned int virt_irq
;
73 #define NUM_IVECS (IMAP_INR + 1)
74 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
76 #define __irq_ino(irq) \
77 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
78 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
79 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
81 /* This has to be in the main kernel image, it cannot be
82 * turned into per-cpu data. The reason is that the main
83 * kernel image is locked into the TLB and this structure
84 * is accessed from the vectored interrupt trap handler. If
85 * access to this structure takes a TLB miss it could cause
86 * the 5-level sparc v9 trap stack to overflow.
88 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
90 static unsigned int virt_to_real_irq_table
[NR_IRQS
];
92 static unsigned char virt_irq_alloc(unsigned int real_irq
)
96 BUILD_BUG_ON(NR_IRQS
>= 256);
98 for (ent
= 1; ent
< NR_IRQS
; ent
++) {
99 if (!virt_to_real_irq_table
[ent
])
102 if (ent
>= NR_IRQS
) {
103 printk(KERN_ERR
"IRQ: Out of virtual IRQs.\n");
107 virt_to_real_irq_table
[ent
] = real_irq
;
112 #ifdef CONFIG_PCI_MSI
113 static void virt_irq_free(unsigned int virt_irq
)
115 unsigned int real_irq
;
117 if (virt_irq
>= NR_IRQS
)
120 real_irq
= virt_to_real_irq_table
[virt_irq
];
121 virt_to_real_irq_table
[virt_irq
] = 0;
123 __bucket(real_irq
)->virt_irq
= 0;
127 static unsigned int virt_to_real_irq(unsigned char virt_irq
)
129 return virt_to_real_irq_table
[virt_irq
];
133 * /proc/interrupts printing:
136 int show_interrupts(struct seq_file
*p
, void *v
)
138 int i
= *(loff_t
*) v
, j
;
139 struct irqaction
* action
;
144 for_each_online_cpu(j
)
145 seq_printf(p
, "CPU%d ",j
);
150 spin_lock_irqsave(&irq_desc
[i
].lock
, flags
);
151 action
= irq_desc
[i
].action
;
154 seq_printf(p
, "%3d: ",i
);
156 seq_printf(p
, "%10u ", kstat_irqs(i
));
158 for_each_online_cpu(j
)
159 seq_printf(p
, "%10u ", kstat_cpu(j
).irqs
[i
]);
161 seq_printf(p
, " %9s", irq_desc
[i
].chip
->typename
);
162 seq_printf(p
, " %s", action
->name
);
164 for (action
=action
->next
; action
; action
= action
->next
)
165 seq_printf(p
, ", %s", action
->name
);
169 spin_unlock_irqrestore(&irq_desc
[i
].lock
, flags
);
174 static unsigned int sun4u_compute_tid(unsigned long imap
, unsigned long cpuid
)
178 if (this_is_starfire
) {
179 tid
= starfire_translate(imap
, cpuid
);
180 tid
<<= IMAP_TID_SHIFT
;
183 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
186 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
187 if ((ver
>> 32UL) == __JALAPENO_ID
||
188 (ver
>> 32UL) == __SERRANO_ID
) {
189 tid
= cpuid
<< IMAP_TID_SHIFT
;
190 tid
&= IMAP_TID_JBUS
;
192 unsigned int a
= cpuid
& 0x1f;
193 unsigned int n
= (cpuid
>> 5) & 0x1f;
195 tid
= ((a
<< IMAP_AID_SHIFT
) |
196 (n
<< IMAP_NID_SHIFT
));
197 tid
&= (IMAP_AID_SAFARI
|
201 tid
= cpuid
<< IMAP_TID_SHIFT
;
209 struct irq_handler_data
{
213 void (*pre_handler
)(unsigned int, void *, void *);
214 void *pre_handler_arg1
;
215 void *pre_handler_arg2
;
218 static inline struct ino_bucket
*virt_irq_to_bucket(unsigned int virt_irq
)
220 unsigned int real_irq
= virt_to_real_irq(virt_irq
);
221 struct ino_bucket
*bucket
= NULL
;
223 if (likely(real_irq
))
224 bucket
= __bucket(real_irq
);
230 static int irq_choose_cpu(unsigned int virt_irq
)
232 cpumask_t mask
= irq_desc
[virt_irq
].affinity
;
235 if (cpus_equal(mask
, CPU_MASK_ALL
)) {
236 static int irq_rover
;
237 static DEFINE_SPINLOCK(irq_rover_lock
);
240 /* Round-robin distribution... */
242 spin_lock_irqsave(&irq_rover_lock
, flags
);
244 while (!cpu_online(irq_rover
)) {
245 if (++irq_rover
>= NR_CPUS
)
250 if (++irq_rover
>= NR_CPUS
)
252 } while (!cpu_online(irq_rover
));
254 spin_unlock_irqrestore(&irq_rover_lock
, flags
);
258 cpus_and(tmp
, cpu_online_map
, mask
);
263 cpuid
= first_cpu(tmp
);
269 static int irq_choose_cpu(unsigned int virt_irq
)
271 return real_hard_smp_processor_id();
275 static void sun4u_irq_enable(unsigned int virt_irq
)
277 struct irq_handler_data
*data
= get_irq_chip_data(virt_irq
);
280 unsigned long cpuid
, imap
, val
;
283 cpuid
= irq_choose_cpu(virt_irq
);
286 tid
= sun4u_compute_tid(imap
, cpuid
);
288 val
= upa_readq(imap
);
289 val
&= ~(IMAP_TID_UPA
| IMAP_TID_JBUS
|
290 IMAP_AID_SAFARI
| IMAP_NID_SAFARI
);
291 val
|= tid
| IMAP_VALID
;
292 upa_writeq(val
, imap
);
296 static void sun4u_set_affinity(unsigned int virt_irq
, cpumask_t mask
)
298 sun4u_irq_enable(virt_irq
);
301 static void sun4u_irq_disable(unsigned int virt_irq
)
303 struct irq_handler_data
*data
= get_irq_chip_data(virt_irq
);
306 unsigned long imap
= data
->imap
;
307 u32 tmp
= upa_readq(imap
);
310 upa_writeq(tmp
, imap
);
314 static void sun4u_irq_end(unsigned int virt_irq
)
316 struct irq_handler_data
*data
= get_irq_chip_data(virt_irq
);
317 struct irq_desc
*desc
= irq_desc
+ virt_irq
;
319 if (unlikely(desc
->status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)))
323 upa_writeq(ICLR_IDLE
, data
->iclr
);
326 static void sun4v_irq_enable(unsigned int virt_irq
)
328 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
329 unsigned int ino
= bucket
- &ivector_table
[0];
331 if (likely(bucket
)) {
335 cpuid
= irq_choose_cpu(virt_irq
);
337 err
= sun4v_intr_settarget(ino
, cpuid
);
339 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
341 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
343 printk("sun4v_intr_setstate(%x): "
344 "err(%d)\n", ino
, err
);
345 err
= sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
347 printk("sun4v_intr_setenabled(%x): err(%d)\n",
352 static void sun4v_set_affinity(unsigned int virt_irq
, cpumask_t mask
)
354 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
355 unsigned int ino
= bucket
- &ivector_table
[0];
357 if (likely(bucket
)) {
361 cpuid
= irq_choose_cpu(virt_irq
);
363 err
= sun4v_intr_settarget(ino
, cpuid
);
365 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
370 static void sun4v_irq_disable(unsigned int virt_irq
)
372 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
373 unsigned int ino
= bucket
- &ivector_table
[0];
375 if (likely(bucket
)) {
378 err
= sun4v_intr_setenabled(ino
, HV_INTR_DISABLED
);
380 printk("sun4v_intr_setenabled(%x): "
381 "err(%d)\n", ino
, err
);
385 #ifdef CONFIG_PCI_MSI
386 static void sun4v_msi_enable(unsigned int virt_irq
)
388 sun4v_irq_enable(virt_irq
);
389 unmask_msi_irq(virt_irq
);
392 static void sun4v_msi_disable(unsigned int virt_irq
)
394 mask_msi_irq(virt_irq
);
395 sun4v_irq_disable(virt_irq
);
399 static void sun4v_irq_end(unsigned int virt_irq
)
401 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
402 unsigned int ino
= bucket
- &ivector_table
[0];
403 struct irq_desc
*desc
= irq_desc
+ virt_irq
;
405 if (unlikely(desc
->status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)))
408 if (likely(bucket
)) {
411 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
413 printk("sun4v_intr_setstate(%x): "
414 "err(%d)\n", ino
, err
);
418 static void sun4v_virq_enable(unsigned int virt_irq
)
420 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
421 unsigned int ino
= bucket
- &ivector_table
[0];
423 if (likely(bucket
)) {
424 unsigned long cpuid
, dev_handle
, dev_ino
;
427 cpuid
= irq_choose_cpu(virt_irq
);
429 dev_handle
= ino
& IMAP_IGN
;
430 dev_ino
= ino
& IMAP_INO
;
432 err
= sun4v_vintr_set_target(dev_handle
, dev_ino
, cpuid
);
434 printk("sun4v_vintr_set_target(%lx,%lx,%lu): "
436 dev_handle
, dev_ino
, cpuid
, err
);
437 err
= sun4v_vintr_set_state(dev_handle
, dev_ino
,
440 printk("sun4v_vintr_set_state(%lx,%lx,"
441 "HV_INTR_STATE_IDLE): err(%d)\n",
442 dev_handle
, dev_ino
, err
);
443 err
= sun4v_vintr_set_valid(dev_handle
, dev_ino
,
446 printk("sun4v_vintr_set_state(%lx,%lx,"
447 "HV_INTR_ENABLED): err(%d)\n",
448 dev_handle
, dev_ino
, err
);
452 static void sun4v_virt_set_affinity(unsigned int virt_irq
, cpumask_t mask
)
454 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
455 unsigned int ino
= bucket
- &ivector_table
[0];
457 if (likely(bucket
)) {
458 unsigned long cpuid
, dev_handle
, dev_ino
;
461 cpuid
= irq_choose_cpu(virt_irq
);
463 dev_handle
= ino
& IMAP_IGN
;
464 dev_ino
= ino
& IMAP_INO
;
466 err
= sun4v_vintr_set_target(dev_handle
, dev_ino
, cpuid
);
468 printk("sun4v_vintr_set_target(%lx,%lx,%lu): "
470 dev_handle
, dev_ino
, cpuid
, err
);
474 static void sun4v_virq_disable(unsigned int virt_irq
)
476 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
477 unsigned int ino
= bucket
- &ivector_table
[0];
479 if (likely(bucket
)) {
480 unsigned long dev_handle
, dev_ino
;
483 dev_handle
= ino
& IMAP_IGN
;
484 dev_ino
= ino
& IMAP_INO
;
486 err
= sun4v_vintr_set_valid(dev_handle
, dev_ino
,
489 printk("sun4v_vintr_set_state(%lx,%lx,"
490 "HV_INTR_DISABLED): err(%d)\n",
491 dev_handle
, dev_ino
, err
);
495 static void sun4v_virq_end(unsigned int virt_irq
)
497 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
498 unsigned int ino
= bucket
- &ivector_table
[0];
499 struct irq_desc
*desc
= irq_desc
+ virt_irq
;
501 if (unlikely(desc
->status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)))
504 if (likely(bucket
)) {
505 unsigned long dev_handle
, dev_ino
;
508 dev_handle
= ino
& IMAP_IGN
;
509 dev_ino
= ino
& IMAP_INO
;
511 err
= sun4v_vintr_set_state(dev_handle
, dev_ino
,
514 printk("sun4v_vintr_set_state(%lx,%lx,"
515 "HV_INTR_STATE_IDLE): err(%d)\n",
516 dev_handle
, dev_ino
, err
);
520 static void run_pre_handler(unsigned int virt_irq
)
522 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
523 struct irq_handler_data
*data
= get_irq_chip_data(virt_irq
);
525 if (likely(data
->pre_handler
)) {
526 data
->pre_handler(__irq_ino(__irq(bucket
)),
527 data
->pre_handler_arg1
,
528 data
->pre_handler_arg2
);
532 static struct irq_chip sun4u_irq
= {
534 .enable
= sun4u_irq_enable
,
535 .disable
= sun4u_irq_disable
,
536 .end
= sun4u_irq_end
,
537 .set_affinity
= sun4u_set_affinity
,
540 static struct irq_chip sun4u_irq_ack
= {
541 .typename
= "sun4u+ack",
542 .enable
= sun4u_irq_enable
,
543 .disable
= sun4u_irq_disable
,
544 .ack
= run_pre_handler
,
545 .end
= sun4u_irq_end
,
546 .set_affinity
= sun4u_set_affinity
,
549 static struct irq_chip sun4v_irq
= {
551 .enable
= sun4v_irq_enable
,
552 .disable
= sun4v_irq_disable
,
553 .end
= sun4v_irq_end
,
554 .set_affinity
= sun4v_set_affinity
,
557 static struct irq_chip sun4v_irq_ack
= {
558 .typename
= "sun4v+ack",
559 .enable
= sun4v_irq_enable
,
560 .disable
= sun4v_irq_disable
,
561 .ack
= run_pre_handler
,
562 .end
= sun4v_irq_end
,
563 .set_affinity
= sun4v_set_affinity
,
566 #ifdef CONFIG_PCI_MSI
567 static struct irq_chip sun4v_msi
= {
568 .typename
= "sun4v+msi",
569 .mask
= mask_msi_irq
,
570 .unmask
= unmask_msi_irq
,
571 .enable
= sun4v_msi_enable
,
572 .disable
= sun4v_msi_disable
,
573 .ack
= run_pre_handler
,
574 .end
= sun4v_irq_end
,
575 .set_affinity
= sun4v_set_affinity
,
579 static struct irq_chip sun4v_virq
= {
580 .typename
= "vsun4v",
581 .enable
= sun4v_virq_enable
,
582 .disable
= sun4v_virq_disable
,
583 .end
= sun4v_virq_end
,
584 .set_affinity
= sun4v_virt_set_affinity
,
587 static struct irq_chip sun4v_virq_ack
= {
588 .typename
= "vsun4v+ack",
589 .enable
= sun4v_virq_enable
,
590 .disable
= sun4v_virq_disable
,
591 .ack
= run_pre_handler
,
592 .end
= sun4v_virq_end
,
593 .set_affinity
= sun4v_virt_set_affinity
,
596 void irq_install_pre_handler(int virt_irq
,
597 void (*func
)(unsigned int, void *, void *),
598 void *arg1
, void *arg2
)
600 struct irq_handler_data
*data
= get_irq_chip_data(virt_irq
);
601 struct irq_chip
*chip
;
603 data
->pre_handler
= func
;
604 data
->pre_handler_arg1
= arg1
;
605 data
->pre_handler_arg2
= arg2
;
607 chip
= get_irq_chip(virt_irq
);
608 if (chip
== &sun4u_irq_ack
||
609 chip
== &sun4v_irq_ack
||
610 chip
== &sun4v_virq_ack
611 #ifdef CONFIG_PCI_MSI
612 || chip
== &sun4v_msi
617 chip
= (chip
== &sun4u_irq
?
619 (chip
== &sun4v_irq
?
620 &sun4v_irq_ack
: &sun4v_virq_ack
));
621 set_irq_chip(virt_irq
, chip
);
624 unsigned int build_irq(int inofixup
, unsigned long iclr
, unsigned long imap
)
626 struct ino_bucket
*bucket
;
627 struct irq_handler_data
*data
;
630 BUG_ON(tlb_type
== hypervisor
);
632 ino
= (upa_readq(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
633 bucket
= &ivector_table
[ino
];
634 if (!bucket
->virt_irq
) {
635 bucket
->virt_irq
= virt_irq_alloc(__irq(bucket
));
636 set_irq_chip(bucket
->virt_irq
, &sun4u_irq
);
639 data
= get_irq_chip_data(bucket
->virt_irq
);
643 data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
644 if (unlikely(!data
)) {
645 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
648 set_irq_chip_data(bucket
->virt_irq
, data
);
654 return bucket
->virt_irq
;
657 static unsigned int sun4v_build_common(unsigned long sysino
,
658 struct irq_chip
*chip
)
660 struct ino_bucket
*bucket
;
661 struct irq_handler_data
*data
;
663 BUG_ON(tlb_type
!= hypervisor
);
665 bucket
= &ivector_table
[sysino
];
666 if (!bucket
->virt_irq
) {
667 bucket
->virt_irq
= virt_irq_alloc(__irq(bucket
));
668 set_irq_chip(bucket
->virt_irq
, chip
);
671 data
= get_irq_chip_data(bucket
->virt_irq
);
675 data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
676 if (unlikely(!data
)) {
677 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
680 set_irq_chip_data(bucket
->virt_irq
, data
);
682 /* Catch accidental accesses to these things. IMAP/ICLR handling
683 * is done by hypervisor calls on sun4v platforms, not by direct
690 return bucket
->virt_irq
;
693 unsigned int sun4v_build_irq(u32 devhandle
, unsigned int devino
)
695 unsigned long sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
697 return sun4v_build_common(sysino
, &sun4v_irq
);
700 unsigned int sun4v_build_virq(u32 devhandle
, unsigned int devino
)
702 unsigned long sysino
, hv_err
;
704 BUG_ON(devhandle
& ~IMAP_IGN
);
705 BUG_ON(devino
& ~IMAP_INO
);
707 sysino
= devhandle
| devino
;
709 hv_err
= sun4v_vintr_set_cookie(devhandle
, devino
, sysino
);
711 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
712 "err=%lu\n", devhandle
, devino
, hv_err
);
716 return sun4v_build_common(sysino
, &sun4v_virq
);
719 #ifdef CONFIG_PCI_MSI
720 unsigned int sun4v_build_msi(u32 devhandle
, unsigned int *virt_irq_p
,
721 unsigned int msi_start
, unsigned int msi_end
)
723 struct ino_bucket
*bucket
;
724 struct irq_handler_data
*data
;
725 unsigned long sysino
;
728 BUG_ON(tlb_type
!= hypervisor
);
730 /* Find a free devino in the given range. */
731 for (devino
= msi_start
; devino
< msi_end
; devino
++) {
732 sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
733 bucket
= &ivector_table
[sysino
];
734 if (!bucket
->virt_irq
)
737 if (devino
>= msi_end
)
740 sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
741 bucket
= &ivector_table
[sysino
];
742 bucket
->virt_irq
= virt_irq_alloc(__irq(bucket
));
743 *virt_irq_p
= bucket
->virt_irq
;
744 set_irq_chip(bucket
->virt_irq
, &sun4v_msi
);
746 data
= get_irq_chip_data(bucket
->virt_irq
);
750 data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
751 if (unlikely(!data
)) {
752 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
755 set_irq_chip_data(bucket
->virt_irq
, data
);
763 void sun4v_destroy_msi(unsigned int virt_irq
)
765 virt_irq_free(virt_irq
);
769 void ack_bad_irq(unsigned int virt_irq
)
771 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
772 unsigned int ino
= 0xdeadbeef;
775 ino
= bucket
- &ivector_table
[0];
777 printk(KERN_CRIT
"Unexpected IRQ from ino[%x] virt_irq[%u]\n",
781 void handler_irq(int irq
, struct pt_regs
*regs
)
783 struct ino_bucket
*bucket
;
784 struct pt_regs
*old_regs
;
786 clear_softint(1 << irq
);
788 old_regs
= set_irq_regs(regs
);
792 bucket
= __bucket(xchg32(irq_work(smp_processor_id()), 0));
794 struct ino_bucket
*next
= __bucket(bucket
->irq_chain
);
796 bucket
->irq_chain
= 0;
797 __do_IRQ(bucket
->virt_irq
);
803 set_irq_regs(old_regs
);
806 #ifdef CONFIG_HOTPLUG_CPU
807 void fixup_irqs(void)
811 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
814 spin_lock_irqsave(&irq_desc
[irq
].lock
, flags
);
815 if (irq_desc
[irq
].action
&&
816 !(irq_desc
[irq
].status
& IRQ_PER_CPU
)) {
817 if (irq_desc
[irq
].chip
->set_affinity
)
818 irq_desc
[irq
].chip
->set_affinity(irq
,
819 irq_desc
[irq
].affinity
);
821 spin_unlock_irqrestore(&irq_desc
[irq
].lock
, flags
);
833 static struct sun5_timer
*prom_timers
;
834 static u64 prom_limit0
, prom_limit1
;
836 static void map_prom_timers(void)
838 struct device_node
*dp
;
839 const unsigned int *addr
;
841 /* PROM timer node hangs out in the top level of device siblings... */
842 dp
= of_find_node_by_path("/");
845 if (!strcmp(dp
->name
, "counter-timer"))
850 /* Assume if node is not present, PROM uses different tick mechanism
851 * which we should not care about.
854 prom_timers
= (struct sun5_timer
*) 0;
858 /* If PROM is really using this, it must be mapped by him. */
859 addr
= of_get_property(dp
, "address", NULL
);
861 prom_printf("PROM does not have timer mapped, trying to continue.\n");
862 prom_timers
= (struct sun5_timer
*) 0;
865 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
868 static void kill_prom_timer(void)
873 /* Save them away for later. */
874 prom_limit0
= prom_timers
->limit0
;
875 prom_limit1
= prom_timers
->limit1
;
877 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
878 * We turn both off here just to be paranoid.
880 prom_timers
->limit0
= 0;
881 prom_timers
->limit1
= 0;
883 /* Wheee, eat the interrupt packet too... */
884 __asm__
__volatile__(
886 " ldxa [%%g0] %0, %%g1\n"
887 " ldxa [%%g2] %1, %%g1\n"
888 " stxa %%g0, [%%g0] %0\n"
891 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
895 void init_irqwork_curcpu(void)
897 int cpu
= hard_smp_processor_id();
899 trap_block
[cpu
].irq_worklist
= 0;
902 /* Please be very careful with register_one_mondo() and
903 * sun4v_register_mondo_queues().
905 * On SMP this gets invoked from the CPU trampoline before
906 * the cpu has fully taken over the trap table from OBP,
907 * and it's kernel stack + %g6 thread register state is
908 * not fully cooked yet.
910 * Therefore you cannot make any OBP calls, not even prom_printf,
911 * from these two routines.
913 static void __cpuinit
register_one_mondo(unsigned long paddr
, unsigned long type
, unsigned long qmask
)
915 unsigned long num_entries
= (qmask
+ 1) / 64;
916 unsigned long status
;
918 status
= sun4v_cpu_qconf(type
, paddr
, num_entries
);
919 if (status
!= HV_EOK
) {
920 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
921 "err %lu\n", type
, paddr
, num_entries
, status
);
926 static void __cpuinit
sun4v_register_mondo_queues(int this_cpu
)
928 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
930 register_one_mondo(tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
,
931 tb
->cpu_mondo_qmask
);
932 register_one_mondo(tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
,
933 tb
->dev_mondo_qmask
);
934 register_one_mondo(tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
,
936 register_one_mondo(tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
,
940 static void __cpuinit
alloc_one_mondo(unsigned long *pa_ptr
, unsigned long qmask
, int use_bootmem
)
942 unsigned long size
= PAGE_ALIGN(qmask
+ 1);
943 unsigned long order
= get_order(size
);
947 p
= __alloc_bootmem_low(size
, size
, 0);
949 struct page
*page
= alloc_pages(GFP_ATOMIC
| __GFP_ZERO
, order
);
951 p
= page_address(page
);
955 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
962 static void __cpuinit
alloc_one_kbuf(unsigned long *pa_ptr
, unsigned long qmask
, int use_bootmem
)
964 unsigned long size
= PAGE_ALIGN(qmask
+ 1);
965 unsigned long order
= get_order(size
);
969 p
= __alloc_bootmem_low(size
, size
, 0);
971 struct page
*page
= alloc_pages(GFP_ATOMIC
| __GFP_ZERO
, order
);
973 p
= page_address(page
);
977 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
984 static void __cpuinit
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
, int use_bootmem
)
989 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
992 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
994 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
997 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1001 tb
->cpu_mondo_block_pa
= __pa(page
);
1002 tb
->cpu_list_pa
= __pa(page
+ 64);
1006 /* Allocate and register the mondo and error queues for this cpu. */
1007 void __cpuinit
sun4v_init_mondo_queues(int use_bootmem
, int cpu
, int alloc
, int load
)
1009 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1012 alloc_one_mondo(&tb
->cpu_mondo_pa
, tb
->cpu_mondo_qmask
, use_bootmem
);
1013 alloc_one_mondo(&tb
->dev_mondo_pa
, tb
->dev_mondo_qmask
, use_bootmem
);
1014 alloc_one_mondo(&tb
->resum_mondo_pa
, tb
->resum_qmask
, use_bootmem
);
1015 alloc_one_kbuf(&tb
->resum_kernel_buf_pa
, tb
->resum_qmask
, use_bootmem
);
1016 alloc_one_mondo(&tb
->nonresum_mondo_pa
, tb
->nonresum_qmask
, use_bootmem
);
1017 alloc_one_kbuf(&tb
->nonresum_kernel_buf_pa
, tb
->nonresum_qmask
, use_bootmem
);
1019 init_cpu_send_mondo_info(tb
, use_bootmem
);
1023 if (cpu
!= hard_smp_processor_id()) {
1024 prom_printf("SUN4V: init mondo on cpu %d not %d\n",
1025 cpu
, hard_smp_processor_id());
1028 sun4v_register_mondo_queues(cpu
);
1032 static struct irqaction timer_irq_action
= {
1036 /* Only invoked on boot processor. */
1037 void __init
init_IRQ(void)
1041 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
1043 if (tlb_type
== hypervisor
)
1044 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
1046 /* We need to clear any IRQ's pending in the soft interrupt
1047 * registers, a spurious one could be left around from the
1048 * PROM timer which we just disabled.
1050 clear_softint(get_softint());
1052 /* Now that ivector table is initialized, it is safe
1053 * to receive IRQ vector traps. We will normally take
1054 * one or two right now, in case some device PROM used
1055 * to boot us wants to speak to us. We just ignore them.
1057 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
1058 "or %%g1, %0, %%g1\n\t"
1059 "wrpr %%g1, 0x0, %%pstate"
1064 irq_desc
[0].action
= &timer_irq_action
;