1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
24 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
33 #include <asm/iommu.h>
35 #include <asm/oplib.h>
36 #include <asm/timer.h>
38 #include <asm/starfire.h>
39 #include <asm/uaccess.h>
40 #include <asm/cache.h>
41 #include <asm/cpudata.h>
42 #include <asm/auxio.h>
46 static void distribute_irqs(void);
49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
50 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
51 * delivered. We must translate this into a non-vector IRQ so we can
52 * set the softint on this cpu.
54 * To make processing these packets efficient and race free we use
55 * an array of irq buckets below. The interrupt vector handler in
56 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
57 * The IVEC handler does not need to act atomically, the PIL dispatch
58 * code uses CAS to get an atomic snapshot of the list and clear it
62 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
64 /* This has to be in the main kernel image, it cannot be
65 * turned into per-cpu data. The reason is that the main
66 * kernel image is locked into the TLB and this structure
67 * is accessed from the vectored interrupt trap handler. If
68 * access to this structure takes a TLB miss it could cause
69 * the 5-level sparc v9 trap stack to overflow.
71 struct irq_work_struct
{
72 unsigned int irq_worklists
[16];
74 struct irq_work_struct __irq_work
[NR_CPUS
];
75 #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
77 static struct irqaction
*irq_action
[NR_IRQS
+1];
79 /* This only synchronizes entities which modify IRQ handler
80 * state and some selected user-level spots that want to
81 * read things in the table. IRQ handler processing orders
82 * its' accesses such that no locking is needed.
84 static DEFINE_SPINLOCK(irq_action_lock
);
86 static void register_irq_proc (unsigned int irq
);
89 * Upper 2b of irqaction->flags holds the ino.
90 * irqaction->mask holds the smp affinity information.
92 #define put_ino_in_irqaction(action, irq) \
93 action->flags &= 0xffffffffffffUL; \
94 if (__bucket(irq) == &pil0_dummy_bucket) \
95 action->flags |= 0xdeadUL << 48; \
97 action->flags |= __irq_ino(irq) << 48;
98 #define get_ino_in_irqaction(action) (action->flags >> 48)
100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
101 #define get_smpaff_in_irqaction(action) ((action)->mask)
103 int show_interrupts(struct seq_file
*p
, void *v
)
106 int i
= *(loff_t
*) v
;
107 struct irqaction
*action
;
112 spin_lock_irqsave(&irq_action_lock
, flags
);
114 if (!(action
= *(i
+ irq_action
)))
116 seq_printf(p
, "%3d: ", i
);
118 seq_printf(p
, "%10u ", kstat_irqs(i
));
120 for (j
= 0; j
< NR_CPUS
; j
++) {
123 seq_printf(p
, "%10u ",
124 kstat_cpu(j
).irqs
[i
]);
127 seq_printf(p
, " %s:%lx", action
->name
,
128 get_ino_in_irqaction(action
));
129 for (action
= action
->next
; action
; action
= action
->next
) {
130 seq_printf(p
, ", %s:%lx", action
->name
,
131 get_ino_in_irqaction(action
));
136 spin_unlock_irqrestore(&irq_action_lock
, flags
);
141 /* Now these are always passed a true fully specified sun4u INO. */
142 void enable_irq(unsigned int irq
)
144 struct ino_bucket
*bucket
= __bucket(irq
);
153 if (tlb_type
== hypervisor
) {
154 unsigned int ino
= __irq_ino(irq
);
155 int cpu
= hard_smp_processor_id();
158 err
= sun4v_intr_settarget(ino
, cpu
);
160 printk("sun4v_intr_settarget(%x,%d): err(%d)\n",
162 err
= sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
164 printk("sun4v_intr_setenabled(%x): err(%d)\n",
169 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
172 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
173 if ((ver
>> 32) == __JALAPENO_ID
||
174 (ver
>> 32) == __SERRANO_ID
) {
175 /* We set it to our JBUS ID. */
176 __asm__
__volatile__("ldxa [%%g0] %1, %0"
178 : "i" (ASI_JBUS_CONFIG
));
179 tid
= ((tid
& (0x1fUL
<<17)) << 9);
180 tid
&= IMAP_TID_JBUS
;
182 /* We set it to our Safari AID. */
183 __asm__
__volatile__("ldxa [%%g0] %1, %0"
185 : "i"(ASI_SAFARI_CONFIG
));
186 tid
= ((tid
& (0x3ffUL
<<17)) << 9);
187 tid
&= IMAP_AID_SAFARI
;
189 } else if (this_is_starfire
== 0) {
190 /* We set it to our UPA MID. */
191 __asm__
__volatile__("ldxa [%%g0] %1, %0"
193 : "i" (ASI_UPA_CONFIG
));
194 tid
= ((tid
& UPA_CONFIG_MID
) << 9);
197 tid
= (starfire_translate(imap
,
198 smp_processor_id()) << 26);
202 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
203 * of this SYSIO's preconfigured IGN in the SYSIO Control
204 * Register, the hardware just mirrors that value here.
205 * However for Graphics and UPA Slave devices the full
206 * IMAP_INR field can be set by the programmer here.
208 * Things like FFB can now be handled via the new IRQ
211 upa_writel(tid
| IMAP_VALID
, imap
);
217 /* This now gets passed true ino's as well. */
218 void disable_irq(unsigned int irq
)
220 struct ino_bucket
*bucket
= __bucket(irq
);
225 if (tlb_type
== hypervisor
) {
226 unsigned int ino
= __irq_ino(irq
);
229 err
= sun4v_intr_setenabled(ino
, HV_INTR_DISABLED
);
231 printk("sun4v_intr_setenabled(%x): "
232 "err(%d)\n", ino
, err
);
236 /* NOTE: We do not want to futz with the IRQ clear registers
237 * and move the state to IDLE, the SCSI code does call
238 * disable_irq() to assure atomicity in the queue cmd
239 * SCSI adapter driver code. Thus we'd lose interrupts.
241 tmp
= upa_readl(imap
);
243 upa_writel(tmp
, imap
);
248 /* The timer is the one "weird" interrupt which is generated by
249 * the CPU %tick register and not by some normal vectored interrupt
250 * source. To handle this special case, we use this dummy INO bucket.
252 static struct irq_desc pil0_dummy_desc
;
253 static struct ino_bucket pil0_dummy_bucket
= {
254 .irq_info
= &pil0_dummy_desc
,
257 static void build_irq_error(const char *msg
, unsigned int ino
, int pil
, int inofixup
,
258 unsigned long iclr
, unsigned long imap
,
259 struct ino_bucket
*bucket
)
261 prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
262 "(%d:%d:%016lx:%016lx), halting...\n",
263 ino
, bucket
->pil
, bucket
->iclr
, bucket
->imap
,
264 pil
, inofixup
, iclr
, imap
);
268 unsigned int build_irq(int pil
, int inofixup
, unsigned long iclr
, unsigned long imap
)
270 struct ino_bucket
*bucket
;
274 if (iclr
!= 0UL || imap
!= 0UL) {
275 prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
279 return __irq(&pil0_dummy_bucket
);
282 BUG_ON(tlb_type
== hypervisor
);
284 /* RULE: Both must be specified in all other cases. */
285 if (iclr
== 0UL || imap
== 0UL) {
286 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
287 pil
, inofixup
, iclr
, imap
);
291 ino
= (upa_readl(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
292 if (ino
> NUM_IVECS
) {
293 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
294 ino
, pil
, inofixup
, iclr
, imap
);
298 bucket
= &ivector_table
[ino
];
299 if (bucket
->flags
& IBF_ACTIVE
)
300 build_irq_error("IRQ: Trying to build active INO bucket.\n",
301 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
303 if (bucket
->irq_info
) {
304 if (bucket
->imap
!= imap
|| bucket
->iclr
!= iclr
)
305 build_irq_error("IRQ: Trying to reinit INO bucket.\n",
306 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
311 bucket
->irq_info
= kmalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
312 if (!bucket
->irq_info
) {
313 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
316 memset(bucket
->irq_info
, 0, sizeof(struct irq_desc
));
318 /* Ok, looks good, set it up. Don't touch the irq_chain or
327 return __irq(bucket
);
330 unsigned int sun4v_build_irq(u32 devhandle
, unsigned int devino
, int pil
, unsigned char flags
)
332 struct ino_bucket
*bucket
;
333 unsigned long sysino
;
335 sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
337 bucket
= &ivector_table
[sysino
];
339 /* Catch accidental accesses to these things. IMAP/ICLR handling
340 * is done by hypervisor calls on sun4v platforms, not by direct
343 * But we need to make them look unique for the disable_irq() logic
346 bucket
->imap
= ~0UL - sysino
;
347 bucket
->iclr
= ~0UL - sysino
;
350 bucket
->flags
= flags
;
352 bucket
->irq_info
= kmalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
353 if (!bucket
->irq_info
) {
354 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
357 memset(bucket
->irq_info
, 0, sizeof(struct irq_desc
));
359 return __irq(bucket
);
362 static void atomic_bucket_insert(struct ino_bucket
*bucket
)
364 unsigned long pstate
;
367 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
368 __asm__
__volatile__("wrpr %0, %1, %%pstate"
369 : : "r" (pstate
), "i" (PSTATE_IE
));
370 ent
= irq_work(smp_processor_id(), bucket
->pil
);
371 bucket
->irq_chain
= *ent
;
372 *ent
= __irq(bucket
);
373 __asm__
__volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate
));
376 static int check_irq_sharing(int pil
, unsigned long irqflags
)
378 struct irqaction
*action
, *tmp
;
380 action
= *(irq_action
+ pil
);
382 if ((action
->flags
& SA_SHIRQ
) && (irqflags
& SA_SHIRQ
)) {
383 for (tmp
= action
; tmp
->next
; tmp
= tmp
->next
)
392 static void append_irq_action(int pil
, struct irqaction
*action
)
394 struct irqaction
**pp
= irq_action
+ pil
;
401 static struct irqaction
*get_action_slot(struct ino_bucket
*bucket
)
403 struct irq_desc
*desc
= bucket
->irq_info
;
407 if (bucket
->flags
& IBF_PCI
)
408 max_irq
= MAX_IRQ_DESC_ACTION
;
409 for (i
= 0; i
< max_irq
; i
++) {
410 struct irqaction
*p
= &desc
->action
[i
];
413 if (desc
->action_active_mask
& mask
)
416 desc
->action_active_mask
|= mask
;
422 int request_irq(unsigned int irq
, irqreturn_t (*handler
)(int, void *, struct pt_regs
*),
423 unsigned long irqflags
, const char *name
, void *dev_id
)
425 struct irqaction
*action
;
426 struct ino_bucket
*bucket
= __bucket(irq
);
430 if (unlikely(!handler
))
433 if (unlikely(!bucket
->irq_info
))
436 if ((bucket
!= &pil0_dummy_bucket
) && (irqflags
& SA_SAMPLE_RANDOM
)) {
438 * This function might sleep, we want to call it first,
439 * outside of the atomic block. In SA_STATIC_ALLOC case,
440 * random driver's kmalloc will fail, but it is safe.
441 * If already initialized, random driver will not reinit.
442 * Yes, this might clear the entropy pool if the wrong
443 * driver is attempted to be loaded, without actually
444 * installing a new handler, but is this really a problem,
445 * only the sysadmin is able to do this.
447 rand_initialize_irq(irq
);
450 spin_lock_irqsave(&irq_action_lock
, flags
);
452 if (check_irq_sharing(bucket
->pil
, irqflags
)) {
453 spin_unlock_irqrestore(&irq_action_lock
, flags
);
457 action
= get_action_slot(bucket
);
459 spin_unlock_irqrestore(&irq_action_lock
, flags
);
463 bucket
->flags
|= IBF_ACTIVE
;
465 if (bucket
!= &pil0_dummy_bucket
) {
466 pending
= bucket
->pending
;
471 action
->handler
= handler
;
472 action
->flags
= irqflags
;
475 action
->dev_id
= dev_id
;
476 put_ino_in_irqaction(action
, irq
);
477 put_smpaff_in_irqaction(action
, CPU_MASK_NONE
);
479 append_irq_action(bucket
->pil
, action
);
483 /* We ate the IVEC already, this makes sure it does not get lost. */
485 atomic_bucket_insert(bucket
);
486 set_softint(1 << bucket
->pil
);
489 spin_unlock_irqrestore(&irq_action_lock
, flags
);
491 if (bucket
!= &pil0_dummy_bucket
)
492 register_irq_proc(__irq_ino(irq
));
500 EXPORT_SYMBOL(request_irq
);
502 static struct irqaction
*unlink_irq_action(unsigned int irq
, void *dev_id
)
504 struct ino_bucket
*bucket
= __bucket(irq
);
505 struct irqaction
*action
, **pp
;
507 pp
= irq_action
+ bucket
->pil
;
509 if (unlikely(!action
))
512 if (unlikely(!action
->handler
)) {
513 printk("Freeing free IRQ %d\n", bucket
->pil
);
517 while (action
&& action
->dev_id
!= dev_id
) {
528 void free_irq(unsigned int irq
, void *dev_id
)
530 struct irqaction
*action
;
531 struct ino_bucket
*bucket
;
534 spin_lock_irqsave(&irq_action_lock
, flags
);
536 action
= unlink_irq_action(irq
, dev_id
);
538 spin_unlock_irqrestore(&irq_action_lock
, flags
);
540 if (unlikely(!action
))
543 synchronize_irq(irq
);
545 spin_lock_irqsave(&irq_action_lock
, flags
);
547 bucket
= __bucket(irq
);
548 if (bucket
!= &pil0_dummy_bucket
) {
549 struct irq_desc
*desc
= bucket
->irq_info
;
552 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
553 struct irqaction
*p
= &desc
->action
[i
];
556 desc
->action_active_mask
&= ~(1 << i
);
561 if (!desc
->action_active_mask
) {
562 unsigned long imap
= bucket
->imap
;
564 /* This unique interrupt source is now inactive. */
565 bucket
->flags
&= ~IBF_ACTIVE
;
567 /* See if any other buckets share this bucket's IMAP
568 * and are still active.
570 for (ent
= 0; ent
< NUM_IVECS
; ent
++) {
571 struct ino_bucket
*bp
= &ivector_table
[ent
];
574 (bp
->flags
& IBF_ACTIVE
) != 0)
578 /* Only disable when no other sub-irq levels of
579 * the same IMAP are active.
581 if (ent
== NUM_IVECS
)
586 spin_unlock_irqrestore(&irq_action_lock
, flags
);
589 EXPORT_SYMBOL(free_irq
);
592 void synchronize_irq(unsigned int irq
)
594 struct ino_bucket
*bucket
= __bucket(irq
);
597 /* The following is how I wish I could implement this.
598 * Unfortunately the ICLR registers are read-only, you can
599 * only write ICLR_foo values to them. To get the current
600 * IRQ status you would need to get at the IRQ diag registers
601 * in the PCI/SBUS controller and the layout of those vary
602 * from one controller to the next, sigh... -DaveM
604 unsigned long iclr
= bucket
->iclr
;
607 u32 tmp
= upa_readl(iclr
);
609 if (tmp
== ICLR_TRANSMIT
||
610 tmp
== ICLR_PENDING
) {
617 /* So we have to do this with a INPROGRESS bit just like x86. */
618 while (bucket
->flags
& IBF_INPROGRESS
)
622 #endif /* CONFIG_SMP */
624 static void process_bucket(int irq
, struct ino_bucket
*bp
, struct pt_regs
*regs
)
626 struct irq_desc
*desc
= bp
->irq_info
;
627 unsigned char flags
= bp
->flags
;
631 bp
->flags
|= IBF_INPROGRESS
;
633 if (unlikely(!(flags
& IBF_ACTIVE
))) {
638 if (desc
->pre_handler
)
639 desc
->pre_handler(bp
,
640 desc
->pre_handler_arg1
,
641 desc
->pre_handler_arg2
);
643 action_mask
= desc
->action_active_mask
;
645 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
646 struct irqaction
*p
= &desc
->action
[i
];
649 if (!(action_mask
& mask
))
652 action_mask
&= ~mask
;
654 if (p
->handler(__irq(bp
), p
->dev_id
, regs
) == IRQ_HANDLED
)
661 if (tlb_type
== hypervisor
) {
662 unsigned int ino
= __irq_ino(bp
);
665 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
667 printk("sun4v_intr_setstate(%x): "
668 "err(%d)\n", ino
, err
);
670 upa_writel(ICLR_IDLE
, bp
->iclr
);
673 /* Test and add entropy */
674 if (random
& SA_SAMPLE_RANDOM
)
675 add_interrupt_randomness(irq
);
678 bp
->flags
&= ~IBF_INPROGRESS
;
681 void handler_irq(int irq
, struct pt_regs
*regs
)
683 struct ino_bucket
*bp
;
684 int cpu
= smp_processor_id();
688 * Check for TICK_INT on level 14 softint.
691 unsigned long clr_mask
= 1 << irq
;
692 unsigned long tick_mask
= tick_ops
->softint_mask
;
694 if ((irq
== 14) && (get_softint() & tick_mask
)) {
696 clr_mask
= tick_mask
;
698 clear_softint(clr_mask
);
701 clear_softint(1 << irq
);
705 kstat_this_cpu
.irqs
[irq
]++;
710 __bucket(xchg32(irq_work(cpu
, irq
), 0)) :
713 bp
= __bucket(xchg32(irq_work(cpu
, irq
), 0));
716 struct ino_bucket
*nbp
= __bucket(bp
->irq_chain
);
719 process_bucket(irq
, bp
, regs
);
725 #ifdef CONFIG_BLK_DEV_FD
726 extern irqreturn_t
floppy_interrupt(int, void *, struct pt_regs
*);;
728 /* XXX No easy way to include asm/floppy.h XXX */
729 extern unsigned char *pdma_vaddr
;
730 extern unsigned long pdma_size
;
731 extern volatile int doing_pdma
;
732 extern unsigned long fdc_status
;
734 irqreturn_t
sparc_floppy_irq(int irq
, void *dev_cookie
, struct pt_regs
*regs
)
736 if (likely(doing_pdma
)) {
737 void __iomem
*stat
= (void __iomem
*) fdc_status
;
738 unsigned char *vaddr
= pdma_vaddr
;
739 unsigned long size
= pdma_size
;
744 if (unlikely(!(val
& 0x80))) {
749 if (unlikely(!(val
& 0x20))) {
757 *vaddr
++ = readb(stat
+ 1);
759 unsigned char data
= *vaddr
++;
762 writeb(data
, stat
+ 1);
770 /* Send Terminal Count pulse to floppy controller. */
771 val
= readb(auxio_register
);
772 val
|= AUXIO_AUX1_FTCNT
;
773 writeb(val
, auxio_register
);
774 val
&= ~AUXIO_AUX1_FTCNT
;
775 writeb(val
, auxio_register
);
781 return floppy_interrupt(irq
, dev_cookie
, regs
);
783 EXPORT_SYMBOL(sparc_floppy_irq
);
786 /* We really don't need these at all on the Sparc. We only have
787 * stubs here because they are exported to modules.
789 unsigned long probe_irq_on(void)
794 EXPORT_SYMBOL(probe_irq_on
);
796 int probe_irq_off(unsigned long mask
)
801 EXPORT_SYMBOL(probe_irq_off
);
804 static int retarget_one_irq(struct irqaction
*p
, int goal_cpu
)
806 struct ino_bucket
*bucket
= get_ino_in_irqaction(p
) + ivector_table
;
808 while (!cpu_online(goal_cpu
)) {
809 if (++goal_cpu
>= NR_CPUS
)
813 if (tlb_type
== hypervisor
) {
814 unsigned int ino
= __irq_ino(bucket
);
816 sun4v_intr_settarget(ino
, goal_cpu
);
817 sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
819 unsigned long imap
= bucket
->imap
;
822 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
823 tid
= goal_cpu
<< 26;
824 tid
&= IMAP_AID_SAFARI
;
825 } else if (this_is_starfire
== 0) {
826 tid
= goal_cpu
<< 26;
829 tid
= (starfire_translate(imap
, goal_cpu
) << 26);
832 upa_writel(tid
| IMAP_VALID
, imap
);
836 if (++goal_cpu
>= NR_CPUS
)
838 } while (!cpu_online(goal_cpu
));
843 /* Called from request_irq. */
844 static void distribute_irqs(void)
849 spin_lock_irqsave(&irq_action_lock
, flags
);
853 * Skip the timer at [0], and very rare error/power intrs at [15].
854 * Also level [12], it causes problems on Ex000 systems.
856 for (level
= 1; level
< NR_IRQS
; level
++) {
857 struct irqaction
*p
= irq_action
[level
];
863 cpu
= retarget_one_irq(p
, cpu
);
867 spin_unlock_irqrestore(&irq_action_lock
, flags
);
878 static struct sun5_timer
*prom_timers
;
879 static u64 prom_limit0
, prom_limit1
;
881 static void map_prom_timers(void)
883 unsigned int addr
[3];
886 /* PROM timer node hangs out in the top level of device siblings... */
887 tnode
= prom_finddevice("/counter-timer");
889 /* Assume if node is not present, PROM uses different tick mechanism
890 * which we should not care about.
892 if (tnode
== 0 || tnode
== -1) {
893 prom_timers
= (struct sun5_timer
*) 0;
897 /* If PROM is really using this, it must be mapped by him. */
898 err
= prom_getproperty(tnode
, "address", (char *)addr
, sizeof(addr
));
900 prom_printf("PROM does not have timer mapped, trying to continue.\n");
901 prom_timers
= (struct sun5_timer
*) 0;
904 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
907 static void kill_prom_timer(void)
912 /* Save them away for later. */
913 prom_limit0
= prom_timers
->limit0
;
914 prom_limit1
= prom_timers
->limit1
;
916 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
917 * We turn both off here just to be paranoid.
919 prom_timers
->limit0
= 0;
920 prom_timers
->limit1
= 0;
922 /* Wheee, eat the interrupt packet too... */
923 __asm__
__volatile__(
925 " ldxa [%%g0] %0, %%g1\n"
926 " ldxa [%%g2] %1, %%g1\n"
927 " stxa %%g0, [%%g0] %0\n"
930 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
934 void init_irqwork_curcpu(void)
936 int cpu
= hard_smp_processor_id();
938 memset(__irq_work
+ cpu
, 0, sizeof(struct irq_work_struct
));
941 static void __cpuinit
register_one_mondo(unsigned long paddr
, unsigned long type
)
943 unsigned long num_entries
= 128;
944 unsigned long status
;
946 status
= sun4v_cpu_qconf(type
, paddr
, num_entries
);
947 if (status
!= HV_EOK
) {
948 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
949 "err %lu\n", type
, paddr
, num_entries
, status
);
954 static void __cpuinit
sun4v_register_mondo_queues(int this_cpu
)
956 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
958 register_one_mondo(tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
);
959 register_one_mondo(tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
);
960 register_one_mondo(tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
);
961 register_one_mondo(tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
);
964 static void __cpuinit
alloc_one_mondo(unsigned long *pa_ptr
, int use_bootmem
)
969 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
971 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
974 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
978 *pa_ptr
= __pa(page
);
981 static void __cpuinit
alloc_one_kbuf(unsigned long *pa_ptr
, int use_bootmem
)
986 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
988 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
991 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
995 *pa_ptr
= __pa(page
);
998 static void __cpuinit
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
, int use_bootmem
)
1003 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
1006 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
1008 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
1011 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1015 tb
->cpu_mondo_block_pa
= __pa(page
);
1016 tb
->cpu_list_pa
= __pa(page
+ 64);
1020 /* Allocate and register the mondo and error queues for this cpu. */
1021 void __cpuinit
sun4v_init_mondo_queues(int use_bootmem
, int cpu
, int alloc
, int load
)
1023 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1026 alloc_one_mondo(&tb
->cpu_mondo_pa
, use_bootmem
);
1027 alloc_one_mondo(&tb
->dev_mondo_pa
, use_bootmem
);
1028 alloc_one_mondo(&tb
->resum_mondo_pa
, use_bootmem
);
1029 alloc_one_kbuf(&tb
->resum_kernel_buf_pa
, use_bootmem
);
1030 alloc_one_mondo(&tb
->nonresum_mondo_pa
, use_bootmem
);
1031 alloc_one_kbuf(&tb
->nonresum_kernel_buf_pa
, use_bootmem
);
1033 init_cpu_send_mondo_info(tb
, use_bootmem
);
1037 if (cpu
!= hard_smp_processor_id()) {
1038 prom_printf("SUN4V: init mondo on cpu %d not %d\n",
1039 cpu
, hard_smp_processor_id());
1042 sun4v_register_mondo_queues(cpu
);
1046 /* Only invoked on boot processor. */
1047 void __init
init_IRQ(void)
1051 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
1053 if (tlb_type
== hypervisor
)
1054 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
1056 /* We need to clear any IRQ's pending in the soft interrupt
1057 * registers, a spurious one could be left around from the
1058 * PROM timer which we just disabled.
1060 clear_softint(get_softint());
1062 /* Now that ivector table is initialized, it is safe
1063 * to receive IRQ vector traps. We will normally take
1064 * one or two right now, in case some device PROM used
1065 * to boot us wants to speak to us. We just ignore them.
1067 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
1068 "or %%g1, %0, %%g1\n\t"
1069 "wrpr %%g1, 0x0, %%pstate"
1075 static struct proc_dir_entry
* root_irq_dir
;
1076 static struct proc_dir_entry
* irq_dir
[NUM_IVECS
];
1080 static int irq_affinity_read_proc (char *page
, char **start
, off_t off
,
1081 int count
, int *eof
, void *data
)
1083 struct ino_bucket
*bp
= ivector_table
+ (long)data
;
1084 struct irq_desc
*desc
= bp
->irq_info
;
1085 struct irqaction
*ap
= desc
->action
;
1089 mask
= get_smpaff_in_irqaction(ap
);
1090 if (cpus_empty(mask
))
1091 mask
= cpu_online_map
;
1093 len
= cpumask_scnprintf(page
, count
, mask
);
1094 if (count
- len
< 2)
1096 len
+= sprintf(page
+ len
, "\n");
1100 static inline void set_intr_affinity(int irq
, cpumask_t hw_aff
)
1102 struct ino_bucket
*bp
= ivector_table
+ irq
;
1103 struct irq_desc
*desc
= bp
->irq_info
;
1104 struct irqaction
*ap
= desc
->action
;
1106 /* Users specify affinity in terms of hw cpu ids.
1107 * As soon as we do this, handler_irq() might see and take action.
1109 put_smpaff_in_irqaction(ap
, hw_aff
);
1111 /* Migration is simply done by the next cpu to service this
1116 static int irq_affinity_write_proc (struct file
*file
, const char __user
*buffer
,
1117 unsigned long count
, void *data
)
1119 int irq
= (long) data
, full_count
= count
, err
;
1120 cpumask_t new_value
;
1122 err
= cpumask_parse(buffer
, count
, new_value
);
1125 * Do not allow disabling IRQs completely - it's a too easy
1126 * way to make the system unusable accidentally :-) At least
1127 * one online CPU still has to be targeted.
1129 cpus_and(new_value
, new_value
, cpu_online_map
);
1130 if (cpus_empty(new_value
))
1133 set_intr_affinity(irq
, new_value
);
1140 #define MAX_NAMELEN 10
1142 static void register_irq_proc (unsigned int irq
)
1144 char name
[MAX_NAMELEN
];
1146 if (!root_irq_dir
|| irq_dir
[irq
])
1149 memset(name
, 0, MAX_NAMELEN
);
1150 sprintf(name
, "%x", irq
);
1152 /* create /proc/irq/1234 */
1153 irq_dir
[irq
] = proc_mkdir(name
, root_irq_dir
);
1156 /* XXX SMP affinity not supported on starfire yet. */
1157 if (this_is_starfire
== 0) {
1158 struct proc_dir_entry
*entry
;
1160 /* create /proc/irq/1234/smp_affinity */
1161 entry
= create_proc_entry("smp_affinity", 0600, irq_dir
[irq
]);
1165 entry
->data
= (void *)(long)irq
;
1166 entry
->read_proc
= irq_affinity_read_proc
;
1167 entry
->write_proc
= irq_affinity_write_proc
;
1173 void init_irq_proc (void)
1175 /* create /proc/irq */
1176 root_irq_dir
= proc_mkdir("irq", NULL
);