1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
24 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
33 #include <asm/iommu.h>
35 #include <asm/oplib.h>
36 #include <asm/timer.h>
38 #include <asm/starfire.h>
39 #include <asm/uaccess.h>
40 #include <asm/cache.h>
41 #include <asm/cpudata.h>
42 #include <asm/auxio.h>
46 static void distribute_irqs(void);
49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
50 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
51 * delivered. We must translate this into a non-vector IRQ so we can
52 * set the softint on this cpu.
54 * To make processing these packets efficient and race free we use
55 * an array of irq buckets below. The interrupt vector handler in
56 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
57 * The IVEC handler does not need to act atomically, the PIL dispatch
58 * code uses CAS to get an atomic snapshot of the list and clear it
62 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
64 /* This has to be in the main kernel image, it cannot be
65 * turned into per-cpu data. The reason is that the main
66 * kernel image is locked into the TLB and this structure
67 * is accessed from the vectored interrupt trap handler. If
68 * access to this structure takes a TLB miss it could cause
69 * the 5-level sparc v9 trap stack to overflow.
71 struct irq_work_struct
{
72 unsigned int irq_worklists
[16];
74 struct irq_work_struct __irq_work
[NR_CPUS
];
75 #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
77 static struct irqaction
*irq_action
[NR_IRQS
+1];
79 /* This only synchronizes entities which modify IRQ handler
80 * state and some selected user-level spots that want to
81 * read things in the table. IRQ handler processing orders
82 * its' accesses such that no locking is needed.
84 static DEFINE_SPINLOCK(irq_action_lock
);
86 static void register_irq_proc (unsigned int irq
);
89 * Upper 2b of irqaction->flags holds the ino.
90 * irqaction->mask holds the smp affinity information.
92 #define put_ino_in_irqaction(action, irq) \
93 action->flags &= 0xffffffffffffUL; \
94 if (__bucket(irq) == &pil0_dummy_bucket) \
95 action->flags |= 0xdeadUL << 48; \
97 action->flags |= __irq_ino(irq) << 48;
98 #define get_ino_in_irqaction(action) (action->flags >> 48)
100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
101 #define get_smpaff_in_irqaction(action) ((action)->mask)
103 int show_interrupts(struct seq_file
*p
, void *v
)
106 int i
= *(loff_t
*) v
;
107 struct irqaction
*action
;
112 spin_lock_irqsave(&irq_action_lock
, flags
);
114 if (!(action
= *(i
+ irq_action
)))
116 seq_printf(p
, "%3d: ", i
);
118 seq_printf(p
, "%10u ", kstat_irqs(i
));
120 for (j
= 0; j
< NR_CPUS
; j
++) {
123 seq_printf(p
, "%10u ",
124 kstat_cpu(j
).irqs
[i
]);
127 seq_printf(p
, " %s:%lx", action
->name
,
128 get_ino_in_irqaction(action
));
129 for (action
= action
->next
; action
; action
= action
->next
) {
130 seq_printf(p
, ", %s:%lx", action
->name
,
131 get_ino_in_irqaction(action
));
136 spin_unlock_irqrestore(&irq_action_lock
, flags
);
141 /* Now these are always passed a true fully specified sun4u INO. */
142 void enable_irq(unsigned int irq
)
144 struct ino_bucket
*bucket
= __bucket(irq
);
154 if (tlb_type
== hypervisor
) {
155 int cpu
= hard_smp_processor_id();
157 sun4v_intr_settarget(irq
, cpu
);
158 sun4v_intr_setenabled(irq
, HV_INTR_ENABLED
);
160 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
163 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
164 if ((ver
>> 32) == __JALAPENO_ID
||
165 (ver
>> 32) == __SERRANO_ID
) {
166 /* We set it to our JBUS ID. */
167 __asm__
__volatile__("ldxa [%%g0] %1, %0"
169 : "i" (ASI_JBUS_CONFIG
));
170 tid
= ((tid
& (0x1fUL
<<17)) << 9);
171 tid
&= IMAP_TID_JBUS
;
173 /* We set it to our Safari AID. */
174 __asm__
__volatile__("ldxa [%%g0] %1, %0"
176 : "i"(ASI_SAFARI_CONFIG
));
177 tid
= ((tid
& (0x3ffUL
<<17)) << 9);
178 tid
&= IMAP_AID_SAFARI
;
180 } else if (this_is_starfire
== 0) {
181 /* We set it to our UPA MID. */
182 __asm__
__volatile__("ldxa [%%g0] %1, %0"
184 : "i" (ASI_UPA_CONFIG
));
185 tid
= ((tid
& UPA_CONFIG_MID
) << 9);
188 tid
= (starfire_translate(imap
,
189 smp_processor_id()) << 26);
193 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
194 * of this SYSIO's preconfigured IGN in the SYSIO Control
195 * Register, the hardware just mirrors that value here.
196 * However for Graphics and UPA Slave devices the full
197 * IMAP_INR field can be set by the programmer here.
199 * Things like FFB can now be handled via the new IRQ
202 upa_writel(tid
| IMAP_VALID
, imap
);
208 /* This now gets passed true ino's as well. */
209 void disable_irq(unsigned int irq
)
211 struct ino_bucket
*bucket
= __bucket(irq
);
216 if (tlb_type
== hypervisor
) {
217 sun4v_intr_setenabled(irq
, HV_INTR_DISABLED
);
221 /* NOTE: We do not want to futz with the IRQ clear registers
222 * and move the state to IDLE, the SCSI code does call
223 * disable_irq() to assure atomicity in the queue cmd
224 * SCSI adapter driver code. Thus we'd lose interrupts.
226 tmp
= upa_readl(imap
);
228 upa_writel(tmp
, imap
);
233 /* The timer is the one "weird" interrupt which is generated by
234 * the CPU %tick register and not by some normal vectored interrupt
235 * source. To handle this special case, we use this dummy INO bucket.
237 static struct irq_desc pil0_dummy_desc
;
238 static struct ino_bucket pil0_dummy_bucket
= {
239 .irq_info
= &pil0_dummy_desc
,
242 static void build_irq_error(const char *msg
, unsigned int ino
, int pil
, int inofixup
,
243 unsigned long iclr
, unsigned long imap
,
244 struct ino_bucket
*bucket
)
246 prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
247 "(%d:%d:%016lx:%016lx), halting...\n",
248 ino
, bucket
->pil
, bucket
->iclr
, bucket
->imap
,
249 pil
, inofixup
, iclr
, imap
);
253 unsigned int build_irq(int pil
, int inofixup
, unsigned long iclr
, unsigned long imap
)
255 struct ino_bucket
*bucket
;
259 if (iclr
!= 0UL || imap
!= 0UL) {
260 prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
264 return __irq(&pil0_dummy_bucket
);
267 BUG_ON(tlb_type
== hypervisor
);
269 /* RULE: Both must be specified in all other cases. */
270 if (iclr
== 0UL || imap
== 0UL) {
271 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
272 pil
, inofixup
, iclr
, imap
);
276 ino
= (upa_readl(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
277 if (ino
> NUM_IVECS
) {
278 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
279 ino
, pil
, inofixup
, iclr
, imap
);
283 bucket
= &ivector_table
[ino
];
284 if (bucket
->flags
& IBF_ACTIVE
)
285 build_irq_error("IRQ: Trying to build active INO bucket.\n",
286 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
288 if (bucket
->irq_info
) {
289 if (bucket
->imap
!= imap
|| bucket
->iclr
!= iclr
)
290 build_irq_error("IRQ: Trying to reinit INO bucket.\n",
291 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
296 bucket
->irq_info
= kmalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
297 if (!bucket
->irq_info
) {
298 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
301 memset(bucket
->irq_info
, 0, sizeof(struct irq_desc
));
303 /* Ok, looks good, set it up. Don't touch the irq_chain or
312 return __irq(bucket
);
315 unsigned int sun4v_build_irq(u32 devhandle
, unsigned int devino
, int pil
, unsigned char flags
)
317 struct ino_bucket
*bucket
;
318 unsigned long sysino
;
320 sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
322 printk(KERN_INFO
"sun4v_irq: Mapping ( devh[%08x] devino[%08x] ) "
323 "--> sysino[%016lx]\n", devhandle
, devino
, sysino
);
325 bucket
= &ivector_table
[sysino
];
327 /* Catch accidental accesses to these things. IMAP/ICLR handling
328 * is done by hypervisor calls on sun4v platforms, not by direct
335 bucket
->flags
= flags
;
337 bucket
->irq_info
= kmalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
338 if (!bucket
->irq_info
) {
339 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
342 memset(bucket
->irq_info
, 0, sizeof(struct irq_desc
));
344 return __irq(bucket
);
347 static void atomic_bucket_insert(struct ino_bucket
*bucket
)
349 unsigned long pstate
;
352 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
353 __asm__
__volatile__("wrpr %0, %1, %%pstate"
354 : : "r" (pstate
), "i" (PSTATE_IE
));
355 ent
= irq_work(smp_processor_id(), bucket
->pil
);
356 bucket
->irq_chain
= *ent
;
357 *ent
= __irq(bucket
);
358 __asm__
__volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate
));
361 static int check_irq_sharing(int pil
, unsigned long irqflags
)
363 struct irqaction
*action
, *tmp
;
365 action
= *(irq_action
+ pil
);
367 if ((action
->flags
& SA_SHIRQ
) && (irqflags
& SA_SHIRQ
)) {
368 for (tmp
= action
; tmp
->next
; tmp
= tmp
->next
)
377 static void append_irq_action(int pil
, struct irqaction
*action
)
379 struct irqaction
**pp
= irq_action
+ pil
;
386 static struct irqaction
*get_action_slot(struct ino_bucket
*bucket
)
388 struct irq_desc
*desc
= bucket
->irq_info
;
392 if (bucket
->flags
& IBF_PCI
)
393 max_irq
= MAX_IRQ_DESC_ACTION
;
394 for (i
= 0; i
< max_irq
; i
++) {
395 struct irqaction
*p
= &desc
->action
[i
];
398 if (desc
->action_active_mask
& mask
)
401 desc
->action_active_mask
|= mask
;
407 int request_irq(unsigned int irq
, irqreturn_t (*handler
)(int, void *, struct pt_regs
*),
408 unsigned long irqflags
, const char *name
, void *dev_id
)
410 struct irqaction
*action
;
411 struct ino_bucket
*bucket
= __bucket(irq
);
415 if (unlikely(!handler
))
418 if (unlikely(!bucket
->irq_info
))
421 if ((bucket
!= &pil0_dummy_bucket
) && (irqflags
& SA_SAMPLE_RANDOM
)) {
423 * This function might sleep, we want to call it first,
424 * outside of the atomic block. In SA_STATIC_ALLOC case,
425 * random driver's kmalloc will fail, but it is safe.
426 * If already initialized, random driver will not reinit.
427 * Yes, this might clear the entropy pool if the wrong
428 * driver is attempted to be loaded, without actually
429 * installing a new handler, but is this really a problem,
430 * only the sysadmin is able to do this.
432 rand_initialize_irq(irq
);
435 spin_lock_irqsave(&irq_action_lock
, flags
);
437 if (check_irq_sharing(bucket
->pil
, irqflags
)) {
438 spin_unlock_irqrestore(&irq_action_lock
, flags
);
442 action
= get_action_slot(bucket
);
444 spin_unlock_irqrestore(&irq_action_lock
, flags
);
448 bucket
->flags
|= IBF_ACTIVE
;
450 if (bucket
!= &pil0_dummy_bucket
) {
451 pending
= bucket
->pending
;
456 action
->handler
= handler
;
457 action
->flags
= irqflags
;
460 action
->dev_id
= dev_id
;
461 put_ino_in_irqaction(action
, irq
);
462 put_smpaff_in_irqaction(action
, CPU_MASK_NONE
);
464 append_irq_action(bucket
->pil
, action
);
468 /* We ate the IVEC already, this makes sure it does not get lost. */
470 atomic_bucket_insert(bucket
);
471 set_softint(1 << bucket
->pil
);
474 spin_unlock_irqrestore(&irq_action_lock
, flags
);
476 if (bucket
!= &pil0_dummy_bucket
)
477 register_irq_proc(__irq_ino(irq
));
485 EXPORT_SYMBOL(request_irq
);
487 static struct irqaction
*unlink_irq_action(unsigned int irq
, void *dev_id
)
489 struct ino_bucket
*bucket
= __bucket(irq
);
490 struct irqaction
*action
, **pp
;
492 pp
= irq_action
+ bucket
->pil
;
494 if (unlikely(!action
))
497 if (unlikely(!action
->handler
)) {
498 printk("Freeing free IRQ %d\n", bucket
->pil
);
502 while (action
&& action
->dev_id
!= dev_id
) {
513 void free_irq(unsigned int irq
, void *dev_id
)
515 struct irqaction
*action
;
516 struct ino_bucket
*bucket
;
519 spin_lock_irqsave(&irq_action_lock
, flags
);
521 action
= unlink_irq_action(irq
, dev_id
);
523 spin_unlock_irqrestore(&irq_action_lock
, flags
);
525 if (unlikely(!action
))
528 synchronize_irq(irq
);
530 spin_lock_irqsave(&irq_action_lock
, flags
);
532 bucket
= __bucket(irq
);
533 if (bucket
!= &pil0_dummy_bucket
) {
534 struct irq_desc
*desc
= bucket
->irq_info
;
535 unsigned long imap
= bucket
->imap
;
538 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
539 struct irqaction
*p
= &desc
->action
[i
];
542 desc
->action_active_mask
&= ~(1 << i
);
547 if (!desc
->action_active_mask
) {
548 /* This unique interrupt source is now inactive. */
549 bucket
->flags
&= ~IBF_ACTIVE
;
551 /* See if any other buckets share this bucket's IMAP
552 * and are still active.
554 for (ent
= 0; ent
< NUM_IVECS
; ent
++) {
555 struct ino_bucket
*bp
= &ivector_table
[ent
];
558 (bp
->flags
& IBF_ACTIVE
) != 0)
562 /* Only disable when no other sub-irq levels of
563 * the same IMAP are active.
565 if (ent
== NUM_IVECS
)
570 spin_unlock_irqrestore(&irq_action_lock
, flags
);
573 EXPORT_SYMBOL(free_irq
);
576 void synchronize_irq(unsigned int irq
)
578 struct ino_bucket
*bucket
= __bucket(irq
);
581 /* The following is how I wish I could implement this.
582 * Unfortunately the ICLR registers are read-only, you can
583 * only write ICLR_foo values to them. To get the current
584 * IRQ status you would need to get at the IRQ diag registers
585 * in the PCI/SBUS controller and the layout of those vary
586 * from one controller to the next, sigh... -DaveM
588 unsigned long iclr
= bucket
->iclr
;
591 u32 tmp
= upa_readl(iclr
);
593 if (tmp
== ICLR_TRANSMIT
||
594 tmp
== ICLR_PENDING
) {
601 /* So we have to do this with a INPROGRESS bit just like x86. */
602 while (bucket
->flags
& IBF_INPROGRESS
)
606 #endif /* CONFIG_SMP */
608 static void process_bucket(int irq
, struct ino_bucket
*bp
, struct pt_regs
*regs
)
610 struct irq_desc
*desc
= bp
->irq_info
;
611 unsigned char flags
= bp
->flags
;
615 bp
->flags
|= IBF_INPROGRESS
;
617 if (unlikely(!(flags
& IBF_ACTIVE
))) {
622 if (desc
->pre_handler
)
623 desc
->pre_handler(bp
,
624 desc
->pre_handler_arg1
,
625 desc
->pre_handler_arg2
);
627 action_mask
= desc
->action_active_mask
;
629 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
630 struct irqaction
*p
= &desc
->action
[i
];
633 if (!(action_mask
& mask
))
636 action_mask
&= ~mask
;
638 if (p
->handler(__irq(bp
), p
->dev_id
, regs
) == IRQ_HANDLED
)
645 if (tlb_type
== hypervisor
) {
646 unsigned int irq
= __irq(bp
);
648 sun4v_intr_setstate(irq
, HV_INTR_STATE_IDLE
);
650 upa_writel(ICLR_IDLE
, bp
->iclr
);
651 /* Test and add entropy */
652 if (random
& SA_SAMPLE_RANDOM
)
653 add_interrupt_randomness(irq
);
657 bp
->flags
&= ~IBF_INPROGRESS
;
660 void handler_irq(int irq
, struct pt_regs
*regs
)
662 struct ino_bucket
*bp
;
663 int cpu
= smp_processor_id();
667 * Check for TICK_INT on level 14 softint.
670 unsigned long clr_mask
= 1 << irq
;
671 unsigned long tick_mask
= tick_ops
->softint_mask
;
673 if ((irq
== 14) && (get_softint() & tick_mask
)) {
675 clr_mask
= tick_mask
;
677 clear_softint(clr_mask
);
680 clear_softint(1 << irq
);
684 kstat_this_cpu
.irqs
[irq
]++;
689 __bucket(xchg32(irq_work(cpu
, irq
), 0)) :
692 bp
= __bucket(xchg32(irq_work(cpu
, irq
), 0));
695 struct ino_bucket
*nbp
= __bucket(bp
->irq_chain
);
698 process_bucket(irq
, bp
, regs
);
704 #ifdef CONFIG_BLK_DEV_FD
705 extern irqreturn_t
floppy_interrupt(int, void *, struct pt_regs
*);;
707 /* XXX No easy way to include asm/floppy.h XXX */
708 extern unsigned char *pdma_vaddr
;
709 extern unsigned long pdma_size
;
710 extern volatile int doing_pdma
;
711 extern unsigned long fdc_status
;
713 irqreturn_t
sparc_floppy_irq(int irq
, void *dev_cookie
, struct pt_regs
*regs
)
715 if (likely(doing_pdma
)) {
716 void __iomem
*stat
= (void __iomem
*) fdc_status
;
717 unsigned char *vaddr
= pdma_vaddr
;
718 unsigned long size
= pdma_size
;
723 if (unlikely(!(val
& 0x80))) {
728 if (unlikely(!(val
& 0x20))) {
736 *vaddr
++ = readb(stat
+ 1);
738 unsigned char data
= *vaddr
++;
741 writeb(data
, stat
+ 1);
749 /* Send Terminal Count pulse to floppy controller. */
750 val
= readb(auxio_register
);
751 val
|= AUXIO_AUX1_FTCNT
;
752 writeb(val
, auxio_register
);
753 val
&= ~AUXIO_AUX1_FTCNT
;
754 writeb(val
, auxio_register
);
760 return floppy_interrupt(irq
, dev_cookie
, regs
);
762 EXPORT_SYMBOL(sparc_floppy_irq
);
765 /* We really don't need these at all on the Sparc. We only have
766 * stubs here because they are exported to modules.
768 unsigned long probe_irq_on(void)
773 EXPORT_SYMBOL(probe_irq_on
);
775 int probe_irq_off(unsigned long mask
)
780 EXPORT_SYMBOL(probe_irq_off
);
783 static int retarget_one_irq(struct irqaction
*p
, int goal_cpu
)
785 struct ino_bucket
*bucket
= get_ino_in_irqaction(p
) + ivector_table
;
786 unsigned long imap
= bucket
->imap
;
788 while (!cpu_online(goal_cpu
)) {
789 if (++goal_cpu
>= NR_CPUS
)
793 if (tlb_type
== hypervisor
) {
794 unsigned int irq
= __irq(bucket
);
796 sun4v_intr_settarget(irq
, goal_cpu
);
797 sun4v_intr_setenabled(irq
, HV_INTR_ENABLED
);
801 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
802 tid
= goal_cpu
<< 26;
803 tid
&= IMAP_AID_SAFARI
;
804 } else if (this_is_starfire
== 0) {
805 tid
= goal_cpu
<< 26;
808 tid
= (starfire_translate(imap
, goal_cpu
) << 26);
811 upa_writel(tid
| IMAP_VALID
, imap
);
815 if (++goal_cpu
>= NR_CPUS
)
817 } while (!cpu_online(goal_cpu
));
822 /* Called from request_irq. */
823 static void distribute_irqs(void)
828 spin_lock_irqsave(&irq_action_lock
, flags
);
832 * Skip the timer at [0], and very rare error/power intrs at [15].
833 * Also level [12], it causes problems on Ex000 systems.
835 for (level
= 1; level
< NR_IRQS
; level
++) {
836 struct irqaction
*p
= irq_action
[level
];
842 cpu
= retarget_one_irq(p
, cpu
);
846 spin_unlock_irqrestore(&irq_action_lock
, flags
);
857 static struct sun5_timer
*prom_timers
;
858 static u64 prom_limit0
, prom_limit1
;
860 static void map_prom_timers(void)
862 unsigned int addr
[3];
865 /* PROM timer node hangs out in the top level of device siblings... */
866 tnode
= prom_finddevice("/counter-timer");
868 /* Assume if node is not present, PROM uses different tick mechanism
869 * which we should not care about.
871 if (tnode
== 0 || tnode
== -1) {
872 prom_timers
= (struct sun5_timer
*) 0;
876 /* If PROM is really using this, it must be mapped by him. */
877 err
= prom_getproperty(tnode
, "address", (char *)addr
, sizeof(addr
));
879 prom_printf("PROM does not have timer mapped, trying to continue.\n");
880 prom_timers
= (struct sun5_timer
*) 0;
883 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
886 static void kill_prom_timer(void)
891 /* Save them away for later. */
892 prom_limit0
= prom_timers
->limit0
;
893 prom_limit1
= prom_timers
->limit1
;
895 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
896 * We turn both off here just to be paranoid.
898 prom_timers
->limit0
= 0;
899 prom_timers
->limit1
= 0;
901 /* Wheee, eat the interrupt packet too... */
902 __asm__
__volatile__(
904 " ldxa [%%g0] %0, %%g1\n"
905 " ldxa [%%g2] %1, %%g1\n"
906 " stxa %%g0, [%%g0] %0\n"
909 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
913 void init_irqwork_curcpu(void)
915 int cpu
= hard_smp_processor_id();
917 memset(__irq_work
+ cpu
, 0, sizeof(struct irq_work_struct
));
920 static void __cpuinit
register_one_mondo(unsigned long paddr
, unsigned long type
)
922 register unsigned long func
__asm__("%o5");
923 register unsigned long arg0
__asm__("%o0");
924 register unsigned long arg1
__asm__("%o1");
925 register unsigned long arg2
__asm__("%o2");
927 func
= HV_FAST_CPU_QCONF
;
930 arg2
= 128; /* XXX Implied by Niagara queue offsets. XXX */
931 __asm__
__volatile__("ta %8"
932 : "=&r" (func
), "=&r" (arg0
),
933 "=&r" (arg1
), "=&r" (arg2
)
934 : "0" (func
), "1" (arg0
),
935 "2" (arg1
), "3" (arg2
),
938 if (arg0
!= HV_EOK
) {
939 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
945 static void __cpuinit
sun4v_register_mondo_queues(int this_cpu
)
947 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
949 register_one_mondo(tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
);
950 register_one_mondo(tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
);
951 register_one_mondo(tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
);
952 register_one_mondo(tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
);
955 static void __cpuinit
alloc_one_mondo(unsigned long *pa_ptr
, int use_bootmem
)
960 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
962 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
965 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
969 *pa_ptr
= __pa(page
);
972 static void __cpuinit
alloc_one_kbuf(unsigned long *pa_ptr
, int use_bootmem
)
977 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
979 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
982 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
986 *pa_ptr
= __pa(page
);
989 static void __cpuinit
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
, int use_bootmem
)
994 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
997 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
999 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
1002 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1006 tb
->cpu_mondo_block_pa
= __pa(page
);
1007 tb
->cpu_list_pa
= __pa(page
+ 64);
1011 /* Allocate and register the mondo and error queues for this cpu. */
1012 void __cpuinit
sun4v_init_mondo_queues(int use_bootmem
)
1014 int cpu
= hard_smp_processor_id();
1015 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1017 alloc_one_mondo(&tb
->cpu_mondo_pa
, use_bootmem
);
1018 alloc_one_mondo(&tb
->dev_mondo_pa
, use_bootmem
);
1019 alloc_one_mondo(&tb
->resum_mondo_pa
, use_bootmem
);
1020 alloc_one_kbuf(&tb
->resum_kernel_buf_pa
, use_bootmem
);
1021 alloc_one_mondo(&tb
->nonresum_mondo_pa
, use_bootmem
);
1022 alloc_one_kbuf(&tb
->nonresum_kernel_buf_pa
, use_bootmem
);
1024 init_cpu_send_mondo_info(tb
, use_bootmem
);
1026 sun4v_register_mondo_queues(cpu
);
1029 /* Only invoked on boot processor. */
1030 void __init
init_IRQ(void)
1034 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
1036 if (tlb_type
== hypervisor
)
1037 sun4v_init_mondo_queues(1);
1039 /* We need to clear any IRQ's pending in the soft interrupt
1040 * registers, a spurious one could be left around from the
1041 * PROM timer which we just disabled.
1043 clear_softint(get_softint());
1045 /* Now that ivector table is initialized, it is safe
1046 * to receive IRQ vector traps. We will normally take
1047 * one or two right now, in case some device PROM used
1048 * to boot us wants to speak to us. We just ignore them.
1050 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
1051 "or %%g1, %0, %%g1\n\t"
1052 "wrpr %%g1, 0x0, %%pstate"
1058 static struct proc_dir_entry
* root_irq_dir
;
1059 static struct proc_dir_entry
* irq_dir
[NUM_IVECS
];
1063 static int irq_affinity_read_proc (char *page
, char **start
, off_t off
,
1064 int count
, int *eof
, void *data
)
1066 struct ino_bucket
*bp
= ivector_table
+ (long)data
;
1067 struct irq_desc
*desc
= bp
->irq_info
;
1068 struct irqaction
*ap
= desc
->action
;
1072 mask
= get_smpaff_in_irqaction(ap
);
1073 if (cpus_empty(mask
))
1074 mask
= cpu_online_map
;
1076 len
= cpumask_scnprintf(page
, count
, mask
);
1077 if (count
- len
< 2)
1079 len
+= sprintf(page
+ len
, "\n");
1083 static inline void set_intr_affinity(int irq
, cpumask_t hw_aff
)
1085 struct ino_bucket
*bp
= ivector_table
+ irq
;
1086 struct irq_desc
*desc
= bp
->irq_info
;
1087 struct irqaction
*ap
= desc
->action
;
1089 /* Users specify affinity in terms of hw cpu ids.
1090 * As soon as we do this, handler_irq() might see and take action.
1092 put_smpaff_in_irqaction(ap
, hw_aff
);
1094 /* Migration is simply done by the next cpu to service this
1099 static int irq_affinity_write_proc (struct file
*file
, const char __user
*buffer
,
1100 unsigned long count
, void *data
)
1102 int irq
= (long) data
, full_count
= count
, err
;
1103 cpumask_t new_value
;
1105 err
= cpumask_parse(buffer
, count
, new_value
);
1108 * Do not allow disabling IRQs completely - it's a too easy
1109 * way to make the system unusable accidentally :-) At least
1110 * one online CPU still has to be targeted.
1112 cpus_and(new_value
, new_value
, cpu_online_map
);
1113 if (cpus_empty(new_value
))
1116 set_intr_affinity(irq
, new_value
);
1123 #define MAX_NAMELEN 10
1125 static void register_irq_proc (unsigned int irq
)
1127 char name
[MAX_NAMELEN
];
1129 if (!root_irq_dir
|| irq_dir
[irq
])
1132 memset(name
, 0, MAX_NAMELEN
);
1133 sprintf(name
, "%x", irq
);
1135 /* create /proc/irq/1234 */
1136 irq_dir
[irq
] = proc_mkdir(name
, root_irq_dir
);
1139 /* XXX SMP affinity not supported on starfire yet. */
1140 if (this_is_starfire
== 0) {
1141 struct proc_dir_entry
*entry
;
1143 /* create /proc/irq/1234/smp_affinity */
1144 entry
= create_proc_entry("smp_affinity", 0600, irq_dir
[irq
]);
1148 entry
->data
= (void *)(long)irq
;
1149 entry
->read_proc
= irq_affinity_read_proc
;
1150 entry
->write_proc
= irq_affinity_write_proc
;
1156 void init_irq_proc (void)
1158 /* create /proc/irq */
1159 root_irq_dir
= proc_mkdir("irq", NULL
);