arch/sparc64/kernel/pci.c

   1 /* pci.c: UltraSparc PCI controller support.
   2  *
   3  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   6  *
   7  * OF tree based PCI bus probing taken from the PowerPC port
   8  * with minor modifications, see there for credits.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/capability.h>
  16 #include <linux/errno.h>
  17 #include <linux/pci.h>
  18 #include <linux/msi.h>
  19 #include <linux/irq.h>
  20 #include <linux/init.h>
  21
  22 #include <asm/uaccess.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/irq.h>
  25 #include <asm/ebus.h>
  26 #include <asm/isa.h>
  27 #include <asm/prom.h>
  28 #include <asm/apb.h>
  29
  30 #include "pci_impl.h"
  31
  32 unsigned long pci_memspace_mask = 0xffffffffUL;
  33
  34 #ifndef CONFIG_PCI
  35 /* A "nop" PCI implementation. */
  36 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
  37                                   unsigned long off, unsigned long len,
  38                                   unsigned char *buf)
  39 {
  40         return 0;
  41 }
  42 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
  43                                    unsigned long off, unsigned long len,
  44                                    unsigned char *buf)
  45 {
  46         return 0;
  47 }
  48 #else
  49
  50 /* List of all PCI controllers found in the system. */
  51 struct pci_pbm_info *pci_pbm_root = NULL;
  52
  53 /* Each PBM found gets a unique index. */
  54 int pci_num_pbms = 0;
  55
  56 volatile int pci_poke_in_progress;
  57 volatile int pci_poke_cpu = -1;
  58 volatile int pci_poke_faulted;
  59
  60 static DEFINE_SPINLOCK(pci_poke_lock);
  61
  62 void pci_config_read8(u8 *addr, u8 *ret)
  63 {
  64         unsigned long flags;
  65         u8 byte;
  66
  67         spin_lock_irqsave(&pci_poke_lock, flags);
  68         pci_poke_cpu = smp_processor_id();
  69         pci_poke_in_progress = 1;
  70         pci_poke_faulted = 0;
  71         __asm__ __volatile__("membar #Sync\n\t"
  72                              "lduba [%1] %2, %0\n\t"
  73                              "membar #Sync"
  74                              : "=r" (byte)
  75                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  76                              : "memory");
  77         pci_poke_in_progress = 0;
  78         pci_poke_cpu = -1;
  79         if (!pci_poke_faulted)
  80                 *ret = byte;
  81         spin_unlock_irqrestore(&pci_poke_lock, flags);
  82 }
  83
  84 void pci_config_read16(u16 *addr, u16 *ret)
  85 {
  86         unsigned long flags;
  87         u16 word;
  88
  89         spin_lock_irqsave(&pci_poke_lock, flags);
  90         pci_poke_cpu = smp_processor_id();
  91         pci_poke_in_progress = 1;
  92         pci_poke_faulted = 0;
  93         __asm__ __volatile__("membar #Sync\n\t"
  94                              "lduha [%1] %2, %0\n\t"
  95                              "membar #Sync"
  96                              : "=r" (word)
  97                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  98                              : "memory");
  99         pci_poke_in_progress = 0;
 100         pci_poke_cpu = -1;
 101         if (!pci_poke_faulted)
 102                 *ret = word;
 103         spin_unlock_irqrestore(&pci_poke_lock, flags);
 104 }
 105
 106 void pci_config_read32(u32 *addr, u32 *ret)
 107 {
 108         unsigned long flags;
 109         u32 dword;
 110
 111         spin_lock_irqsave(&pci_poke_lock, flags);
 112         pci_poke_cpu = smp_processor_id();
 113         pci_poke_in_progress = 1;
 114         pci_poke_faulted = 0;
 115         __asm__ __volatile__("membar #Sync\n\t"
 116                              "lduwa [%1] %2, %0\n\t"
 117                              "membar #Sync"
 118                              : "=r" (dword)
 119                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 120                              : "memory");
 121         pci_poke_in_progress = 0;
 122         pci_poke_cpu = -1;
 123         if (!pci_poke_faulted)
 124                 *ret = dword;
 125         spin_unlock_irqrestore(&pci_poke_lock, flags);
 126 }
 127
 128 void pci_config_write8(u8 *addr, u8 val)
 129 {
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&pci_poke_lock, flags);
 133         pci_poke_cpu = smp_processor_id();
 134         pci_poke_in_progress = 1;
 135         pci_poke_faulted = 0;
 136         __asm__ __volatile__("membar #Sync\n\t"
 137                              "stba %0, [%1] %2\n\t"
 138                              "membar #Sync"
 139                              : /* no outputs */
 140                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 141                              : "memory");
 142         pci_poke_in_progress = 0;
 143         pci_poke_cpu = -1;
 144         spin_unlock_irqrestore(&pci_poke_lock, flags);
 145 }
 146
 147 void pci_config_write16(u16 *addr, u16 val)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&pci_poke_lock, flags);
 152         pci_poke_cpu = smp_processor_id();
 153         pci_poke_in_progress = 1;
 154         pci_poke_faulted = 0;
 155         __asm__ __volatile__("membar #Sync\n\t"
 156                              "stha %0, [%1] %2\n\t"
 157                              "membar #Sync"
 158                              : /* no outputs */
 159                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 160                              : "memory");
 161         pci_poke_in_progress = 0;
 162         pci_poke_cpu = -1;
 163         spin_unlock_irqrestore(&pci_poke_lock, flags);
 164 }
 165
 166 void pci_config_write32(u32 *addr, u32 val)
 167 {
 168         unsigned long flags;
 169
 170         spin_lock_irqsave(&pci_poke_lock, flags);
 171         pci_poke_cpu = smp_processor_id();
 172         pci_poke_in_progress = 1;
 173         pci_poke_faulted = 0;
 174         __asm__ __volatile__("membar #Sync\n\t"
 175                              "stwa %0, [%1] %2\n\t"
 176                              "membar #Sync"
 177                              : /* no outputs */
 178                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 179                              : "memory");
 180         pci_poke_in_progress = 0;
 181         pci_poke_cpu = -1;
 182         spin_unlock_irqrestore(&pci_poke_lock, flags);
 183 }
 184
 185 /* Probe for all PCI controllers in the system. */
 186 extern void sabre_init(struct device_node *, const char *);
 187 extern void psycho_init(struct device_node *, const char *);
 188 extern void schizo_init(struct device_node *, const char *);
 189 extern void schizo_plus_init(struct device_node *, const char *);
 190 extern void tomatillo_init(struct device_node *, const char *);
 191 extern void sun4v_pci_init(struct device_node *, const char *);
 192 extern void fire_pci_init(struct device_node *, const char *);
 193
 194 static struct {
 195         char *model_name;
 196         void (*init)(struct device_node *, const char *);
 197 } pci_controller_table[] __initdata = {
 198         { "SUNW,sabre", sabre_init },
 199         { "pci108e,a000", sabre_init },
 200         { "pci108e,a001", sabre_init },
 201         { "SUNW,psycho", psycho_init },
 202         { "pci108e,8000", psycho_init },
 203         { "SUNW,schizo", schizo_init },
 204         { "pci108e,8001", schizo_init },
 205         { "SUNW,schizo+", schizo_plus_init },
 206         { "pci108e,8002", schizo_plus_init },
 207         { "SUNW,tomatillo", tomatillo_init },
 208         { "pci108e,a801", tomatillo_init },
 209         { "SUNW,sun4v-pci", sun4v_pci_init },
 210         { "pciex108e,80f0", fire_pci_init },
 211 };
 212 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
 213                                   sizeof(pci_controller_table[0]))
 214
 215 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
 216 {
 217         int i;
 218
 219         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 220                 if (!strncmp(model_name,
 221                              pci_controller_table[i].model_name,
 222                              namelen)) {
 223                         pci_controller_table[i].init(dp, model_name);
 224                         return 1;
 225                 }
 226         }
 227
 228         return 0;
 229 }
 230
 231 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
 232 {
 233         int i;
 234
 235         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 236                 if (!strncmp(model_name,
 237                              pci_controller_table[i].model_name,
 238                              namelen)) {
 239                         return 1;
 240                 }
 241         }
 242         return 0;
 243 }
 244
 245 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
 246 {
 247         struct device_node *dp;
 248         int count = 0;
 249
 250         for_each_node_by_name(dp, "pci") {
 251                 struct property *prop;
 252                 int len;
 253
 254                 prop = of_find_property(dp, "model", &len);
 255                 if (!prop)
 256                         prop = of_find_property(dp, "compatible", &len);
 257
 258                 if (prop) {
 259                         const char *model = prop->value;
 260                         int item_len = 0;
 261
 262                         /* Our value may be a multi-valued string in the
 263                          * case of some compatible properties. For sanity,
 264                          * only try the first one.
 265                          */
 266                         while (model[item_len] && len) {
 267                                 len--;
 268                                 item_len++;
 269                         }
 270
 271                         if (handler(model, item_len, dp))
 272                                 count++;
 273                 }
 274         }
 275
 276         return count;
 277 }
 278
 279
 280 /* Is there some PCI controller in the system?  */
 281 int __init pcic_present(void)
 282 {
 283         return pci_controller_scan(pci_is_controller);
 284 }
 285
 286 /* Find each controller in the system, attach and initialize
 287  * software state structure for each and link into the
 288  * pci_pbm_root.  Setup the controller enough such
 289  * that bus scanning can be done.
 290  */
 291 static void __init pci_controller_probe(void)
 292 {
 293         printk("PCI: Probing for controllers.\n");
 294
 295         pci_controller_scan(pci_controller_init);
 296 }
 297
 298 static int ofpci_verbose;
 299
 300 static int __init ofpci_debug(char *str)
 301 {
 302         int val = 0;
 303
 304         get_option(&str, &val);
 305         if (val)
 306                 ofpci_verbose = 1;
 307         return 1;
 308 }
 309
 310 __setup("ofpci_debug=", ofpci_debug);
 311
 312 static unsigned long pci_parse_of_flags(u32 addr0)
 313 {
 314         unsigned long flags = 0;
 315
 316         if (addr0 & 0x02000000) {
 317                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
 318                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
 319                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
 320                 if (addr0 & 0x40000000)
 321                         flags |= IORESOURCE_PREFETCH
 322                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
 323         } else if (addr0 & 0x01000000)
 324                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
 325         return flags;
 326 }
 327
 328 /* The of_device layer has translated all of the assigned-address properties
 329  * into physical address resources, we only have to figure out the register
 330  * mapping.
 331  */
 332 static void pci_parse_of_addrs(struct of_device *op,
 333                                struct device_node *node,
 334                                struct pci_dev *dev)
 335 {
 336         struct resource *op_res;
 337         const u32 *addrs;
 338         int proplen;
 339
 340         addrs = of_get_property(node, "assigned-addresses", &proplen);
 341         if (!addrs)
 342                 return;
 343         if (ofpci_verbose)
 344                 printk("    parse addresses (%d bytes) @ %p\n",
 345                        proplen, addrs);
 346         op_res = &op->resource[0];
 347         for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
 348                 struct resource *res;
 349                 unsigned long flags;
 350                 int i;
 351
 352                 flags = pci_parse_of_flags(addrs[0]);
 353                 if (!flags)
 354                         continue;
 355                 i = addrs[0] & 0xff;
 356                 if (ofpci_verbose)
 357                         printk("  start: %lx, end: %lx, i: %x\n",
 358                                op_res->start, op_res->end, i);
 359
 360                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 361                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 362                 } else if (i == dev->rom_base_reg) {
 363                         res = &dev->resource[PCI_ROM_RESOURCE];
 364                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 365                 } else {
 366                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 367                         continue;
 368                 }
 369                 res->start = op_res->start;
 370                 res->end = op_res->end;
 371                 res->flags = flags;
 372                 res->name = pci_name(dev);
 373         }
 374 }
 375
 376 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 377                                   struct device_node *node,
 378                                   struct pci_bus *bus, int devfn,
 379                                   int host_controller)
 380 {
 381         struct dev_archdata *sd;
 382         struct pci_dev *dev;
 383         const char *type;
 384         u32 class;
 385
 386         dev = alloc_pci_dev();
 387         if (!dev)
 388                 return NULL;
 389
 390         sd = &dev->dev.archdata;
 391         sd->iommu = pbm->iommu;
 392         sd->stc = &pbm->stc;
 393         sd->host_controller = pbm;
 394         sd->prom_node = node;
 395         sd->op = of_find_device_by_node(node);
 396         sd->msi_num = 0xffffffff;
 397
 398         sd = &sd->op->dev.archdata;
 399         sd->iommu = pbm->iommu;
 400         sd->stc = &pbm->stc;
 401
 402         type = of_get_property(node, "device_type", NULL);
 403         if (type == NULL)
 404                 type = "";
 405
 406         if (ofpci_verbose)
 407                 printk("    create device, devfn: %x, type: %s\n",
 408                        devfn, type);
 409
 410         dev->bus = bus;
 411         dev->sysdata = node;
 412         dev->dev.parent = bus->bridge;
 413         dev->dev.bus = &pci_bus_type;
 414         dev->devfn = devfn;
 415         dev->multifunction = 0;         /* maybe a lie? */
 416
 417         if (host_controller) {
 418                 if (tlb_type != hypervisor) {
 419                         pci_read_config_word(dev, PCI_VENDOR_ID,
 420                                              &dev->vendor);
 421                         pci_read_config_word(dev, PCI_DEVICE_ID,
 422                                              &dev->device);
 423                 } else {
 424                         dev->vendor = PCI_VENDOR_ID_SUN;
 425                         dev->device = 0x80f0;
 426                 }
 427                 dev->cfg_size = 256;
 428                 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
 429                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 430                         0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
 431         } else {
 432                 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
 433                 dev->device = of_getintprop_default(node, "device-id", 0xffff);
 434                 dev->subsystem_vendor =
 435                         of_getintprop_default(node, "subsystem-vendor-id", 0);
 436                 dev->subsystem_device =
 437                         of_getintprop_default(node, "subsystem-id", 0);
 438
 439                 dev->cfg_size = pci_cfg_space_size(dev);
 440
 441                 /* We can't actually use the firmware value, we have
 442                  * to read what is in the register right now.  One
 443                  * reason is that in the case of IDE interfaces the
 444                  * firmware can sample the value before the the IDE
 445                  * interface is programmed into native mode.
 446                  */
 447                 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 448                 dev->class = class >> 8;
 449                 dev->revision = class & 0xff;
 450
 451                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 452                         dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 453         }
 454         if (ofpci_verbose)
 455                 printk("    class: 0x%x device name: %s\n",
 456                        dev->class, pci_name(dev));
 457
 458         /* I have seen IDE devices which will not respond to
 459          * the bmdma simplex check reads if bus mastering is
 460          * disabled.
 461          */
 462         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 463                 pci_set_master(dev);
 464
 465         dev->current_state = 4;         /* unknown power state */
 466         dev->error_state = pci_channel_io_normal;
 467
 468         if (host_controller) {
 469                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 470                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 471                 dev->irq = PCI_IRQ_NONE;
 472         } else {
 473                 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 474                         /* a PCI-PCI bridge */
 475                         dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 476                         dev->rom_base_reg = PCI_ROM_ADDRESS1;
 477                 } else if (!strcmp(type, "cardbus")) {
 478                         dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 479                 } else {
 480                         dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 481                         dev->rom_base_reg = PCI_ROM_ADDRESS;
 482
 483                         dev->irq = sd->op->irqs[0];
 484                         if (dev->irq == 0xffffffff)
 485                                 dev->irq = PCI_IRQ_NONE;
 486                 }
 487         }
 488         pci_parse_of_addrs(sd->op, node, dev);
 489
 490         if (ofpci_verbose)
 491                 printk("    adding to system ...\n");
 492
 493         pci_device_add(dev, bus);
 494
 495         return dev;
 496 }
 497
 498 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
 499 {
 500         u32 idx, first, last;
 501
 502         first = 8;
 503         last = 0;
 504         for (idx = 0; idx < 8; idx++) {
 505                 if ((map & (1 << idx)) != 0) {
 506                         if (first > idx)
 507                                 first = idx;
 508                         if (last < idx)
 509                                 last = idx;
 510                 }
 511         }
 512
 513         *first_p = first;
 514         *last_p = last;
 515 }
 516
 517 static void pci_resource_adjust(struct resource *res,
 518                                 struct resource *root)
 519 {
 520         res->start += root->start;
 521         res->end += root->start;
 522 }
 523
 524 /* For PCI bus devices which lack a 'ranges' property we interrogate
 525  * the config space values to set the resources, just like the generic
 526  * Linux PCI probing code does.
 527  */
 528 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
 529                                           struct pci_bus *bus,
 530                                           struct pci_pbm_info *pbm)
 531 {
 532         struct resource *res;
 533         u8 io_base_lo, io_limit_lo;
 534         u16 mem_base_lo, mem_limit_lo;
 535         unsigned long base, limit;
 536
 537         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 538         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 539         base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 540         limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 541
 542         if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 543                 u16 io_base_hi, io_limit_hi;
 544
 545                 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 546                 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 547                 base |= (io_base_hi << 16);
 548                 limit |= (io_limit_hi << 16);
 549         }
 550
 551         res = bus->resource[0];
 552         if (base <= limit) {
 553                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 554                 if (!res->start)
 555                         res->start = base;
 556                 if (!res->end)
 557                         res->end = limit + 0xfff;
 558                 pci_resource_adjust(res, &pbm->io_space);
 559         }
 560
 561         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 562         pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 563         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 564         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 565
 566         res = bus->resource[1];
 567         if (base <= limit) {
 568                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
 569                               IORESOURCE_MEM);
 570                 res->start = base;
 571                 res->end = limit + 0xfffff;
 572                 pci_resource_adjust(res, &pbm->mem_space);
 573         }
 574
 575         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 576         pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 577         base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 578         limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 579
 580         if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 581                 u32 mem_base_hi, mem_limit_hi;
 582
 583                 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 584                 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 585
 586                 /*
 587                  * Some bridges set the base > limit by default, and some
 588                  * (broken) BIOSes do not initialize them.  If we find
 589                  * this, just assume they are not being used.
 590                  */
 591                 if (mem_base_hi <= mem_limit_hi) {
 592                         base |= ((long) mem_base_hi) << 32;
 593                         limit |= ((long) mem_limit_hi) << 32;
 594                 }
 595         }
 596
 597         res = bus->resource[2];
 598         if (base <= limit) {
 599                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
 600                               IORESOURCE_MEM | IORESOURCE_PREFETCH);
 601                 res->start = base;
 602                 res->end = limit + 0xfffff;
 603                 pci_resource_adjust(res, &pbm->mem_space);
 604         }
 605 }
 606
 607 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
 608  * a proper 'ranges' property.
 609  */
 610 static void __devinit apb_fake_ranges(struct pci_dev *dev,
 611                                       struct pci_bus *bus,
 612                                       struct pci_pbm_info *pbm)
 613 {
 614         struct resource *res;
 615         u32 first, last;
 616         u8 map;
 617
 618         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
 619         apb_calc_first_last(map, &first, &last);
 620         res = bus->resource[0];
 621         res->start = (first << 21);
 622         res->end = (last << 21) + ((1 << 21) - 1);
 623         res->flags = IORESOURCE_IO;
 624         pci_resource_adjust(res, &pbm->io_space);
 625
 626         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
 627         apb_calc_first_last(map, &first, &last);
 628         res = bus->resource[1];
 629         res->start = (first << 21);
 630         res->end = (last << 21) + ((1 << 21) - 1);
 631         res->flags = IORESOURCE_MEM;
 632         pci_resource_adjust(res, &pbm->mem_space);
 633 }
 634
 635 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 636                                       struct device_node *node,
 637                                       struct pci_bus *bus);
 638
 639 #define GET_64BIT(prop, i)      ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
 640
 641 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
 642                                          struct device_node *node,
 643                                          struct pci_dev *dev)
 644 {
 645         struct pci_bus *bus;
 646         const u32 *busrange, *ranges;
 647         int len, i, simba;
 648         struct resource *res;
 649         unsigned int flags;
 650         u64 size;
 651
 652         if (ofpci_verbose)
 653                 printk("of_scan_pci_bridge(%s)\n", node->full_name);
 654
 655         /* parse bus-range property */
 656         busrange = of_get_property(node, "bus-range", &len);
 657         if (busrange == NULL || len != 8) {
 658                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 659                        node->full_name);
 660                 return;
 661         }
 662         ranges = of_get_property(node, "ranges", &len);
 663         simba = 0;
 664         if (ranges == NULL) {
 665                 const char *model = of_get_property(node, "model", NULL);
 666                 if (model && !strcmp(model, "SUNW,simba"))
 667                         simba = 1;
 668         }
 669
 670         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 671         if (!bus) {
 672                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 673                        node->full_name);
 674                 return;
 675         }
 676
 677         bus->primary = dev->bus->number;
 678         bus->subordinate = busrange[1];
 679         bus->bridge_ctl = 0;
 680
 681         /* parse ranges property, or cook one up by hand for Simba */
 682         /* PCI #address-cells == 3 and #size-cells == 2 always */
 683         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 684         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 685                 res->flags = 0;
 686                 bus->resource[i] = res;
 687                 ++res;
 688         }
 689         if (simba) {
 690                 apb_fake_ranges(dev, bus, pbm);
 691                 goto after_ranges;
 692         } else if (ranges == NULL) {
 693                 pci_cfg_fake_ranges(dev, bus, pbm);
 694                 goto after_ranges;
 695         }
 696         i = 1;
 697         for (; len >= 32; len -= 32, ranges += 8) {
 698                 struct resource *root;
 699
 700                 flags = pci_parse_of_flags(ranges[0]);
 701                 size = GET_64BIT(ranges, 6);
 702                 if (flags == 0 || size == 0)
 703                         continue;
 704                 if (flags & IORESOURCE_IO) {
 705                         res = bus->resource[0];
 706                         if (res->flags) {
 707                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 708                                        " for bridge %s\n", node->full_name);
 709                                 continue;
 710                         }
 711                         root = &pbm->io_space;
 712                 } else {
 713                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 714                                 printk(KERN_ERR "PCI: too many memory ranges"
 715                                        " for bridge %s\n", node->full_name);
 716                                 continue;
 717                         }
 718                         res = bus->resource[i];
 719                         ++i;
 720                         root = &pbm->mem_space;
 721                 }
 722
 723                 res->start = GET_64BIT(ranges, 1);
 724                 res->end = res->start + size - 1;
 725                 res->flags = flags;
 726
 727                 /* Another way to implement this would be to add an of_device
 728                  * layer routine that can calculate a resource for a given
 729                  * range property value in a PCI device.
 730                  */
 731                 pci_resource_adjust(res, root);
 732         }
 733 after_ranges:
 734         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 735                 bus->number);
 736         if (ofpci_verbose)
 737                 printk("    bus name: %s\n", bus->name);
 738
 739         pci_of_scan_bus(pbm, node, bus);
 740 }
 741
 742 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 743                                       struct device_node *node,
 744                                       struct pci_bus *bus)
 745 {
 746         struct device_node *child;
 747         const u32 *reg;
 748         int reglen, devfn;
 749         struct pci_dev *dev;
 750
 751         if (ofpci_verbose)
 752                 printk("PCI: scan_bus[%s] bus no %d\n",
 753                        node->full_name, bus->number);
 754
 755         child = NULL;
 756         while ((child = of_get_next_child(node, child)) != NULL) {
 757                 if (ofpci_verbose)
 758                         printk("  * %s\n", child->full_name);
 759                 reg = of_get_property(child, "reg", &reglen);
 760                 if (reg == NULL || reglen < 20)
 761                         continue;
 762                 devfn = (reg[0] >> 8) & 0xff;
 763
 764                 /* create a new pci_dev for this device */
 765                 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
 766                 if (!dev)
 767                         continue;
 768                 if (ofpci_verbose)
 769                         printk("PCI: dev header type: %x\n",
 770                                dev->hdr_type);
 771
 772                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 773                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
 774                         of_scan_pci_bridge(pbm, child, dev);
 775         }
 776 }
 777
 778 static ssize_t
 779 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
 780 {
 781         struct pci_dev *pdev;
 782         struct device_node *dp;
 783
 784         pdev = to_pci_dev(dev);
 785         dp = pdev->dev.archdata.prom_node;
 786
 787         return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
 788 }
 789
 790 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
 791
 792 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
 793 {
 794         struct pci_dev *dev;
 795         struct pci_bus *child_bus;
 796         int err;
 797
 798         list_for_each_entry(dev, &bus->devices, bus_list) {
 799                 /* we don't really care if we can create this file or
 800                  * not, but we need to assign the result of the call
 801                  * or the world will fall under alien invasion and
 802                  * everybody will be frozen on a spaceship ready to be
 803                  * eaten on alpha centauri by some green and jelly
 804                  * humanoid.
 805                  */
 806                 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
 807         }
 808         list_for_each_entry(child_bus, &bus->children, node)
 809                 pci_bus_register_of_sysfs(child_bus);
 810 }
 811
 812 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
 813                                  unsigned int devfn,
 814                                  int where, int size,
 815                                  u32 *value)
 816 {
 817         static u8 fake_pci_config[] = {
 818                 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
 819                 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
 820                 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
 821                 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
 822                 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
 823                 0x00, /* Cacheline: 0x00 */
 824                 0x40, /* Latency: 0x40 */
 825                 0x00, /* Header-Type: 0x00 normal */
 826         };
 827
 828         *value = 0;
 829         if (where >= 0 && where < sizeof(fake_pci_config) &&
 830             (where + size) >= 0 &&
 831             (where + size) < sizeof(fake_pci_config) &&
 832             size <= sizeof(u32)) {
 833                 while (size--) {
 834                         *value <<= 8;
 835                         *value |= fake_pci_config[where + size];
 836                 }
 837         }
 838
 839         return PCIBIOS_SUCCESSFUL;
 840 }
 841
 842 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
 843                                   unsigned int devfn,
 844                                   int where, int size,
 845                                   u32 value)
 846 {
 847         return PCIBIOS_SUCCESSFUL;
 848 }
 849
 850 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
 851 {
 852         struct device_node *node = pbm->prom_node;
 853         struct pci_dev *host_pdev;
 854         struct pci_bus *bus;
 855
 856         printk("PCI: Scanning PBM %s\n", node->full_name);
 857
 858         /* XXX parent device? XXX */
 859         bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
 860         if (!bus) {
 861                 printk(KERN_ERR "Failed to create bus for %s\n",
 862                        node->full_name);
 863                 return NULL;
 864         }
 865         bus->secondary = pbm->pci_first_busno;
 866         bus->subordinate = pbm->pci_last_busno;
 867
 868         bus->resource[0] = &pbm->io_space;
 869         bus->resource[1] = &pbm->mem_space;
 870
 871         /* Create the dummy host bridge and link it in.  */
 872         host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
 873         bus->self = host_pdev;
 874
 875         pci_of_scan_bus(pbm, node, bus);
 876         pci_bus_add_devices(bus);
 877         pci_bus_register_of_sysfs(bus);
 878
 879         return bus;
 880 }
 881
 882 static void __init pci_scan_each_controller_bus(void)
 883 {
 884         struct pci_pbm_info *pbm;
 885
 886         for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
 887                 pbm->scan_bus(pbm);
 888 }
 889
 890 extern void power_init(void);
 891
 892 static int __init pcibios_init(void)
 893 {
 894         pci_controller_probe();
 895         if (pci_pbm_root == NULL)
 896                 return 0;
 897
 898         pci_scan_each_controller_bus();
 899
 900         isa_init();
 901         ebus_init();
 902         power_init();
 903
 904         return 0;
 905 }
 906
 907 subsys_initcall(pcibios_init);
 908
 909 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
 910 {
 911         struct pci_pbm_info *pbm = pbus->sysdata;
 912
 913         /* Generic PCI bus probing sets these to point at
 914          * &io{port,mem}_resouce which is wrong for us.
 915          */
 916         pbus->resource[0] = &pbm->io_space;
 917         pbus->resource[1] = &pbm->mem_space;
 918 }
 919
 920 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
 921 {
 922         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 923         struct resource *root = NULL;
 924
 925         if (r->flags & IORESOURCE_IO)
 926                 root = &pbm->io_space;
 927         if (r->flags & IORESOURCE_MEM)
 928                 root = &pbm->mem_space;
 929
 930         return root;
 931 }
 932
 933 void pcibios_update_irq(struct pci_dev *pdev, int irq)
 934 {
 935 }
 936
 937 void pcibios_align_resource(void *data, struct resource *res,
 938                             resource_size_t size, resource_size_t align)
 939 {
 940 }
 941
 942 int pcibios_enable_device(struct pci_dev *dev, int mask)
 943 {
 944         u16 cmd, oldcmd;
 945         int i;
 946
 947         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 948         oldcmd = cmd;
 949
 950         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 951                 struct resource *res = &dev->resource[i];
 952
 953                 /* Only set up the requested stuff */
 954                 if (!(mask & (1<<i)))
 955                         continue;
 956
 957                 if (res->flags & IORESOURCE_IO)
 958                         cmd |= PCI_COMMAND_IO;
 959                 if (res->flags & IORESOURCE_MEM)
 960                         cmd |= PCI_COMMAND_MEMORY;
 961         }
 962
 963         if (cmd != oldcmd) {
 964                 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
 965                        pci_name(dev), cmd);
 966                 /* Enable the appropriate bits in the PCI command register.  */
 967                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 968         }
 969         return 0;
 970 }
 971
 972 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
 973                              struct resource *res)
 974 {
 975         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 976         struct resource zero_res, *root;
 977
 978         zero_res.start = 0;
 979         zero_res.end = 0;
 980         zero_res.flags = res->flags;
 981
 982         if (res->flags & IORESOURCE_IO)
 983                 root = &pbm->io_space;
 984         else
 985                 root = &pbm->mem_space;
 986
 987         pci_resource_adjust(&zero_res, root);
 988
 989         region->start = res->start - zero_res.start;
 990         region->end = res->end - zero_res.start;
 991 }
 992 EXPORT_SYMBOL(pcibios_resource_to_bus);
 993
 994 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
 995                              struct pci_bus_region *region)
 996 {
 997         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 998         struct resource *root;
 999
1000         res->start = region->start;
1001         res->end = region->end;
1002
1003         if (res->flags & IORESOURCE_IO)
1004                 root = &pbm->io_space;
1005         else
1006                 root = &pbm->mem_space;
1007
1008         pci_resource_adjust(res, root);
1009 }
1010 EXPORT_SYMBOL(pcibios_bus_to_resource);
1011
1012 char * __devinit pcibios_setup(char *str)
1013 {
1014         return str;
1015 }
1016
1017 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
1018
1019 /* If the user uses a host-bridge as the PCI device, he may use
1020  * this to perform a raw mmap() of the I/O or MEM space behind
1021  * that controller.
1022  *
1023  * This can be useful for execution of x86 PCI bios initialization code
1024  * on a PCI card, like the xfree86 int10 stuff does.
1025  */
1026 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1027                                       enum pci_mmap_state mmap_state)
1028 {
1029         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1030         unsigned long space_size, user_offset, user_size;
1031
1032         if (mmap_state == pci_mmap_io) {
1033                 space_size = (pbm->io_space.end -
1034                               pbm->io_space.start) + 1;
1035         } else {
1036                 space_size = (pbm->mem_space.end -
1037                               pbm->mem_space.start) + 1;
1038         }
1039
1040         /* Make sure the request is in range. */
1041         user_offset = vma->vm_pgoff << PAGE_SHIFT;
1042         user_size = vma->vm_end - vma->vm_start;
1043
1044         if (user_offset >= space_size ||
1045             (user_offset + user_size) > space_size)
1046                 return -EINVAL;
1047
1048         if (mmap_state == pci_mmap_io) {
1049                 vma->vm_pgoff = (pbm->io_space.start +
1050                                  user_offset) >> PAGE_SHIFT;
1051         } else {
1052                 vma->vm_pgoff = (pbm->mem_space.start +
1053                                  user_offset) >> PAGE_SHIFT;
1054         }
1055
1056         return 0;
1057 }
1058
1059 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
1060  * to the 32-bit pci bus offset for DEV requested by the user.
1061  *
1062  * Basically, the user finds the base address for his device which he wishes
1063  * to mmap.  They read the 32-bit value from the config space base register,
1064  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1065  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1066  *
1067  * Returns negative error code on failure, zero on success.
1068  */
1069 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1070                                   enum pci_mmap_state mmap_state)
1071 {
1072         unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
1073         unsigned long user32 = user_offset & pci_memspace_mask;
1074         unsigned long largest_base, this_base, addr32;
1075         int i;
1076
1077         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1078                 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
1079
1080         /* Figure out which base address this is for. */
1081         largest_base = 0UL;
1082         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1083                 struct resource *rp = &dev->resource[i];
1084
1085                 /* Active? */
1086                 if (!rp->flags)
1087                         continue;
1088
1089                 /* Same type? */
1090                 if (i == PCI_ROM_RESOURCE) {
1091                         if (mmap_state != pci_mmap_mem)
1092                                 continue;
1093                 } else {
1094                         if ((mmap_state == pci_mmap_io &&
1095                              (rp->flags & IORESOURCE_IO) == 0) ||
1096                             (mmap_state == pci_mmap_mem &&
1097                              (rp->flags & IORESOURCE_MEM) == 0))
1098                                 continue;
1099                 }
1100
1101                 this_base = rp->start;
1102
1103                 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
1104
1105                 if (mmap_state == pci_mmap_io)
1106                         addr32 &= 0xffffff;
1107
1108                 if (addr32 <= user32 && this_base > largest_base)
1109                         largest_base = this_base;
1110         }
1111
1112         if (largest_base == 0UL)
1113                 return -EINVAL;
1114
1115         /* Now construct the final physical address. */
1116         if (mmap_state == pci_mmap_io)
1117                 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1118         else
1119                 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1120
1121         return 0;
1122 }
1123
1124 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1125  * mapping.
1126  */
1127 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1128                                             enum pci_mmap_state mmap_state)
1129 {
1130         vma->vm_flags |= (VM_IO | VM_RESERVED);
1131 }
1132
1133 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1134  * device mapping.
1135  */
1136 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1137                                              enum pci_mmap_state mmap_state)
1138 {
1139         /* Our io_remap_pfn_range takes care of this, do nothing.  */
1140 }
1141
1142 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1143  * for this architecture.  The region in the process to map is described by vm_start
1144  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1145  * The pci device structure is provided so that architectures may make mapping
1146  * decisions on a per-device or per-bus basis.
1147  *
1148  * Returns a negative error code on failure, zero on success.
1149  */
1150 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1151                         enum pci_mmap_state mmap_state,
1152                         int write_combine)
1153 {
1154         int ret;
1155
1156         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1157         if (ret < 0)
1158                 return ret;
1159
1160         __pci_mmap_set_flags(dev, vma, mmap_state);
1161         __pci_mmap_set_pgprot(dev, vma, mmap_state);
1162
1163         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1164         ret = io_remap_pfn_range(vma, vma->vm_start,
1165                                  vma->vm_pgoff,
1166                                  vma->vm_end - vma->vm_start,
1167                                  vma->vm_page_prot);
1168         if (ret)
1169                 return ret;
1170
1171         return 0;
1172 }
1173
1174 /* Return the domain nuber for this pci bus */
1175
1176 int pci_domain_nr(struct pci_bus *pbus)
1177 {
1178         struct pci_pbm_info *pbm = pbus->sysdata;
1179         int ret;
1180
1181         if (pbm == NULL || pbm->parent == NULL) {
1182                 ret = -ENXIO;
1183         } else {
1184                 ret = pbm->index;
1185         }
1186
1187         return ret;
1188 }
1189 EXPORT_SYMBOL(pci_domain_nr);
1190
1191 #ifdef CONFIG_PCI_MSI
1192 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1193 {
1194         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1195         int virt_irq;
1196
1197         if (!pbm->setup_msi_irq)
1198                 return -EINVAL;
1199
1200         return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1201 }
1202
1203 void arch_teardown_msi_irq(unsigned int virt_irq)
1204 {
1205         struct msi_desc *entry = get_irq_msi(virt_irq);
1206         struct pci_dev *pdev = entry->dev;
1207         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1208
1209         if (!pbm->teardown_msi_irq)
1210                 return;
1211
1212         return pbm->teardown_msi_irq(virt_irq, pdev);
1213 }
1214 #endif /* !(CONFIG_PCI_MSI) */
1215
1216 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1217 {
1218         return pdev->dev.archdata.prom_node;
1219 }
1220 EXPORT_SYMBOL(pci_device_to_OF_node);
1221
1222 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
1223 {
1224         struct pci_dev *ali_isa_bridge;
1225         u8 val;
1226
1227         /* ALI sound chips generate 31-bits of DMA, a special register
1228          * determines what bit 31 is emitted as.
1229          */
1230         ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
1231                                          PCI_DEVICE_ID_AL_M1533,
1232                                          NULL);
1233
1234         pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
1235         if (set_bit)
1236                 val |= 0x01;
1237         else
1238                 val &= ~0x01;
1239         pci_write_config_byte(ali_isa_bridge, 0x7e, val);
1240         pci_dev_put(ali_isa_bridge);
1241 }
1242
1243 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
1244 {
1245         u64 dma_addr_mask;
1246
1247         if (pdev == NULL) {
1248                 dma_addr_mask = 0xffffffff;
1249         } else {
1250                 struct iommu *iommu = pdev->dev.archdata.iommu;
1251
1252                 dma_addr_mask = iommu->dma_addr_mask;
1253
1254                 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1255                     pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1256                     device_mask == 0x7fffffff) {
1257                         ali_sound_dma_hack(pdev,
1258                                            (dma_addr_mask & 0x80000000) != 0);
1259                         return 1;
1260                 }
1261         }
1262
1263         if (device_mask >= (1UL << 32UL))
1264                 return 0;
1265
1266         return (device_mask & dma_addr_mask) == dma_addr_mask;
1267 }
1268
1269 #endif /* !(CONFIG_PCI) */