arch/sparc64/kernel/pci.c

   1 /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
   2  * pci.c: UltraSparc PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/string.h>
  13 #include <linux/sched.h>
  14 #include <linux/capability.h>
  15 #include <linux/errno.h>
  16 #include <linux/smp_lock.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/uaccess.h>
  20 #include <asm/pbm.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/irq.h>
  23 #include <asm/ebus.h>
  24 #include <asm/isa.h>
  25
  26 unsigned long pci_memspace_mask = 0xffffffffUL;
  27
  28 #ifndef CONFIG_PCI
  29 /* A "nop" PCI implementation. */
  30 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
  31                                   unsigned long off, unsigned long len,
  32                                   unsigned char *buf)
  33 {
  34         return 0;
  35 }
  36 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
  37                                    unsigned long off, unsigned long len,
  38                                    unsigned char *buf)
  39 {
  40         return 0;
  41 }
  42 #else
  43
  44 /* List of all PCI controllers found in the system. */
  45 struct pci_controller_info *pci_controller_root = NULL;
  46
  47 /* Each PCI controller found gets a unique index. */
  48 int pci_num_controllers = 0;
  49
  50 volatile int pci_poke_in_progress;
  51 volatile int pci_poke_cpu = -1;
  52 volatile int pci_poke_faulted;
  53
  54 static DEFINE_SPINLOCK(pci_poke_lock);
  55
  56 void pci_config_read8(u8 *addr, u8 *ret)
  57 {
  58         unsigned long flags;
  59         u8 byte;
  60
  61         spin_lock_irqsave(&pci_poke_lock, flags);
  62         pci_poke_cpu = smp_processor_id();
  63         pci_poke_in_progress = 1;
  64         pci_poke_faulted = 0;
  65         __asm__ __volatile__("membar #Sync\n\t"
  66                              "lduba [%1] %2, %0\n\t"
  67                              "membar #Sync"
  68                              : "=r" (byte)
  69                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  70                              : "memory");
  71         pci_poke_in_progress = 0;
  72         pci_poke_cpu = -1;
  73         if (!pci_poke_faulted)
  74                 *ret = byte;
  75         spin_unlock_irqrestore(&pci_poke_lock, flags);
  76 }
  77
  78 void pci_config_read16(u16 *addr, u16 *ret)
  79 {
  80         unsigned long flags;
  81         u16 word;
  82
  83         spin_lock_irqsave(&pci_poke_lock, flags);
  84         pci_poke_cpu = smp_processor_id();
  85         pci_poke_in_progress = 1;
  86         pci_poke_faulted = 0;
  87         __asm__ __volatile__("membar #Sync\n\t"
  88                              "lduha [%1] %2, %0\n\t"
  89                              "membar #Sync"
  90                              : "=r" (word)
  91                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  92                              : "memory");
  93         pci_poke_in_progress = 0;
  94         pci_poke_cpu = -1;
  95         if (!pci_poke_faulted)
  96                 *ret = word;
  97         spin_unlock_irqrestore(&pci_poke_lock, flags);
  98 }
  99
 100 void pci_config_read32(u32 *addr, u32 *ret)
 101 {
 102         unsigned long flags;
 103         u32 dword;
 104
 105         spin_lock_irqsave(&pci_poke_lock, flags);
 106         pci_poke_cpu = smp_processor_id();
 107         pci_poke_in_progress = 1;
 108         pci_poke_faulted = 0;
 109         __asm__ __volatile__("membar #Sync\n\t"
 110                              "lduwa [%1] %2, %0\n\t"
 111                              "membar #Sync"
 112                              : "=r" (dword)
 113                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 114                              : "memory");
 115         pci_poke_in_progress = 0;
 116         pci_poke_cpu = -1;
 117         if (!pci_poke_faulted)
 118                 *ret = dword;
 119         spin_unlock_irqrestore(&pci_poke_lock, flags);
 120 }
 121
 122 void pci_config_write8(u8 *addr, u8 val)
 123 {
 124         unsigned long flags;
 125
 126         spin_lock_irqsave(&pci_poke_lock, flags);
 127         pci_poke_cpu = smp_processor_id();
 128         pci_poke_in_progress = 1;
 129         pci_poke_faulted = 0;
 130         __asm__ __volatile__("membar #Sync\n\t"
 131                              "stba %0, [%1] %2\n\t"
 132                              "membar #Sync"
 133                              : /* no outputs */
 134                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 135                              : "memory");
 136         pci_poke_in_progress = 0;
 137         pci_poke_cpu = -1;
 138         spin_unlock_irqrestore(&pci_poke_lock, flags);
 139 }
 140
 141 void pci_config_write16(u16 *addr, u16 val)
 142 {
 143         unsigned long flags;
 144
 145         spin_lock_irqsave(&pci_poke_lock, flags);
 146         pci_poke_cpu = smp_processor_id();
 147         pci_poke_in_progress = 1;
 148         pci_poke_faulted = 0;
 149         __asm__ __volatile__("membar #Sync\n\t"
 150                              "stha %0, [%1] %2\n\t"
 151                              "membar #Sync"
 152                              : /* no outputs */
 153                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 154                              : "memory");
 155         pci_poke_in_progress = 0;
 156         pci_poke_cpu = -1;
 157         spin_unlock_irqrestore(&pci_poke_lock, flags);
 158 }
 159
 160 void pci_config_write32(u32 *addr, u32 val)
 161 {
 162         unsigned long flags;
 163
 164         spin_lock_irqsave(&pci_poke_lock, flags);
 165         pci_poke_cpu = smp_processor_id();
 166         pci_poke_in_progress = 1;
 167         pci_poke_faulted = 0;
 168         __asm__ __volatile__("membar #Sync\n\t"
 169                              "stwa %0, [%1] %2\n\t"
 170                              "membar #Sync"
 171                              : /* no outputs */
 172                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 173                              : "memory");
 174         pci_poke_in_progress = 0;
 175         pci_poke_cpu = -1;
 176         spin_unlock_irqrestore(&pci_poke_lock, flags);
 177 }
 178
 179 /* Probe for all PCI controllers in the system. */
 180 extern void sabre_init(int, char *);
 181 extern void psycho_init(int, char *);
 182 extern void schizo_init(int, char *);
 183 extern void schizo_plus_init(int, char *);
 184 extern void tomatillo_init(int, char *);
 185 extern void sun4v_pci_init(int, char *);
 186
 187 static struct {
 188         char *model_name;
 189         void (*init)(int, char *);
 190 } pci_controller_table[] __initdata = {
 191         { "SUNW,sabre", sabre_init },
 192         { "pci108e,a000", sabre_init },
 193         { "pci108e,a001", sabre_init },
 194         { "SUNW,psycho", psycho_init },
 195         { "pci108e,8000", psycho_init },
 196         { "SUNW,schizo", schizo_init },
 197         { "pci108e,8001", schizo_init },
 198         { "SUNW,schizo+", schizo_plus_init },
 199         { "pci108e,8002", schizo_plus_init },
 200         { "SUNW,tomatillo", tomatillo_init },
 201         { "pci108e,a801", tomatillo_init },
 202         { "SUNW,sun4v-pci", sun4v_pci_init },
 203 };
 204 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
 205                                   sizeof(pci_controller_table[0]))
 206
 207 static int __init pci_controller_init(char *model_name, int namelen, int node)
 208 {
 209         int i;
 210
 211         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 212                 if (!strncmp(model_name,
 213                              pci_controller_table[i].model_name,
 214                              namelen)) {
 215                         pci_controller_table[i].init(node, model_name);
 216                         return 1;
 217                 }
 218         }
 219         printk("PCI: Warning unknown controller, model name [%s]\n",
 220                model_name);
 221         printk("PCI: Ignoring controller...\n");
 222
 223         return 0;
 224 }
 225
 226 static int __init pci_is_controller(char *model_name, int namelen, int node)
 227 {
 228         int i;
 229
 230         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 231                 if (!strncmp(model_name,
 232                              pci_controller_table[i].model_name,
 233                              namelen)) {
 234                         return 1;
 235                 }
 236         }
 237         return 0;
 238 }
 239
 240 static int __init pci_controller_scan(int (*handler)(char *, int, int))
 241 {
 242         char namebuf[64];
 243         int node;
 244         int count = 0;
 245
 246         node = prom_getchild(prom_root_node);
 247         while ((node = prom_searchsiblings(node, "pci")) != 0) {
 248                 int len;
 249
 250                 if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 ||
 251                     (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) {
 252                         int item_len = 0;
 253
 254                         /* Our value may be a multi-valued string in the
 255                          * case of some compatible properties. For sanity,
 256                          * only try the first one. */
 257
 258                         while (namebuf[item_len] && len) {
 259                                 len--;
 260                                 item_len++;
 261                         }
 262
 263                         if (handler(namebuf, item_len, node))
 264                                 count++;
 265                 }
 266
 267                 node = prom_getsibling(node);
 268                 if (!node)
 269                         break;
 270         }
 271
 272         return count;
 273 }
 274
 275
 276 /* Is there some PCI controller in the system?  */
 277 int __init pcic_present(void)
 278 {
 279         return pci_controller_scan(pci_is_controller);
 280 }
 281
 282 struct pci_iommu_ops *pci_iommu_ops;
 283 EXPORT_SYMBOL(pci_iommu_ops);
 284
 285 extern struct pci_iommu_ops pci_sun4u_iommu_ops,
 286         pci_sun4v_iommu_ops;
 287
 288 /* Find each controller in the system, attach and initialize
 289  * software state structure for each and link into the
 290  * pci_controller_root.  Setup the controller enough such
 291  * that bus scanning can be done.
 292  */
 293 static void __init pci_controller_probe(void)
 294 {
 295         if (tlb_type == hypervisor)
 296                 pci_iommu_ops = &pci_sun4v_iommu_ops;
 297         else
 298                 pci_iommu_ops = &pci_sun4u_iommu_ops;
 299
 300         printk("PCI: Probing for controllers.\n");
 301
 302         pci_controller_scan(pci_controller_init);
 303 }
 304
 305 static void __init pci_scan_each_controller_bus(void)
 306 {
 307         struct pci_controller_info *p;
 308
 309         for (p = pci_controller_root; p; p = p->next)
 310                 p->scan_bus(p);
 311 }
 312
 313 extern void clock_probe(void);
 314 extern void power_init(void);
 315
 316 static int __init pcibios_init(void)
 317 {
 318         pci_controller_probe();
 319         if (pci_controller_root == NULL)
 320                 return 0;
 321
 322         pci_scan_each_controller_bus();
 323
 324         isa_init();
 325         ebus_init();
 326         clock_probe();
 327         power_init();
 328
 329         return 0;
 330 }
 331
 332 subsys_initcall(pcibios_init);
 333
 334 void pcibios_fixup_bus(struct pci_bus *pbus)
 335 {
 336         struct pci_pbm_info *pbm = pbus->sysdata;
 337
 338         /* Generic PCI bus probing sets these to point at
 339          * &io{port,mem}_resouce which is wrong for us.
 340          */
 341         pbus->resource[0] = &pbm->io_space;
 342         pbus->resource[1] = &pbm->mem_space;
 343 }
 344
 345 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
 346 {
 347         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 348         struct resource *root = NULL;
 349
 350         if (r->flags & IORESOURCE_IO)
 351                 root = &pbm->io_space;
 352         if (r->flags & IORESOURCE_MEM)
 353                 root = &pbm->mem_space;
 354
 355         return root;
 356 }
 357
 358 void pcibios_update_irq(struct pci_dev *pdev, int irq)
 359 {
 360 }
 361
 362 void pcibios_align_resource(void *data, struct resource *res,
 363                             unsigned long size, unsigned long align)
 364 {
 365 }
 366
 367 int pcibios_enable_device(struct pci_dev *pdev, int mask)
 368 {
 369         return 0;
 370 }
 371
 372 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
 373                              struct resource *res)
 374 {
 375         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 376         struct resource zero_res, *root;
 377
 378         zero_res.start = 0;
 379         zero_res.end = 0;
 380         zero_res.flags = res->flags;
 381
 382         if (res->flags & IORESOURCE_IO)
 383                 root = &pbm->io_space;
 384         else
 385                 root = &pbm->mem_space;
 386
 387         pbm->parent->resource_adjust(pdev, &zero_res, root);
 388
 389         region->start = res->start - zero_res.start;
 390         region->end = res->end - zero_res.start;
 391 }
 392 EXPORT_SYMBOL(pcibios_resource_to_bus);
 393
 394 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
 395                              struct pci_bus_region *region)
 396 {
 397         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 398         struct resource *root;
 399
 400         res->start = region->start;
 401         res->end = region->end;
 402
 403         if (res->flags & IORESOURCE_IO)
 404                 root = &pbm->io_space;
 405         else
 406                 root = &pbm->mem_space;
 407
 408         pbm->parent->resource_adjust(pdev, res, root);
 409 }
 410 EXPORT_SYMBOL(pcibios_bus_to_resource);
 411
 412 char * __init pcibios_setup(char *str)
 413 {
 414         return str;
 415 }
 416
 417 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
 418
 419 /* If the user uses a host-bridge as the PCI device, he may use
 420  * this to perform a raw mmap() of the I/O or MEM space behind
 421  * that controller.
 422  *
 423  * This can be useful for execution of x86 PCI bios initialization code
 424  * on a PCI card, like the xfree86 int10 stuff does.
 425  */
 426 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
 427                                       enum pci_mmap_state mmap_state)
 428 {
 429         struct pcidev_cookie *pcp = pdev->sysdata;
 430         struct pci_pbm_info *pbm;
 431         struct pci_controller_info *p;
 432         unsigned long space_size, user_offset, user_size;
 433
 434         if (!pcp)
 435                 return -ENXIO;
 436         pbm = pcp->pbm;
 437         if (!pbm)
 438                 return -ENXIO;
 439
 440         p = pbm->parent;
 441         if (p->pbms_same_domain) {
 442                 unsigned long lowest, highest;
 443
 444                 lowest = ~0UL; highest = 0UL;
 445                 if (mmap_state == pci_mmap_io) {
 446                         if (p->pbm_A.io_space.flags) {
 447                                 lowest = p->pbm_A.io_space.start;
 448                                 highest = p->pbm_A.io_space.end + 1;
 449                         }
 450                         if (p->pbm_B.io_space.flags) {
 451                                 if (lowest > p->pbm_B.io_space.start)
 452                                         lowest = p->pbm_B.io_space.start;
 453                                 if (highest < p->pbm_B.io_space.end + 1)
 454                                         highest = p->pbm_B.io_space.end + 1;
 455                         }
 456                         space_size = highest - lowest;
 457                 } else {
 458                         if (p->pbm_A.mem_space.flags) {
 459                                 lowest = p->pbm_A.mem_space.start;
 460                                 highest = p->pbm_A.mem_space.end + 1;
 461                         }
 462                         if (p->pbm_B.mem_space.flags) {
 463                                 if (lowest > p->pbm_B.mem_space.start)
 464                                         lowest = p->pbm_B.mem_space.start;
 465                                 if (highest < p->pbm_B.mem_space.end + 1)
 466                                         highest = p->pbm_B.mem_space.end + 1;
 467                         }
 468                         space_size = highest - lowest;
 469                 }
 470         } else {
 471                 if (mmap_state == pci_mmap_io) {
 472                         space_size = (pbm->io_space.end -
 473                                       pbm->io_space.start) + 1;
 474                 } else {
 475                         space_size = (pbm->mem_space.end -
 476                                       pbm->mem_space.start) + 1;
 477                 }
 478         }
 479
 480         /* Make sure the request is in range. */
 481         user_offset = vma->vm_pgoff << PAGE_SHIFT;
 482         user_size = vma->vm_end - vma->vm_start;
 483
 484         if (user_offset >= space_size ||
 485             (user_offset + user_size) > space_size)
 486                 return -EINVAL;
 487
 488         if (p->pbms_same_domain) {
 489                 unsigned long lowest = ~0UL;
 490
 491                 if (mmap_state == pci_mmap_io) {
 492                         if (p->pbm_A.io_space.flags)
 493                                 lowest = p->pbm_A.io_space.start;
 494                         if (p->pbm_B.io_space.flags &&
 495                             lowest > p->pbm_B.io_space.start)
 496                                 lowest = p->pbm_B.io_space.start;
 497                 } else {
 498                         if (p->pbm_A.mem_space.flags)
 499                                 lowest = p->pbm_A.mem_space.start;
 500                         if (p->pbm_B.mem_space.flags &&
 501                             lowest > p->pbm_B.mem_space.start)
 502                                 lowest = p->pbm_B.mem_space.start;
 503                 }
 504                 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
 505         } else {
 506                 if (mmap_state == pci_mmap_io) {
 507                         vma->vm_pgoff = (pbm->io_space.start +
 508                                          user_offset) >> PAGE_SHIFT;
 509                 } else {
 510                         vma->vm_pgoff = (pbm->mem_space.start +
 511                                          user_offset) >> PAGE_SHIFT;
 512                 }
 513         }
 514
 515         return 0;
 516 }
 517
 518 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
 519  * to the 32-bit pci bus offset for DEV requested by the user.
 520  *
 521  * Basically, the user finds the base address for his device which he wishes
 522  * to mmap.  They read the 32-bit value from the config space base register,
 523  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 524  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 525  *
 526  * Returns negative error code on failure, zero on success.
 527  */
 528 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
 529                                   enum pci_mmap_state mmap_state)
 530 {
 531         unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
 532         unsigned long user32 = user_offset & pci_memspace_mask;
 533         unsigned long largest_base, this_base, addr32;
 534         int i;
 535
 536         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
 537                 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
 538
 539         /* Figure out which base address this is for. */
 540         largest_base = 0UL;
 541         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 542                 struct resource *rp = &dev->resource[i];
 543
 544                 /* Active? */
 545                 if (!rp->flags)
 546                         continue;
 547
 548                 /* Same type? */
 549                 if (i == PCI_ROM_RESOURCE) {
 550                         if (mmap_state != pci_mmap_mem)
 551                                 continue;
 552                 } else {
 553                         if ((mmap_state == pci_mmap_io &&
 554                              (rp->flags & IORESOURCE_IO) == 0) ||
 555                             (mmap_state == pci_mmap_mem &&
 556                              (rp->flags & IORESOURCE_MEM) == 0))
 557                                 continue;
 558                 }
 559
 560                 this_base = rp->start;
 561
 562                 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
 563
 564                 if (mmap_state == pci_mmap_io)
 565                         addr32 &= 0xffffff;
 566
 567                 if (addr32 <= user32 && this_base > largest_base)
 568                         largest_base = this_base;
 569         }
 570
 571         if (largest_base == 0UL)
 572                 return -EINVAL;
 573
 574         /* Now construct the final physical address. */
 575         if (mmap_state == pci_mmap_io)
 576                 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
 577         else
 578                 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
 579
 580         return 0;
 581 }
 582
 583 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
 584  * mapping.
 585  */
 586 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
 587                                             enum pci_mmap_state mmap_state)
 588 {
 589         vma->vm_flags |= (VM_IO | VM_RESERVED);
 590 }
 591
 592 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 593  * device mapping.
 594  */
 595 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
 596                                              enum pci_mmap_state mmap_state)
 597 {
 598         /* Our io_remap_pfn_range takes care of this, do nothing.  */
 599 }
 600
 601 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
 602  * for this architecture.  The region in the process to map is described by vm_start
 603  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
 604  * The pci device structure is provided so that architectures may make mapping
 605  * decisions on a per-device or per-bus basis.
 606  *
 607  * Returns a negative error code on failure, zero on success.
 608  */
 609 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 610                         enum pci_mmap_state mmap_state,
 611                         int write_combine)
 612 {
 613         int ret;
 614
 615         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
 616         if (ret < 0)
 617                 return ret;
 618
 619         __pci_mmap_set_flags(dev, vma, mmap_state);
 620         __pci_mmap_set_pgprot(dev, vma, mmap_state);
 621
 622         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 623         ret = io_remap_pfn_range(vma, vma->vm_start,
 624                                  vma->vm_pgoff,
 625                                  vma->vm_end - vma->vm_start,
 626                                  vma->vm_page_prot);
 627         if (ret)
 628                 return ret;
 629
 630         return 0;
 631 }
 632
 633 /* Return the domain nuber for this pci bus */
 634
 635 int pci_domain_nr(struct pci_bus *pbus)
 636 {
 637         struct pci_pbm_info *pbm = pbus->sysdata;
 638         int ret;
 639
 640         if (pbm == NULL || pbm->parent == NULL) {
 641                 ret = -ENXIO;
 642         } else {
 643                 struct pci_controller_info *p = pbm->parent;
 644
 645                 ret = p->index;
 646                 if (p->pbms_same_domain == 0)
 647                         ret = ((ret << 1) +
 648                                ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
 649         }
 650
 651         return ret;
 652 }
 653 EXPORT_SYMBOL(pci_domain_nr);
 654
 655 int pcibios_prep_mwi(struct pci_dev *dev)
 656 {
 657         /* We set correct PCI_CACHE_LINE_SIZE register values for every
 658          * device probed on this platform.  So there is nothing to check
 659          * and this always succeeds.
 660          */
 661         return 0;
 662 }
 663
 664 #endif /* !(CONFIG_PCI) */