arch/sparc64/kernel/pci.c

   1 /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
   2  * pci.c: UltraSparc PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/string.h>
  13 #include <linux/sched.h>
  14 #include <linux/capability.h>
  15 #include <linux/errno.h>
  16 #include <linux/smp_lock.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/uaccess.h>
  20 #include <asm/pbm.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/irq.h>
  23 #include <asm/ebus.h>
  24 #include <asm/isa.h>
  25 #include <asm/prom.h>
  26
  27 unsigned long pci_memspace_mask = 0xffffffffUL;
  28
  29 #ifndef CONFIG_PCI
  30 /* A "nop" PCI implementation. */
  31 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
  32                                   unsigned long off, unsigned long len,
  33                                   unsigned char *buf)
  34 {
  35         return 0;
  36 }
  37 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
  38                                    unsigned long off, unsigned long len,
  39                                    unsigned char *buf)
  40 {
  41         return 0;
  42 }
  43 #else
  44
  45 /* List of all PCI controllers found in the system. */
  46 struct pci_controller_info *pci_controller_root = NULL;
  47
  48 /* Each PCI controller found gets a unique index. */
  49 int pci_num_controllers = 0;
  50
  51 volatile int pci_poke_in_progress;
  52 volatile int pci_poke_cpu = -1;
  53 volatile int pci_poke_faulted;
  54
  55 static DEFINE_SPINLOCK(pci_poke_lock);
  56
  57 void pci_config_read8(u8 *addr, u8 *ret)
  58 {
  59         unsigned long flags;
  60         u8 byte;
  61
  62         spin_lock_irqsave(&pci_poke_lock, flags);
  63         pci_poke_cpu = smp_processor_id();
  64         pci_poke_in_progress = 1;
  65         pci_poke_faulted = 0;
  66         __asm__ __volatile__("membar #Sync\n\t"
  67                              "lduba [%1] %2, %0\n\t"
  68                              "membar #Sync"
  69                              : "=r" (byte)
  70                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  71                              : "memory");
  72         pci_poke_in_progress = 0;
  73         pci_poke_cpu = -1;
  74         if (!pci_poke_faulted)
  75                 *ret = byte;
  76         spin_unlock_irqrestore(&pci_poke_lock, flags);
  77 }
  78
  79 void pci_config_read16(u16 *addr, u16 *ret)
  80 {
  81         unsigned long flags;
  82         u16 word;
  83
  84         spin_lock_irqsave(&pci_poke_lock, flags);
  85         pci_poke_cpu = smp_processor_id();
  86         pci_poke_in_progress = 1;
  87         pci_poke_faulted = 0;
  88         __asm__ __volatile__("membar #Sync\n\t"
  89                              "lduha [%1] %2, %0\n\t"
  90                              "membar #Sync"
  91                              : "=r" (word)
  92                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  93                              : "memory");
  94         pci_poke_in_progress = 0;
  95         pci_poke_cpu = -1;
  96         if (!pci_poke_faulted)
  97                 *ret = word;
  98         spin_unlock_irqrestore(&pci_poke_lock, flags);
  99 }
 100
 101 void pci_config_read32(u32 *addr, u32 *ret)
 102 {
 103         unsigned long flags;
 104         u32 dword;
 105
 106         spin_lock_irqsave(&pci_poke_lock, flags);
 107         pci_poke_cpu = smp_processor_id();
 108         pci_poke_in_progress = 1;
 109         pci_poke_faulted = 0;
 110         __asm__ __volatile__("membar #Sync\n\t"
 111                              "lduwa [%1] %2, %0\n\t"
 112                              "membar #Sync"
 113                              : "=r" (dword)
 114                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 115                              : "memory");
 116         pci_poke_in_progress = 0;
 117         pci_poke_cpu = -1;
 118         if (!pci_poke_faulted)
 119                 *ret = dword;
 120         spin_unlock_irqrestore(&pci_poke_lock, flags);
 121 }
 122
 123 void pci_config_write8(u8 *addr, u8 val)
 124 {
 125         unsigned long flags;
 126
 127         spin_lock_irqsave(&pci_poke_lock, flags);
 128         pci_poke_cpu = smp_processor_id();
 129         pci_poke_in_progress = 1;
 130         pci_poke_faulted = 0;
 131         __asm__ __volatile__("membar #Sync\n\t"
 132                              "stba %0, [%1] %2\n\t"
 133                              "membar #Sync"
 134                              : /* no outputs */
 135                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 136                              : "memory");
 137         pci_poke_in_progress = 0;
 138         pci_poke_cpu = -1;
 139         spin_unlock_irqrestore(&pci_poke_lock, flags);
 140 }
 141
 142 void pci_config_write16(u16 *addr, u16 val)
 143 {
 144         unsigned long flags;
 145
 146         spin_lock_irqsave(&pci_poke_lock, flags);
 147         pci_poke_cpu = smp_processor_id();
 148         pci_poke_in_progress = 1;
 149         pci_poke_faulted = 0;
 150         __asm__ __volatile__("membar #Sync\n\t"
 151                              "stha %0, [%1] %2\n\t"
 152                              "membar #Sync"
 153                              : /* no outputs */
 154                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 155                              : "memory");
 156         pci_poke_in_progress = 0;
 157         pci_poke_cpu = -1;
 158         spin_unlock_irqrestore(&pci_poke_lock, flags);
 159 }
 160
 161 void pci_config_write32(u32 *addr, u32 val)
 162 {
 163         unsigned long flags;
 164
 165         spin_lock_irqsave(&pci_poke_lock, flags);
 166         pci_poke_cpu = smp_processor_id();
 167         pci_poke_in_progress = 1;
 168         pci_poke_faulted = 0;
 169         __asm__ __volatile__("membar #Sync\n\t"
 170                              "stwa %0, [%1] %2\n\t"
 171                              "membar #Sync"
 172                              : /* no outputs */
 173                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 174                              : "memory");
 175         pci_poke_in_progress = 0;
 176         pci_poke_cpu = -1;
 177         spin_unlock_irqrestore(&pci_poke_lock, flags);
 178 }
 179
 180 /* Probe for all PCI controllers in the system. */
 181 extern void sabre_init(struct device_node *, const char *);
 182 extern void psycho_init(struct device_node *, const char *);
 183 extern void schizo_init(struct device_node *, const char *);
 184 extern void schizo_plus_init(struct device_node *, const char *);
 185 extern void tomatillo_init(struct device_node *, const char *);
 186 extern void sun4v_pci_init(struct device_node *, const char *);
 187
 188 static struct {
 189         char *model_name;
 190         void (*init)(struct device_node *, const char *);
 191 } pci_controller_table[] __initdata = {
 192         { "SUNW,sabre", sabre_init },
 193         { "pci108e,a000", sabre_init },
 194         { "pci108e,a001", sabre_init },
 195         { "SUNW,psycho", psycho_init },
 196         { "pci108e,8000", psycho_init },
 197         { "SUNW,schizo", schizo_init },
 198         { "pci108e,8001", schizo_init },
 199         { "SUNW,schizo+", schizo_plus_init },
 200         { "pci108e,8002", schizo_plus_init },
 201         { "SUNW,tomatillo", tomatillo_init },
 202         { "pci108e,a801", tomatillo_init },
 203         { "SUNW,sun4v-pci", sun4v_pci_init },
 204 };
 205 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
 206                                   sizeof(pci_controller_table[0]))
 207
 208 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
 209 {
 210         int i;
 211
 212         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 213                 if (!strncmp(model_name,
 214                              pci_controller_table[i].model_name,
 215                              namelen)) {
 216                         pci_controller_table[i].init(dp, model_name);
 217                         return 1;
 218                 }
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
 225 {
 226         int i;
 227
 228         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 229                 if (!strncmp(model_name,
 230                              pci_controller_table[i].model_name,
 231                              namelen)) {
 232                         return 1;
 233                 }
 234         }
 235         return 0;
 236 }
 237
 238 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
 239 {
 240         struct device_node *dp;
 241         int count = 0;
 242
 243         for_each_node_by_name(dp, "pci") {
 244                 struct property *prop;
 245                 int len;
 246
 247                 prop = of_find_property(dp, "model", &len);
 248                 if (!prop)
 249                         prop = of_find_property(dp, "compatible", &len);
 250
 251                 if (prop) {
 252                         const char *model = prop->value;
 253                         int item_len = 0;
 254
 255                         /* Our value may be a multi-valued string in the
 256                          * case of some compatible properties. For sanity,
 257                          * only try the first one.
 258                          */
 259                         while (model[item_len] && len) {
 260                                 len--;
 261                                 item_len++;
 262                         }
 263
 264                         if (handler(model, item_len, dp))
 265                                 count++;
 266                 }
 267         }
 268
 269         return count;
 270 }
 271
 272
 273 /* Is there some PCI controller in the system?  */
 274 int __init pcic_present(void)
 275 {
 276         return pci_controller_scan(pci_is_controller);
 277 }
 278
 279 struct pci_iommu_ops *pci_iommu_ops;
 280 EXPORT_SYMBOL(pci_iommu_ops);
 281
 282 extern struct pci_iommu_ops pci_sun4u_iommu_ops,
 283         pci_sun4v_iommu_ops;
 284
 285 /* Find each controller in the system, attach and initialize
 286  * software state structure for each and link into the
 287  * pci_controller_root.  Setup the controller enough such
 288  * that bus scanning can be done.
 289  */
 290 static void __init pci_controller_probe(void)
 291 {
 292         if (tlb_type == hypervisor)
 293                 pci_iommu_ops = &pci_sun4v_iommu_ops;
 294         else
 295                 pci_iommu_ops = &pci_sun4u_iommu_ops;
 296
 297         printk("PCI: Probing for controllers.\n");
 298
 299         pci_controller_scan(pci_controller_init);
 300 }
 301
 302 static void __init pci_scan_each_controller_bus(void)
 303 {
 304         struct pci_controller_info *p;
 305
 306         for (p = pci_controller_root; p; p = p->next)
 307                 p->scan_bus(p);
 308 }
 309
 310 extern void clock_probe(void);
 311 extern void power_init(void);
 312
 313 static int __init pcibios_init(void)
 314 {
 315         pci_controller_probe();
 316         if (pci_controller_root == NULL)
 317                 return 0;
 318
 319         pci_scan_each_controller_bus();
 320
 321         isa_init();
 322         ebus_init();
 323         clock_probe();
 324         power_init();
 325
 326         return 0;
 327 }
 328
 329 subsys_initcall(pcibios_init);
 330
 331 void pcibios_fixup_bus(struct pci_bus *pbus)
 332 {
 333         struct pci_pbm_info *pbm = pbus->sysdata;
 334
 335         /* Generic PCI bus probing sets these to point at
 336          * &io{port,mem}_resouce which is wrong for us.
 337          */
 338         pbus->resource[0] = &pbm->io_space;
 339         pbus->resource[1] = &pbm->mem_space;
 340 }
 341
 342 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
 343 {
 344         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 345         struct resource *root = NULL;
 346
 347         if (r->flags & IORESOURCE_IO)
 348                 root = &pbm->io_space;
 349         if (r->flags & IORESOURCE_MEM)
 350                 root = &pbm->mem_space;
 351
 352         return root;
 353 }
 354
 355 void pcibios_update_irq(struct pci_dev *pdev, int irq)
 356 {
 357 }
 358
 359 void pcibios_align_resource(void *data, struct resource *res,
 360                             unsigned long size, unsigned long align)
 361 {
 362 }
 363
 364 int pcibios_enable_device(struct pci_dev *pdev, int mask)
 365 {
 366         return 0;
 367 }
 368
 369 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
 370                              struct resource *res)
 371 {
 372         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 373         struct resource zero_res, *root;
 374
 375         zero_res.start = 0;
 376         zero_res.end = 0;
 377         zero_res.flags = res->flags;
 378
 379         if (res->flags & IORESOURCE_IO)
 380                 root = &pbm->io_space;
 381         else
 382                 root = &pbm->mem_space;
 383
 384         pbm->parent->resource_adjust(pdev, &zero_res, root);
 385
 386         region->start = res->start - zero_res.start;
 387         region->end = res->end - zero_res.start;
 388 }
 389 EXPORT_SYMBOL(pcibios_resource_to_bus);
 390
 391 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
 392                              struct pci_bus_region *region)
 393 {
 394         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 395         struct resource *root;
 396
 397         res->start = region->start;
 398         res->end = region->end;
 399
 400         if (res->flags & IORESOURCE_IO)
 401                 root = &pbm->io_space;
 402         else
 403                 root = &pbm->mem_space;
 404
 405         pbm->parent->resource_adjust(pdev, res, root);
 406 }
 407 EXPORT_SYMBOL(pcibios_bus_to_resource);
 408
 409 extern int pci_irq_verbose;
 410
 411 char * __init pcibios_setup(char *str)
 412 {
 413         if (!strcmp(str, "irq_verbose")) {
 414                 pci_irq_verbose = 1;
 415                 return NULL;
 416         }
 417         return str;
 418 }
 419
 420 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
 421
 422 /* If the user uses a host-bridge as the PCI device, he may use
 423  * this to perform a raw mmap() of the I/O or MEM space behind
 424  * that controller.
 425  *
 426  * This can be useful for execution of x86 PCI bios initialization code
 427  * on a PCI card, like the xfree86 int10 stuff does.
 428  */
 429 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
 430                                       enum pci_mmap_state mmap_state)
 431 {
 432         struct pcidev_cookie *pcp = pdev->sysdata;
 433         struct pci_pbm_info *pbm;
 434         struct pci_controller_info *p;
 435         unsigned long space_size, user_offset, user_size;
 436
 437         if (!pcp)
 438                 return -ENXIO;
 439         pbm = pcp->pbm;
 440         if (!pbm)
 441                 return -ENXIO;
 442
 443         p = pbm->parent;
 444         if (p->pbms_same_domain) {
 445                 unsigned long lowest, highest;
 446
 447                 lowest = ~0UL; highest = 0UL;
 448                 if (mmap_state == pci_mmap_io) {
 449                         if (p->pbm_A.io_space.flags) {
 450                                 lowest = p->pbm_A.io_space.start;
 451                                 highest = p->pbm_A.io_space.end + 1;
 452                         }
 453                         if (p->pbm_B.io_space.flags) {
 454                                 if (lowest > p->pbm_B.io_space.start)
 455                                         lowest = p->pbm_B.io_space.start;
 456                                 if (highest < p->pbm_B.io_space.end + 1)
 457                                         highest = p->pbm_B.io_space.end + 1;
 458                         }
 459                         space_size = highest - lowest;
 460                 } else {
 461                         if (p->pbm_A.mem_space.flags) {
 462                                 lowest = p->pbm_A.mem_space.start;
 463                                 highest = p->pbm_A.mem_space.end + 1;
 464                         }
 465                         if (p->pbm_B.mem_space.flags) {
 466                                 if (lowest > p->pbm_B.mem_space.start)
 467                                         lowest = p->pbm_B.mem_space.start;
 468                                 if (highest < p->pbm_B.mem_space.end + 1)
 469                                         highest = p->pbm_B.mem_space.end + 1;
 470                         }
 471                         space_size = highest - lowest;
 472                 }
 473         } else {
 474                 if (mmap_state == pci_mmap_io) {
 475                         space_size = (pbm->io_space.end -
 476                                       pbm->io_space.start) + 1;
 477                 } else {
 478                         space_size = (pbm->mem_space.end -
 479                                       pbm->mem_space.start) + 1;
 480                 }
 481         }
 482
 483         /* Make sure the request is in range. */
 484         user_offset = vma->vm_pgoff << PAGE_SHIFT;
 485         user_size = vma->vm_end - vma->vm_start;
 486
 487         if (user_offset >= space_size ||
 488             (user_offset + user_size) > space_size)
 489                 return -EINVAL;
 490
 491         if (p->pbms_same_domain) {
 492                 unsigned long lowest = ~0UL;
 493
 494                 if (mmap_state == pci_mmap_io) {
 495                         if (p->pbm_A.io_space.flags)
 496                                 lowest = p->pbm_A.io_space.start;
 497                         if (p->pbm_B.io_space.flags &&
 498                             lowest > p->pbm_B.io_space.start)
 499                                 lowest = p->pbm_B.io_space.start;
 500                 } else {
 501                         if (p->pbm_A.mem_space.flags)
 502                                 lowest = p->pbm_A.mem_space.start;
 503                         if (p->pbm_B.mem_space.flags &&
 504                             lowest > p->pbm_B.mem_space.start)
 505                                 lowest = p->pbm_B.mem_space.start;
 506                 }
 507                 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
 508         } else {
 509                 if (mmap_state == pci_mmap_io) {
 510                         vma->vm_pgoff = (pbm->io_space.start +
 511                                          user_offset) >> PAGE_SHIFT;
 512                 } else {
 513                         vma->vm_pgoff = (pbm->mem_space.start +
 514                                          user_offset) >> PAGE_SHIFT;
 515                 }
 516         }
 517
 518         return 0;
 519 }
 520
 521 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
 522  * to the 32-bit pci bus offset for DEV requested by the user.
 523  *
 524  * Basically, the user finds the base address for his device which he wishes
 525  * to mmap.  They read the 32-bit value from the config space base register,
 526  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 527  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 528  *
 529  * Returns negative error code on failure, zero on success.
 530  */
 531 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
 532                                   enum pci_mmap_state mmap_state)
 533 {
 534         unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
 535         unsigned long user32 = user_offset & pci_memspace_mask;
 536         unsigned long largest_base, this_base, addr32;
 537         int i;
 538
 539         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
 540                 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
 541
 542         /* Figure out which base address this is for. */
 543         largest_base = 0UL;
 544         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 545                 struct resource *rp = &dev->resource[i];
 546
 547                 /* Active? */
 548                 if (!rp->flags)
 549                         continue;
 550
 551                 /* Same type? */
 552                 if (i == PCI_ROM_RESOURCE) {
 553                         if (mmap_state != pci_mmap_mem)
 554                                 continue;
 555                 } else {
 556                         if ((mmap_state == pci_mmap_io &&
 557                              (rp->flags & IORESOURCE_IO) == 0) ||
 558                             (mmap_state == pci_mmap_mem &&
 559                              (rp->flags & IORESOURCE_MEM) == 0))
 560                                 continue;
 561                 }
 562
 563                 this_base = rp->start;
 564
 565                 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
 566
 567                 if (mmap_state == pci_mmap_io)
 568                         addr32 &= 0xffffff;
 569
 570                 if (addr32 <= user32 && this_base > largest_base)
 571                         largest_base = this_base;
 572         }
 573
 574         if (largest_base == 0UL)
 575                 return -EINVAL;
 576
 577         /* Now construct the final physical address. */
 578         if (mmap_state == pci_mmap_io)
 579                 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
 580         else
 581                 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
 582
 583         return 0;
 584 }
 585
 586 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
 587  * mapping.
 588  */
 589 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
 590                                             enum pci_mmap_state mmap_state)
 591 {
 592         vma->vm_flags |= (VM_IO | VM_RESERVED);
 593 }
 594
 595 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 596  * device mapping.
 597  */
 598 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
 599                                              enum pci_mmap_state mmap_state)
 600 {
 601         /* Our io_remap_pfn_range takes care of this, do nothing.  */
 602 }
 603
 604 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
 605  * for this architecture.  The region in the process to map is described by vm_start
 606  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
 607  * The pci device structure is provided so that architectures may make mapping
 608  * decisions on a per-device or per-bus basis.
 609  *
 610  * Returns a negative error code on failure, zero on success.
 611  */
 612 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 613                         enum pci_mmap_state mmap_state,
 614                         int write_combine)
 615 {
 616         int ret;
 617
 618         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
 619         if (ret < 0)
 620                 return ret;
 621
 622         __pci_mmap_set_flags(dev, vma, mmap_state);
 623         __pci_mmap_set_pgprot(dev, vma, mmap_state);
 624
 625         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 626         ret = io_remap_pfn_range(vma, vma->vm_start,
 627                                  vma->vm_pgoff,
 628                                  vma->vm_end - vma->vm_start,
 629                                  vma->vm_page_prot);
 630         if (ret)
 631                 return ret;
 632
 633         return 0;
 634 }
 635
 636 /* Return the domain nuber for this pci bus */
 637
 638 int pci_domain_nr(struct pci_bus *pbus)
 639 {
 640         struct pci_pbm_info *pbm = pbus->sysdata;
 641         int ret;
 642
 643         if (pbm == NULL || pbm->parent == NULL) {
 644                 ret = -ENXIO;
 645         } else {
 646                 struct pci_controller_info *p = pbm->parent;
 647
 648                 ret = p->index;
 649                 if (p->pbms_same_domain == 0)
 650                         ret = ((ret << 1) +
 651                                ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
 652         }
 653
 654         return ret;
 655 }
 656 EXPORT_SYMBOL(pci_domain_nr);
 657
 658 int pcibios_prep_mwi(struct pci_dev *dev)
 659 {
 660         /* We set correct PCI_CACHE_LINE_SIZE register values for every
 661          * device probed on this platform.  So there is nothing to check
 662          * and this always succeeds.
 663          */
 664         return 0;
 665 }
 666
 667 #endif /* !(CONFIG_PCI) */