arch/sparc64/kernel/pci_common.c

   1 /* $Id: pci_common.c,v 1.29 2002/02/01 00:56:03 davem Exp $
   2  * pci_common.c: PCI controller common support.
   3  *
   4  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
   5  */
   6
   7 #include <linux/string.h>
   8 #include <linux/slab.h>
   9 #include <linux/init.h>
  10
  11 #include <asm/pbm.h>
  12 #include <asm/prom.h>
  13 #include <asm/of_device.h>
  14
  15 #include "pci_impl.h"
  16
  17 /* Fix self device of BUS and hook it into BUS->self.
  18  * The pci_scan_bus does not do this for the host bridge.
  19  */
  20 void __init pci_fixup_host_bridge_self(struct pci_bus *pbus)
  21 {
  22         struct pci_dev *pdev;
  23
  24         list_for_each_entry(pdev, &pbus->devices, bus_list) {
  25                 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_HOST) {
  26                         pbus->self = pdev;
  27                         return;
  28                 }
  29         }
  30
  31         prom_printf("PCI: Critical error, cannot find host bridge PDEV.\n");
  32         prom_halt();
  33 }
  34
  35 /* Find the OBP PROM device tree node for a PCI device.  */
  36 static struct device_node * __init
  37 find_device_prom_node(struct pci_pbm_info *pbm, struct pci_dev *pdev,
  38                       struct device_node *bus_node,
  39                       struct linux_prom_pci_registers **pregs,
  40                       int *nregs)
  41 {
  42         struct device_node *dp;
  43
  44         *nregs = 0;
  45
  46         /*
  47          * Return the PBM's PROM node in case we are it's PCI device,
  48          * as the PBM's reg property is different to standard PCI reg
  49          * properties. We would delete this device entry otherwise,
  50          * which confuses XFree86's device probing...
  51          */
  52         if ((pdev->bus->number == pbm->pci_bus->number) && (pdev->devfn == 0) &&
  53             (pdev->vendor == PCI_VENDOR_ID_SUN) &&
  54             (pdev->device == PCI_DEVICE_ID_SUN_PBM ||
  55              pdev->device == PCI_DEVICE_ID_SUN_SCHIZO ||
  56              pdev->device == PCI_DEVICE_ID_SUN_TOMATILLO ||
  57              pdev->device == PCI_DEVICE_ID_SUN_SABRE ||
  58              pdev->device == PCI_DEVICE_ID_SUN_HUMMINGBIRD))
  59                 return bus_node;
  60
  61         dp = bus_node->child;
  62         while (dp) {
  63                 struct linux_prom_pci_registers *regs;
  64                 struct property *prop;
  65                 int len;
  66
  67                 prop = of_find_property(dp, "reg", &len);
  68                 if (!prop)
  69                         goto do_next_sibling;
  70
  71                 regs = prop->value;
  72                 if (((regs[0].phys_hi >> 8) & 0xff) == pdev->devfn) {
  73                         *pregs = regs;
  74                         *nregs = len / sizeof(struct linux_prom_pci_registers);
  75                         return dp;
  76                 }
  77
  78         do_next_sibling:
  79                 dp = dp->sibling;
  80         }
  81
  82         return NULL;
  83 }
  84
  85 /* Older versions of OBP on PCI systems encode 64-bit MEM
  86  * space assignments incorrectly, this fixes them up.  We also
  87  * take the opportunity here to hide other kinds of bogus
  88  * assignments.
  89  */
  90 static void __init fixup_obp_assignments(struct pci_dev *pdev,
  91                                          struct pcidev_cookie *pcp)
  92 {
  93         int i;
  94
  95         if (pdev->vendor == PCI_VENDOR_ID_AL &&
  96             (pdev->device == PCI_DEVICE_ID_AL_M7101 ||
  97              pdev->device == PCI_DEVICE_ID_AL_M1533)) {
  98                 int i;
  99
 100                 /* Zap all of the normal resources, they are
 101                  * meaningless and generate bogus resource collision
 102                  * messages.  This is OpenBoot's ill-fated attempt to
 103                  * represent the implicit resources that these devices
 104                  * have.
 105                  */
 106                 pcp->num_prom_assignments = 0;
 107                 for (i = 0; i < 6; i++) {
 108                         pdev->resource[i].start =
 109                                 pdev->resource[i].end =
 110                                 pdev->resource[i].flags = 0;
 111                 }
 112                 pdev->resource[PCI_ROM_RESOURCE].start =
 113                         pdev->resource[PCI_ROM_RESOURCE].end =
 114                         pdev->resource[PCI_ROM_RESOURCE].flags = 0;
 115                 return;
 116         }
 117
 118         for (i = 0; i < pcp->num_prom_assignments; i++) {
 119                 struct linux_prom_pci_registers *ap;
 120                 int space;
 121
 122                 ap = &pcp->prom_assignments[i];
 123                 space = ap->phys_hi >> 24;
 124                 if ((space & 0x3) == 2 &&
 125                     (space & 0x4) != 0) {
 126                         ap->phys_hi &= ~(0x7 << 24);
 127                         ap->phys_hi |= 0x3 << 24;
 128                 }
 129         }
 130 }
 131
 132 /* Fill in the PCI device cookie sysdata for the given
 133  * PCI device.  This cookie is the means by which one
 134  * can get to OBP and PCI controller specific information
 135  * for a PCI device.
 136  */
 137 static void __init pdev_cookie_fillin(struct pci_pbm_info *pbm,
 138                                       struct pci_dev *pdev,
 139                                       struct device_node *bus_node)
 140 {
 141         struct linux_prom_pci_registers *pregs = NULL;
 142         struct pcidev_cookie *pcp;
 143         struct device_node *dp;
 144         struct property *prop;
 145         int nregs, len;
 146
 147         dp = find_device_prom_node(pbm, pdev, bus_node,
 148                                    &pregs, &nregs);
 149         if (!dp) {
 150                 /* If it is not in the OBP device tree then
 151                  * there must be a damn good reason for it.
 152                  *
 153                  * So what we do is delete the device from the
 154                  * PCI device tree completely.  This scenario
 155                  * is seen, for example, on CP1500 for the
 156                  * second EBUS/HappyMeal pair if the external
 157                  * connector for it is not present.
 158                  */
 159                 pci_remove_bus_device(pdev);
 160                 return;
 161         }
 162
 163         pcp = kzalloc(sizeof(*pcp), GFP_ATOMIC);
 164         if (pcp == NULL) {
 165                 prom_printf("PCI_COOKIE: Fatal malloc error, aborting...\n");
 166                 prom_halt();
 167         }
 168         pcp->pbm = pbm;
 169         pcp->prom_node = dp;
 170         pcp->op = of_find_device_by_node(dp);
 171         memcpy(pcp->prom_regs, pregs,
 172                nregs * sizeof(struct linux_prom_pci_registers));
 173         pcp->num_prom_regs = nregs;
 174
 175         /* We can't have the pcidev_cookie assignments be just
 176          * direct pointers into the property value, since they
 177          * are potentially modified by the probing process.
 178          */
 179         prop = of_find_property(dp, "assigned-addresses", &len);
 180         if (!prop) {
 181                 pcp->num_prom_assignments = 0;
 182         } else {
 183                 memcpy(pcp->prom_assignments, prop->value, len);
 184                 pcp->num_prom_assignments =
 185                         (len / sizeof(pcp->prom_assignments[0]));
 186         }
 187
 188         if (strcmp(dp->name, "ebus") == 0) {
 189                 struct linux_prom_ebus_ranges *erng;
 190                 int iter;
 191
 192                 /* EBUS is special... */
 193                 prop = of_find_property(dp, "ranges", &len);
 194                 if (!prop) {
 195                         prom_printf("EBUS: Fatal error, no range property\n");
 196                         prom_halt();
 197                 }
 198                 erng = prop->value;
 199                 len = (len / sizeof(erng[0]));
 200                 for (iter = 0; iter < len; iter++) {
 201                         struct linux_prom_ebus_ranges *ep = &erng[iter];
 202                         struct linux_prom_pci_registers *ap;
 203
 204                         ap = &pcp->prom_assignments[iter];
 205
 206                         ap->phys_hi = ep->parent_phys_hi;
 207                         ap->phys_mid = ep->parent_phys_mid;
 208                         ap->phys_lo = ep->parent_phys_lo;
 209                         ap->size_hi = 0;
 210                         ap->size_lo = ep->size;
 211                 }
 212                 pcp->num_prom_assignments = len;
 213         }
 214
 215         fixup_obp_assignments(pdev, pcp);
 216
 217         pdev->sysdata = pcp;
 218 }
 219
 220 void __init pci_fill_in_pbm_cookies(struct pci_bus *pbus,
 221                                     struct pci_pbm_info *pbm,
 222                                     struct device_node *dp)
 223 {
 224         struct pci_dev *pdev, *pdev_next;
 225         struct pci_bus *this_pbus, *pbus_next;
 226
 227         /* This must be _safe because the cookie fillin
 228            routine can delete devices from the tree.  */
 229         list_for_each_entry_safe(pdev, pdev_next, &pbus->devices, bus_list)
 230                 pdev_cookie_fillin(pbm, pdev, dp);
 231
 232         list_for_each_entry_safe(this_pbus, pbus_next, &pbus->children, node) {
 233                 struct pcidev_cookie *pcp = this_pbus->self->sysdata;
 234
 235                 pci_fill_in_pbm_cookies(this_pbus, pbm, pcp->prom_node);
 236         }
 237 }
 238
 239 static void __init bad_assignment(struct pci_dev *pdev,
 240                                   struct linux_prom_pci_registers *ap,
 241                                   struct resource *res,
 242                                   int do_prom_halt)
 243 {
 244         prom_printf("PCI: Bogus PROM assignment. BUS[%02x] DEVFN[%x]\n",
 245                     pdev->bus->number, pdev->devfn);
 246         if (ap)
 247                 prom_printf("PCI: phys[%08x:%08x:%08x] size[%08x:%08x]\n",
 248                             ap->phys_hi, ap->phys_mid, ap->phys_lo,
 249                             ap->size_hi, ap->size_lo);
 250         if (res)
 251                 prom_printf("PCI: RES[%016lx-->%016lx:(%lx)]\n",
 252                             res->start, res->end, res->flags);
 253         if (do_prom_halt)
 254                 prom_halt();
 255 }
 256
 257 static struct resource *
 258 __init get_root_resource(struct linux_prom_pci_registers *ap,
 259                          struct pci_pbm_info *pbm)
 260 {
 261         int space = (ap->phys_hi >> 24) & 3;
 262
 263         switch (space) {
 264         case 0:
 265                 /* Configuration space, silently ignore it. */
 266                 return NULL;
 267
 268         case 1:
 269                 /* 16-bit IO space */
 270                 return &pbm->io_space;
 271
 272         case 2:
 273                 /* 32-bit MEM space */
 274                 return &pbm->mem_space;
 275
 276         case 3:
 277                 /* 64-bit MEM space, these are allocated out of
 278                  * the 32-bit mem_space range for the PBM, ie.
 279                  * we just zero out the upper 32-bits.
 280                  */
 281                 return &pbm->mem_space;
 282
 283         default:
 284                 printk("PCI: What is resource space %x?\n", space);
 285                 return NULL;
 286         };
 287 }
 288
 289 static struct resource *
 290 __init get_device_resource(struct linux_prom_pci_registers *ap,
 291                            struct pci_dev *pdev)
 292 {
 293         struct resource *res;
 294         int breg = (ap->phys_hi & 0xff);
 295
 296         switch (breg) {
 297         case  PCI_ROM_ADDRESS:
 298                 /* Unfortunately I have seen several cases where
 299                  * buggy FCODE uses a space value of '1' (I/O space)
 300                  * in the register property for the ROM address
 301                  * so disable this sanity check for now.
 302                  */
 303 #if 0
 304         {
 305                 int space = (ap->phys_hi >> 24) & 3;
 306
 307                 /* It had better be MEM space. */
 308                 if (space != 2)
 309                         bad_assignment(pdev, ap, NULL, 0);
 310         }
 311 #endif
 312                 res = &pdev->resource[PCI_ROM_RESOURCE];
 313                 break;
 314
 315         case PCI_BASE_ADDRESS_0:
 316         case PCI_BASE_ADDRESS_1:
 317         case PCI_BASE_ADDRESS_2:
 318         case PCI_BASE_ADDRESS_3:
 319         case PCI_BASE_ADDRESS_4:
 320         case PCI_BASE_ADDRESS_5:
 321                 res = &pdev->resource[(breg - PCI_BASE_ADDRESS_0) / 4];
 322                 break;
 323
 324         default:
 325                 bad_assignment(pdev, ap, NULL, 0);
 326                 res = NULL;
 327                 break;
 328         };
 329
 330         return res;
 331 }
 332
 333 static void __init pdev_record_assignments(struct pci_pbm_info *pbm,
 334                                            struct pci_dev *pdev)
 335 {
 336         struct pcidev_cookie *pcp = pdev->sysdata;
 337         int i;
 338
 339         for (i = 0; i < pcp->num_prom_assignments; i++) {
 340                 struct linux_prom_pci_registers *ap;
 341                 struct resource *root, *res;
 342
 343                 /* The format of this property is specified in
 344                  * the PCI Bus Binding to IEEE1275-1994.
 345                  */
 346                 ap = &pcp->prom_assignments[i];
 347                 root = get_root_resource(ap, pbm);
 348                 res = get_device_resource(ap, pdev);
 349                 if (root == NULL || res == NULL ||
 350                     res->flags == 0)
 351                         continue;
 352
 353                 /* Ok we know which resource this PROM assignment is
 354                  * for, sanity check it.
 355                  */
 356                 if ((res->start & 0xffffffffUL) != ap->phys_lo)
 357                         bad_assignment(pdev, ap, res, 1);
 358
 359                 /* If it is a 64-bit MEM space assignment, verify that
 360                  * the resource is too and that the upper 32-bits match.
 361                  */
 362                 if (((ap->phys_hi >> 24) & 3) == 3) {
 363                         if (((res->flags & IORESOURCE_MEM) == 0) ||
 364                             ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
 365                              != PCI_BASE_ADDRESS_MEM_TYPE_64))
 366                                 bad_assignment(pdev, ap, res, 1);
 367                         if ((res->start >> 32) != ap->phys_mid)
 368                                 bad_assignment(pdev, ap, res, 1);
 369
 370                         /* PBM cannot generate cpu initiated PIOs
 371                          * to the full 64-bit space.  Therefore the
 372                          * upper 32-bits better be zero.  If it is
 373                          * not, just skip it and we will assign it
 374                          * properly ourselves.
 375                          */
 376                         if ((res->start >> 32) != 0UL) {
 377                                 printk(KERN_ERR "PCI: OBP assigns out of range MEM address "
 378                                        "%016lx for region %ld on device %s\n",
 379                                        res->start, (res - &pdev->resource[0]), pci_name(pdev));
 380                                 continue;
 381                         }
 382                 }
 383
 384                 /* Adjust the resource into the physical address space
 385                  * of this PBM.
 386                  */
 387                 pbm->parent->resource_adjust(pdev, res, root);
 388
 389                 if (request_resource(root, res) < 0) {
 390                         int rnum;
 391
 392                         /* OK, there is some conflict.  But this is fine
 393                          * since we'll reassign it in the fixup pass.
 394                          *
 395                          * Do not print the warning for ROM resources
 396                          * as such a conflict is quite common and
 397                          * harmless as the ROM bar is disabled.
 398                          */
 399                         rnum = (res - &pdev->resource[0]);
 400                         if (rnum != PCI_ROM_RESOURCE)
 401                                 printk(KERN_ERR "PCI: Resource collision, "
 402                                        "region %d "
 403                                        "[%016lx:%016lx] of device %s\n",
 404                                        rnum,
 405                                        res->start, res->end,
 406                                        pci_name(pdev));
 407                 }
 408         }
 409 }
 410
 411 void __init pci_record_assignments(struct pci_pbm_info *pbm,
 412                                    struct pci_bus *pbus)
 413 {
 414         struct pci_dev *dev;
 415         struct pci_bus *bus;
 416
 417         list_for_each_entry(dev, &pbus->devices, bus_list)
 418                 pdev_record_assignments(pbm, dev);
 419
 420         list_for_each_entry(bus, &pbus->children, node)
 421                 pci_record_assignments(pbm, bus);
 422 }
 423
 424 /* Return non-zero if PDEV has implicit I/O resources even
 425  * though it may not have an I/O base address register
 426  * active.
 427  */
 428 static int __init has_implicit_io(struct pci_dev *pdev)
 429 {
 430         int class = pdev->class >> 8;
 431
 432         if (class == PCI_CLASS_NOT_DEFINED ||
 433             class == PCI_CLASS_NOT_DEFINED_VGA ||
 434             class == PCI_CLASS_STORAGE_IDE ||
 435             (pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
 436                 return 1;
 437
 438         return 0;
 439 }
 440
 441 static void __init pdev_assign_unassigned(struct pci_pbm_info *pbm,
 442                                           struct pci_dev *pdev)
 443 {
 444         u32 reg;
 445         u16 cmd;
 446         int i, io_seen, mem_seen;
 447
 448         io_seen = mem_seen = 0;
 449         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 450                 struct resource *root, *res;
 451                 unsigned long size, min, max, align;
 452
 453                 res = &pdev->resource[i];
 454
 455                 if (res->flags & IORESOURCE_IO)
 456                         io_seen++;
 457                 else if (res->flags & IORESOURCE_MEM)
 458                         mem_seen++;
 459
 460                 /* If it is already assigned or the resource does
 461                  * not exist, there is nothing to do.
 462                  */
 463                 if (res->parent != NULL || res->flags == 0UL)
 464                         continue;
 465
 466                 /* Determine the root we allocate from. */
 467                 if (res->flags & IORESOURCE_IO) {
 468                         root = &pbm->io_space;
 469                         min = root->start + 0x400UL;
 470                         max = root->end;
 471                 } else {
 472                         root = &pbm->mem_space;
 473                         min = root->start;
 474                         max = min + 0x80000000UL;
 475                 }
 476
 477                 size = res->end - res->start;
 478                 align = size + 1;
 479                 if (allocate_resource(root, res, size + 1, min, max, align, NULL, NULL) < 0) {
 480                         /* uh oh */
 481                         prom_printf("PCI: Failed to allocate resource %d for %s\n",
 482                                     i, pci_name(pdev));
 483                         prom_halt();
 484                 }
 485
 486                 /* Update PCI config space. */
 487                 pbm->parent->base_address_update(pdev, i);
 488         }
 489
 490         /* Special case, disable the ROM.  Several devices
 491          * act funny (ie. do not respond to memory space writes)
 492          * when it is left enabled.  A good example are Qlogic,ISP
 493          * adapters.
 494          */
 495         pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &reg);
 496         reg &= ~PCI_ROM_ADDRESS_ENABLE;
 497         pci_write_config_dword(pdev, PCI_ROM_ADDRESS, reg);
 498
 499         /* If we saw I/O or MEM resources, enable appropriate
 500          * bits in PCI command register.
 501          */
 502         if (io_seen || mem_seen) {
 503                 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
 504                 if (io_seen || has_implicit_io(pdev))
 505                         cmd |= PCI_COMMAND_IO;
 506                 if (mem_seen)
 507                         cmd |= PCI_COMMAND_MEMORY;
 508                 pci_write_config_word(pdev, PCI_COMMAND, cmd);
 509         }
 510
 511         /* If this is a PCI bridge or an IDE controller,
 512          * enable bus mastering.  In the former case also
 513          * set the cache line size correctly.
 514          */
 515         if (((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) ||
 516             (((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) &&
 517              ((pdev->class & 0x80) != 0))) {
 518                 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
 519                 cmd |= PCI_COMMAND_MASTER;
 520                 pci_write_config_word(pdev, PCI_COMMAND, cmd);
 521
 522                 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 523                         pci_write_config_byte(pdev,
 524                                               PCI_CACHE_LINE_SIZE,
 525                                               (64 / sizeof(u32)));
 526         }
 527 }
 528
 529 void __init pci_assign_unassigned(struct pci_pbm_info *pbm,
 530                                   struct pci_bus *pbus)
 531 {
 532         struct pci_dev *dev;
 533         struct pci_bus *bus;
 534
 535         list_for_each_entry(dev, &pbus->devices, bus_list)
 536                 pdev_assign_unassigned(pbm, dev);
 537
 538         list_for_each_entry(bus, &pbus->children, node)
 539                 pci_assign_unassigned(pbm, bus);
 540 }
 541
 542 static void __init pdev_fixup_irq(struct pci_dev *pdev)
 543 {
 544         struct pcidev_cookie *pcp = pdev->sysdata;
 545         struct of_device *op = pcp->op;
 546
 547         if (op->irqs[0] == 0xffffffff) {
 548                 pdev->irq = PCI_IRQ_NONE;
 549                 return;
 550         }
 551
 552         pdev->irq = op->irqs[0];
 553
 554         pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,
 555                               pdev->irq & PCI_IRQ_INO);
 556 }
 557
 558 void __init pci_fixup_irq(struct pci_pbm_info *pbm,
 559                           struct pci_bus *pbus)
 560 {
 561         struct pci_dev *dev;
 562         struct pci_bus *bus;
 563
 564         list_for_each_entry(dev, &pbus->devices, bus_list)
 565                 pdev_fixup_irq(dev);
 566
 567         list_for_each_entry(bus, &pbus->children, node)
 568                 pci_fixup_irq(pbm, bus);
 569 }
 570
 571 static void pdev_setup_busmastering(struct pci_dev *pdev, int is_66mhz)
 572 {
 573         u16 cmd;
 574         u8 hdr_type, min_gnt, ltimer;
 575
 576         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
 577         cmd |= PCI_COMMAND_MASTER;
 578         pci_write_config_word(pdev, PCI_COMMAND, cmd);
 579
 580         /* Read it back, if the mastering bit did not
 581          * get set, the device does not support bus
 582          * mastering so we have nothing to do here.
 583          */
 584         pci_read_config_word(pdev, PCI_COMMAND, &cmd);
 585         if ((cmd & PCI_COMMAND_MASTER) == 0)
 586                 return;
 587
 588         /* Set correct cache line size, 64-byte on all
 589          * Sparc64 PCI systems.  Note that the value is
 590          * measured in 32-bit words.
 591          */
 592         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
 593                               64 / sizeof(u32));
 594
 595         pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr_type);
 596         hdr_type &= ~0x80;
 597         if (hdr_type != PCI_HEADER_TYPE_NORMAL)
 598                 return;
 599
 600         /* If the latency timer is already programmed with a non-zero
 601          * value, assume whoever set it (OBP or whoever) knows what
 602          * they are doing.
 603          */
 604         pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ltimer);
 605         if (ltimer != 0)
 606                 return;
 607
 608         /* XXX Since I'm tipping off the min grant value to
 609          * XXX choose a suitable latency timer value, I also
 610          * XXX considered making use of the max latency value
 611          * XXX as well.  Unfortunately I've seen too many bogusly
 612          * XXX low settings for it to the point where it lacks
 613          * XXX any usefulness.  In one case, an ethernet card
 614          * XXX claimed a min grant of 10 and a max latency of 5.
 615          * XXX Now, if I had two such cards on the same bus I
 616          * XXX could not set the desired burst period (calculated
 617          * XXX from min grant) without violating the max latency
 618          * XXX bound.  Duh...
 619          * XXX
 620          * XXX I blame dumb PC bios implementors for stuff like
 621          * XXX this, most of them don't even try to do something
 622          * XXX sensible with latency timer values and just set some
 623          * XXX default value (usually 32) into every device.
 624          */
 625
 626         pci_read_config_byte(pdev, PCI_MIN_GNT, &min_gnt);
 627
 628         if (min_gnt == 0) {
 629                 /* If no min_gnt setting then use a default
 630                  * value.
 631                  */
 632                 if (is_66mhz)
 633                         ltimer = 16;
 634                 else
 635                         ltimer = 32;
 636         } else {
 637                 int shift_factor;
 638
 639                 if (is_66mhz)
 640                         shift_factor = 2;
 641                 else
 642                         shift_factor = 3;
 643
 644                 /* Use a default value when the min_gnt value
 645                  * is erroneously high.
 646                  */
 647                 if (((unsigned int) min_gnt << shift_factor) > 512 ||
 648                     ((min_gnt << shift_factor) & 0xff) == 0) {
 649                         ltimer = 8 << shift_factor;
 650                 } else {
 651                         ltimer = min_gnt << shift_factor;
 652                 }
 653         }
 654
 655         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ltimer);
 656 }
 657
 658 void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
 659                                      struct pci_bus *pbus)
 660 {
 661         struct pci_dev *pdev;
 662         int all_are_66mhz;
 663         u16 status;
 664
 665         if (pbm->is_66mhz_capable == 0) {
 666                 all_are_66mhz = 0;
 667                 goto out;
 668         }
 669
 670         all_are_66mhz = 1;
 671         list_for_each_entry(pdev, &pbus->devices, bus_list) {
 672                 pci_read_config_word(pdev, PCI_STATUS, &status);
 673                 if (!(status & PCI_STATUS_66MHZ)) {
 674                         all_are_66mhz = 0;
 675                         break;
 676                 }
 677         }
 678 out:
 679         pbm->all_devs_66mhz = all_are_66mhz;
 680
 681         printk("PCI%d(PBM%c): Bus running at %dMHz\n",
 682                pbm->parent->index,
 683                (pbm == &pbm->parent->pbm_A) ? 'A' : 'B',
 684                (all_are_66mhz ? 66 : 33));
 685 }
 686
 687 void pci_setup_busmastering(struct pci_pbm_info *pbm,
 688                             struct pci_bus *pbus)
 689 {
 690         struct pci_dev *dev;
 691         struct pci_bus *bus;
 692         int is_66mhz;
 693
 694         is_66mhz = pbm->is_66mhz_capable && pbm->all_devs_66mhz;
 695
 696         list_for_each_entry(dev, &pbus->devices, bus_list)
 697                 pdev_setup_busmastering(dev, is_66mhz);
 698
 699         list_for_each_entry(bus, &pbus->children, node)
 700                 pci_setup_busmastering(pbm, bus);
 701 }
 702
 703 void pci_register_legacy_regions(struct resource *io_res,
 704                                  struct resource *mem_res)
 705 {
 706         struct resource *p;
 707
 708         /* VGA Video RAM. */
 709         p = kzalloc(sizeof(*p), GFP_KERNEL);
 710         if (!p)
 711                 return;
 712
 713         p->name = "Video RAM area";
 714         p->start = mem_res->start + 0xa0000UL;
 715         p->end = p->start + 0x1ffffUL;
 716         p->flags = IORESOURCE_BUSY;
 717         request_resource(mem_res, p);
 718
 719         p = kzalloc(sizeof(*p), GFP_KERNEL);
 720         if (!p)
 721                 return;
 722
 723         p->name = "System ROM";
 724         p->start = mem_res->start + 0xf0000UL;
 725         p->end = p->start + 0xffffUL;
 726         p->flags = IORESOURCE_BUSY;
 727         request_resource(mem_res, p);
 728
 729         p = kzalloc(sizeof(*p), GFP_KERNEL);
 730         if (!p)
 731                 return;
 732
 733         p->name = "Video ROM";
 734         p->start = mem_res->start + 0xc0000UL;
 735         p->end = p->start + 0x7fffUL;
 736         p->flags = IORESOURCE_BUSY;
 737         request_resource(mem_res, p);
 738 }
 739
 740 /* Generic helper routines for PCI error reporting. */
 741 void pci_scan_for_target_abort(struct pci_controller_info *p,
 742                                struct pci_pbm_info *pbm,
 743                                struct pci_bus *pbus)
 744 {
 745         struct pci_dev *pdev;
 746         struct pci_bus *bus;
 747
 748         list_for_each_entry(pdev, &pbus->devices, bus_list) {
 749                 u16 status, error_bits;
 750
 751                 pci_read_config_word(pdev, PCI_STATUS, &status);
 752                 error_bits =
 753                         (status & (PCI_STATUS_SIG_TARGET_ABORT |
 754                                    PCI_STATUS_REC_TARGET_ABORT));
 755                 if (error_bits) {
 756                         pci_write_config_word(pdev, PCI_STATUS, error_bits);
 757                         printk("PCI%d(PBM%c): Device [%s] saw Target Abort [%016x]\n",
 758                                p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
 759                                pci_name(pdev), status);
 760                 }
 761         }
 762
 763         list_for_each_entry(bus, &pbus->children, node)
 764                 pci_scan_for_target_abort(p, pbm, bus);
 765 }
 766
 767 void pci_scan_for_master_abort(struct pci_controller_info *p,
 768                                struct pci_pbm_info *pbm,
 769                                struct pci_bus *pbus)
 770 {
 771         struct pci_dev *pdev;
 772         struct pci_bus *bus;
 773
 774         list_for_each_entry(pdev, &pbus->devices, bus_list) {
 775                 u16 status, error_bits;
 776
 777                 pci_read_config_word(pdev, PCI_STATUS, &status);
 778                 error_bits =
 779                         (status & (PCI_STATUS_REC_MASTER_ABORT));
 780                 if (error_bits) {
 781                         pci_write_config_word(pdev, PCI_STATUS, error_bits);
 782                         printk("PCI%d(PBM%c): Device [%s] received Master Abort [%016x]\n",
 783                                p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
 784                                pci_name(pdev), status);
 785                 }
 786         }
 787
 788         list_for_each_entry(bus, &pbus->children, node)
 789                 pci_scan_for_master_abort(p, pbm, bus);
 790 }
 791
 792 void pci_scan_for_parity_error(struct pci_controller_info *p,
 793                                struct pci_pbm_info *pbm,
 794                                struct pci_bus *pbus)
 795 {
 796         struct pci_dev *pdev;
 797         struct pci_bus *bus;
 798
 799         list_for_each_entry(pdev, &pbus->devices, bus_list) {
 800                 u16 status, error_bits;
 801
 802                 pci_read_config_word(pdev, PCI_STATUS, &status);
 803                 error_bits =
 804                         (status & (PCI_STATUS_PARITY |
 805                                    PCI_STATUS_DETECTED_PARITY));
 806                 if (error_bits) {
 807                         pci_write_config_word(pdev, PCI_STATUS, error_bits);
 808                         printk("PCI%d(PBM%c): Device [%s] saw Parity Error [%016x]\n",
 809                                p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
 810                                pci_name(pdev), status);
 811                 }
 812         }
 813
 814         list_for_each_entry(bus, &pbus->children, node)
 815                 pci_scan_for_parity_error(p, pbm, bus);
 816 }