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[SPARC64] PCI: Use common routine to fetch PBM properties.
[deliverable/linux.git] / arch / sparc64 / kernel / pci_psycho.c
1 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14
15 #include <asm/pbm.h>
16 #include <asm/iommu.h>
17 #include <asm/irq.h>
18 #include <asm/starfire.h>
19 #include <asm/prom.h>
20 #include <asm/of_device.h>
21
22 #include "pci_impl.h"
23 #include "iommu_common.h"
24
25 /* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29 #define psycho_read(__reg) \
30 ({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36 })
37 #define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44 /* Misc. PSYCHO PCI controller register offsets and definitions. */
45 #define PSYCHO_CONTROL 0x0010UL
46 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55 #define PSYCHO_PCIA_CTRL 0x2000UL
56 #define PSYCHO_PCIB_CTRL 0x4000UL
57 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
69
70 /* U2P Programmer's Manual, page 13-55, configuration space
71 * address format:
72 *
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
77 */
78 #define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
84
85 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
86 unsigned char bus,
87 unsigned int devfn,
88 int where)
89 {
90 if (!pbm)
91 return NULL;
92 return (void *)
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
95 }
96
97 static int psycho_out_of_range(struct pci_pbm_info *pbm,
98 unsigned char bus,
99 unsigned char devfn)
100 {
101 return ((pbm->parent == 0) ||
102 ((pbm == &pbm->parent->pbm_B) &&
103 (bus == pbm->pci_first_busno) &&
104 PCI_SLOT(devfn) > 8) ||
105 ((pbm == &pbm->parent->pbm_A) &&
106 (bus == pbm->pci_first_busno) &&
107 PCI_SLOT(devfn) > 8));
108 }
109
110 /* PSYCHO PCI configuration space accessors. */
111
112 static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
113 int where, int size, u32 *value)
114 {
115 struct pci_pbm_info *pbm = bus_dev->sysdata;
116 unsigned char bus = bus_dev->number;
117 u32 *addr;
118 u16 tmp16;
119 u8 tmp8;
120
121 if (bus_dev == pbm->pci_bus && devfn == 0x00)
122 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
123 size, value);
124
125 switch (size) {
126 case 1:
127 *value = 0xff;
128 break;
129 case 2:
130 *value = 0xffff;
131 break;
132 case 4:
133 *value = 0xffffffff;
134 break;
135 }
136
137 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
138 if (!addr)
139 return PCIBIOS_SUCCESSFUL;
140
141 if (psycho_out_of_range(pbm, bus, devfn))
142 return PCIBIOS_SUCCESSFUL;
143 switch (size) {
144 case 1:
145 pci_config_read8((u8 *)addr, &tmp8);
146 *value = (u32) tmp8;
147 break;
148
149 case 2:
150 if (where & 0x01) {
151 printk("pci_read_config_word: misaligned reg [%x]\n",
152 where);
153 return PCIBIOS_SUCCESSFUL;
154 }
155 pci_config_read16((u16 *)addr, &tmp16);
156 *value = (u32) tmp16;
157 break;
158
159 case 4:
160 if (where & 0x03) {
161 printk("pci_read_config_dword: misaligned reg [%x]\n",
162 where);
163 return PCIBIOS_SUCCESSFUL;
164 }
165 pci_config_read32(addr, value);
166 break;
167 }
168 return PCIBIOS_SUCCESSFUL;
169 }
170
171 static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
172 int where, int size, u32 value)
173 {
174 struct pci_pbm_info *pbm = bus_dev->sysdata;
175 unsigned char bus = bus_dev->number;
176 u32 *addr;
177
178 if (bus_dev == pbm->pci_bus && devfn == 0x00)
179 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
180 size, value);
181 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
182 if (!addr)
183 return PCIBIOS_SUCCESSFUL;
184
185 if (psycho_out_of_range(pbm, bus, devfn))
186 return PCIBIOS_SUCCESSFUL;
187
188 switch (size) {
189 case 1:
190 pci_config_write8((u8 *)addr, value);
191 break;
192
193 case 2:
194 if (where & 0x01) {
195 printk("pci_write_config_word: misaligned reg [%x]\n",
196 where);
197 return PCIBIOS_SUCCESSFUL;
198 }
199 pci_config_write16((u16 *)addr, value);
200 break;
201
202 case 4:
203 if (where & 0x03) {
204 printk("pci_write_config_dword: misaligned reg [%x]\n",
205 where);
206 return PCIBIOS_SUCCESSFUL;
207 }
208 pci_config_write32(addr, value);
209 }
210 return PCIBIOS_SUCCESSFUL;
211 }
212
213 static struct pci_ops psycho_ops = {
214 .read = psycho_read_pci_cfg,
215 .write = psycho_write_pci_cfg,
216 };
217
218 /* PSYCHO error handling support. */
219 enum psycho_error_type {
220 UE_ERR, CE_ERR, PCI_ERR
221 };
222
223 /* Helper function of IOMMU error checking, which checks out
224 * the state of the streaming buffers. The IOMMU lock is
225 * held when this is called.
226 *
227 * For the PCI error case we know which PBM (and thus which
228 * streaming buffer) caused the error, but for the uncorrectable
229 * error case we do not. So we always check both streaming caches.
230 */
231 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
232 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
233 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
234 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
235 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
236 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
237 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
238 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
239 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
240 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
241 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
242 #define PSYCHO_STC_DATA_A 0xb000UL
243 #define PSYCHO_STC_DATA_B 0xc000UL
244 #define PSYCHO_STC_ERR_A 0xb400UL
245 #define PSYCHO_STC_ERR_B 0xc400UL
246 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
247 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
248 #define PSYCHO_STC_TAG_A 0xb800UL
249 #define PSYCHO_STC_TAG_B 0xc800UL
250 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
251 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
252 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
253 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
254 #define PSYCHO_STC_LINE_A 0xb900UL
255 #define PSYCHO_STC_LINE_B 0xc900UL
256 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
257 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
258 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
259 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
260 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
261 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
262
263 static DEFINE_SPINLOCK(stc_buf_lock);
264 static unsigned long stc_error_buf[128];
265 static unsigned long stc_tag_buf[16];
266 static unsigned long stc_line_buf[16];
267
268 static void __psycho_check_one_stc(struct pci_controller_info *p,
269 struct pci_pbm_info *pbm,
270 int is_pbm_a)
271 {
272 struct strbuf *strbuf = &pbm->stc;
273 unsigned long regbase = p->pbm_A.controller_regs;
274 unsigned long err_base, tag_base, line_base;
275 u64 control;
276 int i;
277
278 if (is_pbm_a) {
279 err_base = regbase + PSYCHO_STC_ERR_A;
280 tag_base = regbase + PSYCHO_STC_TAG_A;
281 line_base = regbase + PSYCHO_STC_LINE_A;
282 } else {
283 err_base = regbase + PSYCHO_STC_ERR_B;
284 tag_base = regbase + PSYCHO_STC_TAG_B;
285 line_base = regbase + PSYCHO_STC_LINE_B;
286 }
287
288 spin_lock(&stc_buf_lock);
289
290 /* This is __REALLY__ dangerous. When we put the
291 * streaming buffer into diagnostic mode to probe
292 * it's tags and error status, we _must_ clear all
293 * of the line tag valid bits before re-enabling
294 * the streaming buffer. If any dirty data lives
295 * in the STC when we do this, we will end up
296 * invalidating it before it has a chance to reach
297 * main memory.
298 */
299 control = psycho_read(strbuf->strbuf_control);
300 psycho_write(strbuf->strbuf_control,
301 (control | PSYCHO_STRBUF_CTRL_DENAB));
302 for (i = 0; i < 128; i++) {
303 unsigned long val;
304
305 val = psycho_read(err_base + (i * 8UL));
306 psycho_write(err_base + (i * 8UL), 0UL);
307 stc_error_buf[i] = val;
308 }
309 for (i = 0; i < 16; i++) {
310 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
311 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
312 psycho_write(tag_base + (i * 8UL), 0UL);
313 psycho_write(line_base + (i * 8UL), 0UL);
314 }
315
316 /* OK, state is logged, exit diagnostic mode. */
317 psycho_write(strbuf->strbuf_control, control);
318
319 for (i = 0; i < 16; i++) {
320 int j, saw_error, first, last;
321
322 saw_error = 0;
323 first = i * 8;
324 last = first + 8;
325 for (j = first; j < last; j++) {
326 unsigned long errval = stc_error_buf[j];
327 if (errval != 0) {
328 saw_error++;
329 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
330 p->index,
331 (is_pbm_a ? 'A' : 'B'),
332 j,
333 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
334 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
335 }
336 }
337 if (saw_error != 0) {
338 unsigned long tagval = stc_tag_buf[i];
339 unsigned long lineval = stc_line_buf[i];
340 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
341 p->index,
342 (is_pbm_a ? 'A' : 'B'),
343 i,
344 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
345 (tagval & PSYCHO_STCTAG_VPN),
346 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
347 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
348 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
349 "V(%d)FOFN(%d)]\n",
350 p->index,
351 (is_pbm_a ? 'A' : 'B'),
352 i,
353 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
354 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
355 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
356 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
357 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
358 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
359 }
360 }
361
362 spin_unlock(&stc_buf_lock);
363 }
364
365 static void __psycho_check_stc_error(struct pci_controller_info *p,
366 unsigned long afsr,
367 unsigned long afar,
368 enum psycho_error_type type)
369 {
370 struct pci_pbm_info *pbm;
371
372 pbm = &p->pbm_A;
373 if (pbm->stc.strbuf_enabled)
374 __psycho_check_one_stc(p, pbm, 1);
375
376 pbm = &p->pbm_B;
377 if (pbm->stc.strbuf_enabled)
378 __psycho_check_one_stc(p, pbm, 0);
379 }
380
381 /* When an Uncorrectable Error or a PCI Error happens, we
382 * interrogate the IOMMU state to see if it is the cause.
383 */
384 #define PSYCHO_IOMMU_CONTROL 0x0200UL
385 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
386 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
387 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
388 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
389 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
390 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
391 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
392 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
393 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
394 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
395 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
396 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
397 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
398 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
399 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
400 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
401 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
402 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
403 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
404 #define PSYCHO_IOMMU_FLUSH 0x0210UL
405 #define PSYCHO_IOMMU_TAG 0xa580UL
406 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
407 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
408 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
409 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
410 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
411 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
412 #define PSYCHO_IOMMU_DATA 0xa600UL
413 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
414 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
415 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
416 static void psycho_check_iommu_error(struct pci_controller_info *p,
417 unsigned long afsr,
418 unsigned long afar,
419 enum psycho_error_type type)
420 {
421 struct iommu *iommu = p->pbm_A.iommu;
422 unsigned long iommu_tag[16];
423 unsigned long iommu_data[16];
424 unsigned long flags;
425 u64 control;
426 int i;
427
428 spin_lock_irqsave(&iommu->lock, flags);
429 control = psycho_read(iommu->iommu_control);
430 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
431 char *type_string;
432
433 /* Clear the error encountered bit. */
434 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
435 psycho_write(iommu->iommu_control, control);
436
437 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
438 case 0:
439 type_string = "Protection Error";
440 break;
441 case 1:
442 type_string = "Invalid Error";
443 break;
444 case 2:
445 type_string = "TimeOut Error";
446 break;
447 case 3:
448 default:
449 type_string = "ECC Error";
450 break;
451 };
452 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
453 p->index, type_string);
454
455 /* Put the IOMMU into diagnostic mode and probe
456 * it's TLB for entries with error status.
457 *
458 * It is very possible for another DVMA to occur
459 * while we do this probe, and corrupt the system
460 * further. But we are so screwed at this point
461 * that we are likely to crash hard anyways, so
462 * get as much diagnostic information to the
463 * console as we can.
464 */
465 psycho_write(iommu->iommu_control,
466 control | PSYCHO_IOMMU_CTRL_DENAB);
467 for (i = 0; i < 16; i++) {
468 unsigned long base = p->pbm_A.controller_regs;
469
470 iommu_tag[i] =
471 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
472 iommu_data[i] =
473 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
474
475 /* Now clear out the entry. */
476 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
477 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
478 }
479
480 /* Leave diagnostic mode. */
481 psycho_write(iommu->iommu_control, control);
482
483 for (i = 0; i < 16; i++) {
484 unsigned long tag, data;
485
486 tag = iommu_tag[i];
487 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
488 continue;
489
490 data = iommu_data[i];
491 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
492 case 0:
493 type_string = "Protection Error";
494 break;
495 case 1:
496 type_string = "Invalid Error";
497 break;
498 case 2:
499 type_string = "TimeOut Error";
500 break;
501 case 3:
502 default:
503 type_string = "ECC Error";
504 break;
505 };
506 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
507 p->index, i, type_string,
508 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
509 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
510 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
511 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
512 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
513 p->index, i,
514 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
515 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
516 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
517 }
518 }
519 __psycho_check_stc_error(p, afsr, afar, type);
520 spin_unlock_irqrestore(&iommu->lock, flags);
521 }
522
523 /* Uncorrectable Errors. Cause of the error and the address are
524 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
525 * relating to UPA interface transactions.
526 */
527 #define PSYCHO_UE_AFSR 0x0030UL
528 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
529 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
530 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
531 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
532 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
533 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
534 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
535 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
536 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
537 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
538 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
539 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
540 #define PSYCHO_UE_AFAR 0x0038UL
541
542 static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
543 {
544 struct pci_controller_info *p = dev_id;
545 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR;
546 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR;
547 unsigned long afsr, afar, error_bits;
548 int reported;
549
550 /* Latch uncorrectable error status. */
551 afar = psycho_read(afar_reg);
552 afsr = psycho_read(afsr_reg);
553
554 /* Clear the primary/secondary error status bits. */
555 error_bits = afsr &
556 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
557 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
558 if (!error_bits)
559 return IRQ_NONE;
560 psycho_write(afsr_reg, error_bits);
561
562 /* Log the error. */
563 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
564 p->index,
565 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
566 "PIO" :
567 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
568 "DMA Read" :
569 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
570 "DMA Write" : "???")))));
571 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
572 p->index,
573 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
574 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
575 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
576 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
577 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
578 printk("PSYCHO%d: UE Secondary errors [", p->index);
579 reported = 0;
580 if (afsr & PSYCHO_UEAFSR_SPIO) {
581 reported++;
582 printk("(PIO)");
583 }
584 if (afsr & PSYCHO_UEAFSR_SDRD) {
585 reported++;
586 printk("(DMA Read)");
587 }
588 if (afsr & PSYCHO_UEAFSR_SDWR) {
589 reported++;
590 printk("(DMA Write)");
591 }
592 if (!reported)
593 printk("(none)");
594 printk("]\n");
595
596 /* Interrogate IOMMU for error status. */
597 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
598
599 return IRQ_HANDLED;
600 }
601
602 /* Correctable Errors. */
603 #define PSYCHO_CE_AFSR 0x0040UL
604 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
605 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
606 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
607 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
608 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
609 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
610 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
611 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
612 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
613 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
614 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
615 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
616 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
617 #define PSYCHO_CE_AFAR 0x0040UL
618
619 static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
620 {
621 struct pci_controller_info *p = dev_id;
622 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR;
623 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR;
624 unsigned long afsr, afar, error_bits;
625 int reported;
626
627 /* Latch error status. */
628 afar = psycho_read(afar_reg);
629 afsr = psycho_read(afsr_reg);
630
631 /* Clear primary/secondary error status bits. */
632 error_bits = afsr &
633 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
634 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
635 if (!error_bits)
636 return IRQ_NONE;
637 psycho_write(afsr_reg, error_bits);
638
639 /* Log the error. */
640 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
641 p->index,
642 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
643 "PIO" :
644 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
645 "DMA Read" :
646 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
647 "DMA Write" : "???")))));
648
649 /* XXX Use syndrome and afar to print out module string just like
650 * XXX UDB CE trap handler does... -DaveM
651 */
652 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
653 "UPA_MID[%02lx] was_block(%d)\n",
654 p->index,
655 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
656 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
657 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
658 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
659 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
660 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
661 printk("PSYCHO%d: CE Secondary errors [", p->index);
662 reported = 0;
663 if (afsr & PSYCHO_CEAFSR_SPIO) {
664 reported++;
665 printk("(PIO)");
666 }
667 if (afsr & PSYCHO_CEAFSR_SDRD) {
668 reported++;
669 printk("(DMA Read)");
670 }
671 if (afsr & PSYCHO_CEAFSR_SDWR) {
672 reported++;
673 printk("(DMA Write)");
674 }
675 if (!reported)
676 printk("(none)");
677 printk("]\n");
678
679 return IRQ_HANDLED;
680 }
681
682 /* PCI Errors. They are signalled by the PCI bus module since they
683 * are associated with a specific bus segment.
684 */
685 #define PSYCHO_PCI_AFSR_A 0x2010UL
686 #define PSYCHO_PCI_AFSR_B 0x4010UL
687 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
688 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
689 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
690 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
691 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
692 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
693 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
694 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
695 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
696 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
697 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
698 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
699 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
700 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
701 #define PSYCHO_PCI_AFAR_A 0x2018UL
702 #define PSYCHO_PCI_AFAR_B 0x4018UL
703
704 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
705 {
706 unsigned long csr_reg, csr, csr_error_bits;
707 irqreturn_t ret = IRQ_NONE;
708 u16 stat;
709
710 if (is_pbm_a) {
711 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
712 } else {
713 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
714 }
715 csr = psycho_read(csr_reg);
716 csr_error_bits =
717 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
718 if (csr_error_bits) {
719 /* Clear the errors. */
720 psycho_write(csr_reg, csr);
721
722 /* Log 'em. */
723 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
724 printk("%s: PCI streaming byte hole error asserted.\n",
725 pbm->name);
726 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
727 printk("%s: PCI SERR signal asserted.\n", pbm->name);
728 ret = IRQ_HANDLED;
729 }
730 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
731 if (stat & (PCI_STATUS_PARITY |
732 PCI_STATUS_SIG_TARGET_ABORT |
733 PCI_STATUS_REC_TARGET_ABORT |
734 PCI_STATUS_REC_MASTER_ABORT |
735 PCI_STATUS_SIG_SYSTEM_ERROR)) {
736 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
737 pbm->name, stat);
738 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
739 ret = IRQ_HANDLED;
740 }
741 return ret;
742 }
743
744 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
745 {
746 struct pci_pbm_info *pbm = dev_id;
747 struct pci_controller_info *p = pbm->parent;
748 unsigned long afsr_reg, afar_reg;
749 unsigned long afsr, afar, error_bits;
750 int is_pbm_a, reported;
751
752 is_pbm_a = (pbm == &pbm->parent->pbm_A);
753 if (is_pbm_a) {
754 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
755 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
756 } else {
757 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
758 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
759 }
760
761 /* Latch error status. */
762 afar = psycho_read(afar_reg);
763 afsr = psycho_read(afsr_reg);
764
765 /* Clear primary/secondary error status bits. */
766 error_bits = afsr &
767 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
768 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
769 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
770 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
771 if (!error_bits)
772 return psycho_pcierr_intr_other(pbm, is_pbm_a);
773 psycho_write(afsr_reg, error_bits);
774
775 /* Log the error. */
776 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
777 p->index, (is_pbm_a ? 'A' : 'B'),
778 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
779 "Master Abort" :
780 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
781 "Target Abort" :
782 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
783 "Excessive Retries" :
784 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
785 "Parity Error" : "???"))))));
786 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
787 p->index, (is_pbm_a ? 'A' : 'B'),
788 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
789 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
790 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
791 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
792 p->index, (is_pbm_a ? 'A' : 'B'), afar);
793 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
794 p->index, (is_pbm_a ? 'A' : 'B'));
795 reported = 0;
796 if (afsr & PSYCHO_PCIAFSR_SMA) {
797 reported++;
798 printk("(Master Abort)");
799 }
800 if (afsr & PSYCHO_PCIAFSR_STA) {
801 reported++;
802 printk("(Target Abort)");
803 }
804 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
805 reported++;
806 printk("(Excessive Retries)");
807 }
808 if (afsr & PSYCHO_PCIAFSR_SPERR) {
809 reported++;
810 printk("(Parity Error)");
811 }
812 if (!reported)
813 printk("(none)");
814 printk("]\n");
815
816 /* For the error types shown, scan PBM's PCI bus for devices
817 * which have logged that error type.
818 */
819
820 /* If we see a Target Abort, this could be the result of an
821 * IOMMU translation error of some sort. It is extremely
822 * useful to log this information as usually it indicates
823 * a bug in the IOMMU support code or a PCI device driver.
824 */
825 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
826 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
827 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
828 }
829 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
830 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
831
832 /* For excessive retries, PSYCHO/PBM will abort the device
833 * and there is no way to specifically check for excessive
834 * retries in the config space status registers. So what
835 * we hope is that we'll catch it via the master/target
836 * abort events.
837 */
838
839 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
840 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
841
842 return IRQ_HANDLED;
843 }
844
845 /* XXX What about PowerFail/PowerManagement??? -DaveM */
846 #define PSYCHO_ECC_CTRL 0x0020
847 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
848 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
849 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
850 static void psycho_register_error_handlers(struct pci_controller_info *p)
851 {
852 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
853 struct of_device *op = of_find_device_by_node(pbm->prom_node);
854 unsigned long base = p->pbm_A.controller_regs;
855 u64 tmp;
856
857 if (!op)
858 return;
859
860 /* Psycho interrupt property order is:
861 * 0: PCIERR PBM B INO
862 * 1: UE ERR
863 * 2: CE ERR
864 * 3: POWER FAIL
865 * 4: SPARE HARDWARE
866 * 5: PCIERR PBM A INO
867 */
868
869 if (op->num_irqs < 6)
870 return;
871
872 request_irq(op->irqs[1], psycho_ue_intr, IRQF_SHARED, "PSYCHO UE", p);
873 request_irq(op->irqs[2], psycho_ce_intr, IRQF_SHARED, "PSYCHO CE", p);
874 request_irq(op->irqs[5], psycho_pcierr_intr, IRQF_SHARED,
875 "PSYCHO PCIERR-A", &p->pbm_A);
876 request_irq(op->irqs[0], psycho_pcierr_intr, IRQF_SHARED,
877 "PSYCHO PCIERR-B", &p->pbm_B);
878
879 /* Enable UE and CE interrupts for controller. */
880 psycho_write(base + PSYCHO_ECC_CTRL,
881 (PSYCHO_ECCCTRL_EE |
882 PSYCHO_ECCCTRL_UE |
883 PSYCHO_ECCCTRL_CE));
884
885 /* Enable PCI Error interrupts and clear error
886 * bits for each PBM.
887 */
888 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
889 tmp |= (PSYCHO_PCICTRL_SERR |
890 PSYCHO_PCICTRL_SBH_ERR |
891 PSYCHO_PCICTRL_EEN);
892 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
893 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
894
895 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
896 tmp |= (PSYCHO_PCICTRL_SERR |
897 PSYCHO_PCICTRL_SBH_ERR |
898 PSYCHO_PCICTRL_EEN);
899 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
900 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
901 }
902
903 /* PSYCHO boot time probing and initialization. */
904 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
905 {
906 u8 *addr;
907
908 /* Set cache-line size to 64 bytes, this is actually
909 * a nop but I do it for completeness.
910 */
911 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
912 0, PCI_CACHE_LINE_SIZE);
913 pci_config_write8(addr, 64 / sizeof(u32));
914
915 /* Set PBM latency timer to 64 PCI clocks. */
916 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
917 0, PCI_LATENCY_TIMER);
918 pci_config_write8(addr, 64);
919 }
920
921 static void pbm_scan_bus(struct pci_controller_info *p,
922 struct pci_pbm_info *pbm)
923 {
924 pbm->pci_bus = pci_scan_one_pbm(pbm);
925 }
926
927 static void psycho_scan_bus(struct pci_controller_info *p)
928 {
929 pbm_config_busmastering(&p->pbm_B);
930 p->pbm_B.is_66mhz_capable = 0;
931 pbm_config_busmastering(&p->pbm_A);
932 p->pbm_A.is_66mhz_capable = 1;
933 pbm_scan_bus(p, &p->pbm_B);
934 pbm_scan_bus(p, &p->pbm_A);
935
936 /* After the PCI bus scan is complete, we can register
937 * the error interrupt handlers.
938 */
939 psycho_register_error_handlers(p);
940 }
941
942 static void psycho_iommu_init(struct pci_controller_info *p)
943 {
944 struct iommu *iommu = p->pbm_A.iommu;
945 unsigned long i;
946 u64 control;
947
948 /* Register addresses. */
949 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
950 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
951 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
952 /* PSYCHO's IOMMU lacks ctx flushing. */
953 iommu->iommu_ctxflush = 0;
954
955 /* We use the main control register of PSYCHO as the write
956 * completion register.
957 */
958 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
959
960 /*
961 * Invalidate TLB Entries.
962 */
963 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
964 control |= PSYCHO_IOMMU_CTRL_DENAB;
965 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
966 for(i = 0; i < 16; i++) {
967 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
968 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
969 }
970
971 /* Leave diag mode enabled for full-flushing done
972 * in pci_iommu.c
973 */
974 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
975
976 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
977 __pa(iommu->page_table));
978
979 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
980 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
981 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
982 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
983
984 /* If necessary, hook us up for starfire IRQ translations. */
985 if (this_is_starfire)
986 starfire_hookup(p->pbm_A.portid);
987 }
988
989 #define PSYCHO_IRQ_RETRY 0x1a00UL
990 #define PSYCHO_PCIA_DIAG 0x2020UL
991 #define PSYCHO_PCIB_DIAG 0x4020UL
992 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
993 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
994 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
995 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
996 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
997 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
998 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
999 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
1000
1001 static void psycho_controller_hwinit(struct pci_controller_info *p)
1002 {
1003 u64 tmp;
1004
1005 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1006
1007 /* Enable arbiter for all PCI slots. */
1008 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
1009 tmp |= PSYCHO_PCICTRL_AEN;
1010 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
1011
1012 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1013 tmp |= PSYCHO_PCICTRL_AEN;
1014 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1015
1016 /* Disable DMA write / PIO read synchronization on
1017 * both PCI bus segments.
1018 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1019 */
1020 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1021 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1022 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1023
1024 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1025 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1026 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1027 }
1028
1029 static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1030 struct pci_pbm_info *pbm,
1031 int is_pbm_a)
1032 {
1033 unsigned long base = pbm->controller_regs;
1034 u64 control;
1035
1036 if (is_pbm_a) {
1037 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1038 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1039 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1040 } else {
1041 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1042 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1043 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1044 }
1045 /* PSYCHO's streaming buffer lacks ctx flushing. */
1046 pbm->stc.strbuf_ctxflush = 0;
1047 pbm->stc.strbuf_ctxmatch_base = 0;
1048
1049 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1050 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1051 + 63UL)
1052 & ~63UL);
1053 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1054 __pa(pbm->stc.strbuf_flushflag);
1055
1056 /* Enable the streaming buffer. We have to be careful
1057 * just in case OBP left it with LRU locking enabled.
1058 *
1059 * It is possible to control if PBM will be rerun on
1060 * line misses. Currently I just retain whatever setting
1061 * OBP left us with. All checks so far show it having
1062 * a value of zero.
1063 */
1064 #undef PSYCHO_STRBUF_RERUN_ENABLE
1065 #undef PSYCHO_STRBUF_RERUN_DISABLE
1066 control = psycho_read(pbm->stc.strbuf_control);
1067 control |= PSYCHO_STRBUF_CTRL_ENAB;
1068 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1069 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1070 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1071 #else
1072 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1073 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1074 #endif
1075 #endif
1076 psycho_write(pbm->stc.strbuf_control, control);
1077
1078 pbm->stc.strbuf_enabled = 1;
1079 }
1080
1081 #define PSYCHO_IOSPACE_A 0x002000000UL
1082 #define PSYCHO_IOSPACE_B 0x002010000UL
1083 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1084 #define PSYCHO_MEMSPACE_A 0x100000000UL
1085 #define PSYCHO_MEMSPACE_B 0x180000000UL
1086 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1087
1088 static void psycho_pbm_init(struct pci_controller_info *p,
1089 struct device_node *dp, int is_pbm_a)
1090 {
1091 struct property *prop;
1092 struct pci_pbm_info *pbm;
1093
1094 if (is_pbm_a)
1095 pbm = &p->pbm_A;
1096 else
1097 pbm = &p->pbm_B;
1098
1099 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
1100 pbm->chip_version = 0;
1101 prop = of_find_property(dp, "version#", NULL);
1102 if (prop)
1103 pbm->chip_version = *(int *) prop->value;
1104 pbm->chip_revision = 0;
1105 prop = of_find_property(dp, "module-revision#", NULL);
1106 if (prop)
1107 pbm->chip_revision = *(int *) prop->value;
1108
1109 pbm->parent = p;
1110 pbm->prom_node = dp;
1111 pbm->name = dp->full_name;
1112
1113 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1114 pbm->name,
1115 pbm->chip_version, pbm->chip_revision);
1116
1117 pci_determine_mem_io_space(pbm);
1118
1119 pci_get_pbm_props(pbm);
1120
1121 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1122 }
1123
1124 #define PSYCHO_CONFIGSPACE 0x001000000UL
1125
1126 void psycho_init(struct device_node *dp, char *model_name)
1127 {
1128 struct linux_prom64_registers *pr_regs;
1129 struct pci_controller_info *p;
1130 struct iommu *iommu;
1131 struct property *prop;
1132 u32 upa_portid;
1133 int is_pbm_a;
1134
1135 upa_portid = 0xff;
1136 prop = of_find_property(dp, "upa-portid", NULL);
1137 if (prop)
1138 upa_portid = *(u32 *) prop->value;
1139
1140 for(p = pci_controller_root; p; p = p->next) {
1141 if (p->pbm_A.portid == upa_portid) {
1142 is_pbm_a = (p->pbm_A.prom_node == NULL);
1143 psycho_pbm_init(p, dp, is_pbm_a);
1144 return;
1145 }
1146 }
1147
1148 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1149 if (!p) {
1150 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1151 prom_halt();
1152 }
1153 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1154 if (!iommu) {
1155 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1156 prom_halt();
1157 }
1158 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1159
1160 p->next = pci_controller_root;
1161 pci_controller_root = p;
1162
1163 p->pbm_A.portid = upa_portid;
1164 p->pbm_B.portid = upa_portid;
1165 p->index = pci_num_controllers++;
1166 p->scan_bus = psycho_scan_bus;
1167 p->pci_ops = &psycho_ops;
1168
1169 prop = of_find_property(dp, "reg", NULL);
1170 pr_regs = prop->value;
1171
1172 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1173 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1174
1175 p->pbm_A.config_space = p->pbm_B.config_space =
1176 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1177
1178 /*
1179 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1180 * we need to adjust our MEM space mask.
1181 */
1182 pci_memspace_mask = 0x7fffffffUL;
1183
1184 psycho_controller_hwinit(p);
1185
1186 psycho_iommu_init(p);
1187
1188 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1189 psycho_pbm_init(p, dp, is_pbm_a);
1190 }
Linux kernel - Deliverables
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